/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family * of PCI-SCSI IO processors. * * Copyright (C) 1999-2001 Gerard Roudier <[email protected]> * * This driver is derived from the Linux sym53c8xx driver. * Copyright (C) 1998-2000 Gerard Roudier * * The sym53c8xx driver is derived from the ncr53c8xx driver that had been * a port of the FreeBSD ncr driver to Linux-1.2.13. * * The original ncr driver has been written for 386bsd and FreeBSD by * Wolfgang Stanglmeier <[email protected]> * Stefan Esser <[email protected]> * Copyright (C) 1994 Wolfgang Stanglmeier * * Other major contributions: * * NVRAM detection and reading. * Copyright (C) 1997 Richard Waltham <[email protected]> * *----------------------------------------------------------------------------- */ #ifndef SYM_DEFS_H #define SYM_DEFS_H #define SYM_VERSION … #define SYM_DRIVER_NAME … /* * SYM53C8XX device features descriptor. */ struct sym_chip { … }; /* * SYM53C8XX IO register data structure. */ struct sym_reg { … }; /*----------------------------------------------------------- * * Utility macros for the script. * *----------------------------------------------------------- */ #define REGJ(p,r) … #define REG(r) … /*----------------------------------------------------------- * * SCSI phases * *----------------------------------------------------------- */ #define SCR_DATA_OUT … #define SCR_DATA_IN … #define SCR_COMMAND … #define SCR_STATUS … #define SCR_DT_DATA_OUT … #define SCR_DT_DATA_IN … #define SCR_MSG_OUT … #define SCR_MSG_IN … /* DT phases are illegal for non Ultra3 mode */ #define SCR_ILG_OUT … #define SCR_ILG_IN … /*----------------------------------------------------------- * * Data transfer via SCSI. * *----------------------------------------------------------- * * MOVE_ABS (LEN) * <<start address>> * * MOVE_IND (LEN) * <<dnad_offset>> * * MOVE_TBL * <<dnad_offset>> * *----------------------------------------------------------- */ #define OPC_MOVE … #define SCR_MOVE_ABS(l) … /* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */ #define SCR_MOVE_TBL … #define SCR_CHMOV_ABS(l) … /* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */ #define SCR_CHMOV_TBL … #ifdef SYM_CONF_TARGET_ROLE_SUPPORT /* We steal the `indirect addressing' flag for target mode MOVE in scripts */ #define OPC_TCHMOVE … #define SCR_TCHMOVE_ABS … #define SCR_TCHMOVE_TBL … #define SCR_TMOV_ABS … #define SCR_TMOV_TBL … #endif struct sym_tblmove { … }; /*----------------------------------------------------------- * * Selection * *----------------------------------------------------------- * * SEL_ABS | SCR_ID (0..15) [ | REL_JMP] * <<alternate_address>> * * SEL_TBL | << dnad_offset>> [ | REL_JMP] * <<alternate_address>> * *----------------------------------------------------------- */ #define SCR_SEL_ABS … #define SCR_SEL_ABS_ATN … #define SCR_SEL_TBL … #define SCR_SEL_TBL_ATN … #ifdef SYM_CONF_TARGET_ROLE_SUPPORT #define SCR_RESEL_ABS … #define SCR_RESEL_ABS_ATN … #define SCR_RESEL_TBL … #define SCR_RESEL_TBL_ATN … #endif struct sym_tblsel { … }; #define SCR_JMP_REL … #define SCR_ID(id) … /*----------------------------------------------------------- * * Waiting for Disconnect or Reselect * *----------------------------------------------------------- * * WAIT_DISC * dummy: <<alternate_address>> * * WAIT_RESEL * <<alternate_address>> * *----------------------------------------------------------- */ #define SCR_WAIT_DISC … #define SCR_WAIT_RESEL … #ifdef SYM_CONF_TARGET_ROLE_SUPPORT #define SCR_DISCONNECT … #endif /*----------------------------------------------------------- * * Bit Set / Reset * *----------------------------------------------------------- * * SET (flags {|.. }) * * CLR (flags {|.. }) * *----------------------------------------------------------- */ #define SCR_SET(f) … #define SCR_CLR(f) … #define SCR_CARRY … #define SCR_TRG … #define SCR_ACK … #define SCR_ATN … /*----------------------------------------------------------- * * Memory to memory move * *----------------------------------------------------------- * * COPY (bytecount) * << source_address >> * << destination_address >> * * SCR_COPY sets the NO FLUSH option by default. * SCR_COPY_F does not set this option. * * For chips which do not support this option, * sym_fw_bind_script() will remove this bit. * *----------------------------------------------------------- */ #define SCR_NO_FLUSH … #define SCR_COPY(n) … #define SCR_COPY_F(n) … /*----------------------------------------------------------- * * Register move and binary operations * *----------------------------------------------------------- * * SFBR_REG (reg, op, data) reg = SFBR op data * << 0 >> * * REG_SFBR (reg, op, data) SFBR = reg op data * << 0 >> * * REG_REG (reg, op, data) reg = reg op data * << 0 >> * *----------------------------------------------------------- * * On 825A, 875, 895 and 896 chips the content * of SFBR register can be used as data (SCR_SFBR_DATA). * The 896 has additionnal IO registers starting at * offset 0x80. Bit 7 of register offset is stored in * bit 7 of the SCRIPTS instruction first DWORD. * *----------------------------------------------------------- */ #define SCR_REG_OFS(ofs) … #define SCR_SFBR_REG(reg,op,data) … #define SCR_REG_SFBR(reg,op,data) … #define SCR_REG_REG(reg,op,data) … #define SCR_LOAD … #define SCR_SHL … #define SCR_OR … #define SCR_XOR … #define SCR_AND … #define SCR_SHR … #define SCR_ADD … #define SCR_ADDC … #define SCR_SFBR_DATA … /*----------------------------------------------------------- * * FROM_REG (reg) SFBR = reg * << 0 >> * * TO_REG (reg) reg = SFBR * << 0 >> * * LOAD_REG (reg, data) reg = <data> * << 0 >> * * LOAD_SFBR(data) SFBR = <data> * << 0 >> * *----------------------------------------------------------- */ #define SCR_FROM_REG(reg) … #define SCR_TO_REG(reg) … #define SCR_LOAD_REG(reg,data) … #define SCR_LOAD_SFBR(data) … /*----------------------------------------------------------- * * LOAD from memory to register. * STORE from register to memory. * * Only supported by 810A, 860, 825A, 875, 895 and 896. * *----------------------------------------------------------- * * LOAD_ABS (LEN) * <<start address>> * * LOAD_REL (LEN) (DSA relative) * <<dsa_offset>> * *----------------------------------------------------------- */ #define SCR_REG_OFS2(ofs) … #define SCR_NO_FLUSH2 … #define SCR_DSA_REL2 … #define SCR_LOAD_R(reg, how, n) … #define SCR_STORE_R(reg, how, n) … #define SCR_LOAD_ABS(reg, n) … #define SCR_LOAD_REL(reg, n) … #define SCR_LOAD_ABS_F(reg, n) … #define SCR_LOAD_REL_F(reg, n) … #define SCR_STORE_ABS(reg, n) … #define SCR_STORE_REL(reg, n) … #define SCR_STORE_ABS_F(reg, n) … #define SCR_STORE_REL_F(reg, n) … /*----------------------------------------------------------- * * Waiting for Disconnect or Reselect * *----------------------------------------------------------- * * JUMP [ | IFTRUE/IFFALSE ( ... ) ] * <<address>> * * JUMPR [ | IFTRUE/IFFALSE ( ... ) ] * <<distance>> * * CALL [ | IFTRUE/IFFALSE ( ... ) ] * <<address>> * * CALLR [ | IFTRUE/IFFALSE ( ... ) ] * <<distance>> * * RETURN [ | IFTRUE/IFFALSE ( ... ) ] * <<dummy>> * * INT [ | IFTRUE/IFFALSE ( ... ) ] * <<ident>> * * INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] * <<ident>> * * Conditions: * WHEN (phase) * IF (phase) * CARRYSET * DATA (data, mask) * *----------------------------------------------------------- */ #define SCR_NO_OP … #define SCR_JUMP … #define SCR_JUMP64 … #define SCR_JUMPR … #define SCR_CALL … #define SCR_CALLR … #define SCR_RETURN … #define SCR_INT … #define SCR_INT_FLY … #define IFFALSE(arg) … #define IFTRUE(arg) … #define WHEN(phase) … #define IF(phase) … #define DATA(D) … #define MASK(D,M) … #define CARRYSET … /*----------------------------------------------------------- * * SCSI constants. * *----------------------------------------------------------- */ /* * Messages */ #define M_COMPLETE … #define M_EXTENDED … #define M_SAVE_DP … #define M_RESTORE_DP … #define M_DISCONNECT … #define M_ID_ERROR … #define M_ABORT … #define M_REJECT … #define M_NOOP … #define M_PARITY … #define M_LCOMPLETE … #define M_FCOMPLETE … #define M_RESET … #define M_ABORT_TAG … #define M_CLEAR_QUEUE … #define M_INIT_REC … #define M_REL_REC … #define M_TERMINATE … #define M_SIMPLE_TAG … #define M_HEAD_TAG … #define M_ORDERED_TAG … #define M_IGN_RESIDUE … #define M_X_MODIFY_DP … #define M_X_SYNC_REQ … #define M_X_WIDE_REQ … #define M_X_PPR_REQ … /* * PPR protocol options */ #define PPR_OPT_IU … #define PPR_OPT_DT … #define PPR_OPT_QAS … #define PPR_OPT_MASK … /* * Status */ #define S_GOOD … #define S_CHECK_COND … #define S_COND_MET … #define S_BUSY … #define S_INT … #define S_INT_COND_MET … #define S_CONFLICT … #define S_TERMINATED … #define S_QUEUE_FULL … #define S_ILLEGAL … #endif /* defined SYM_DEFS_H */
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