#ifndef MPI2_IOC_H
#define MPI2_IOC_H
pMpi2IOCInitRequest_t;
#define MPI2_WHOINIT_NOT_INITIALIZED …
#define MPI2_WHOINIT_SYSTEM_BIOS …
#define MPI2_WHOINIT_ROM_BIOS …
#define MPI2_WHOINIT_PCI_PEER …
#define MPI2_WHOINIT_HOST_DRIVER …
#define MPI2_WHOINIT_MANUFACTURER …
#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE …
#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK …
#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT …
#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK …
#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT …
#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK …
#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT …
#define MPI2_IOCINIT_HDRVERSION_DEV_MASK …
#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT …
#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT …
#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE …
#define MPI2_RDPQ_DEPTH_MIN …
pMpi2IOCInitRDPQArrayEntry;
pMpi2IOCInitReply_t;
pMpi2IOCFactsRequest_t;
pMpi2IOCFactsReply_t;
#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK …
#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT …
#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK …
#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT …
#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK …
#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT …
#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK …
#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT …
#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED …
#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE …
#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX …
#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK …
#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD …
#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP …
#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED …
#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP …
#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED …
#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL …
#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL …
#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID …
#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL …
#define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED …
#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV …
#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ …
#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE …
#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE …
#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY …
#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX …
#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR …
#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY …
#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID …
#define MPI2_IOCFACTS_CAPABILITY_TLR …
#define MPI2_IOCFACTS_CAPABILITY_MULTICAST …
#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET …
#define MPI2_IOCFACTS_CAPABILITY_EEDP …
#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER …
#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER …
#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER …
#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING …
#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES …
#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR …
#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET …
pMpi2PortFactsRequest_t;
pMpi2PortFactsReply_t;
#define MPI2_PORTFACTS_PORTTYPE_INACTIVE …
#define MPI2_PORTFACTS_PORTTYPE_FC …
#define MPI2_PORTFACTS_PORTTYPE_ISCSI …
#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL …
#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL …
#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE …
pMpi2PortEnableRequest_t;
pMpi2PortEnableReply_t;
#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS …
pMpi2EventNotificationRequest_t;
pMpi2EventNotificationReply_t;
#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED …
#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED …
#define MPI2_EVENT_LOG_DATA …
#define MPI2_EVENT_STATE_CHANGE …
#define MPI2_EVENT_HARD_RESET_RECEIVED …
#define MPI2_EVENT_EVENT_CHANGE …
#define MPI2_EVENT_TASK_SET_FULL …
#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE …
#define MPI2_EVENT_IR_OPERATION_STATUS …
#define MPI2_EVENT_SAS_DISCOVERY …
#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE …
#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE …
#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW …
#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST …
#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE …
#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE …
#define MPI2_EVENT_IR_VOLUME …
#define MPI2_EVENT_IR_PHYSICAL_DISK …
#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST …
#define MPI2_EVENT_LOG_ENTRY_ADDED …
#define MPI2_EVENT_SAS_PHY_COUNTER …
#define MPI2_EVENT_GPIO_INTERRUPT …
#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY …
#define MPI2_EVENT_SAS_QUIESCE …
#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE …
#define MPI2_EVENT_TEMP_THRESHOLD …
#define MPI2_EVENT_HOST_MESSAGE …
#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE …
#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE …
#define MPI2_EVENT_PCIE_ENUMERATION …
#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST …
#define MPI2_EVENT_PCIE_LINK_COUNTER …
#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION …
#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR …
#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC …
#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC …
#define MPI2_EVENT_DATA_LOG_DATA_LENGTH …
pMpi2EventDataLogEntryAdded_t;
pMpi2EventDataGpioInterrupt_t;
pMpi2EventDataTemperature_t;
#define MPI2_EVENT_TEMPERATURE3_EXCEEDED …
#define MPI2_EVENT_TEMPERATURE2_EXCEEDED …
#define MPI2_EVENT_TEMPERATURE1_EXCEEDED …
#define MPI2_EVENT_TEMPERATURE0_EXCEEDED …
pMpi2EventDataHostMessage_t;
pMpi2EventDataPowerPerfChange_t;
#define MPI2_EVENT_PM_INIT_MASK …
#define MPI2_EVENT_PM_INIT_UNAVAILABLE …
#define MPI2_EVENT_PM_INIT_HOST …
#define MPI2_EVENT_PM_INIT_IO_UNIT …
#define MPI2_EVENT_PM_INIT_PCIE_DPA …
#define MPI2_EVENT_PM_MODE_MASK …
#define MPI2_EVENT_PM_MODE_UNAVAILABLE …
#define MPI2_EVENT_PM_MODE_UNKNOWN …
#define MPI2_EVENT_PM_MODE_FULL_POWER …
#define MPI2_EVENT_PM_MODE_REDUCED_POWER …
#define MPI2_EVENT_PM_MODE_STANDBY …
pMpi26EventDataActiveCableExcept_t;
#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER …
#define MPI25_EVENT_ACTIVE_CABLE_PRESENT …
#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED …
#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER …
#define MPI26_EVENT_ACTIVE_CABLE_PRESENT …
#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED …
pMpi2EventDataHardResetReceived_t;
pMpi2EventDataTaskSetFull_t;
pMpi2EventDataSasDeviceStatusChange_t;
#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA …
#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED …
#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET …
#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL …
#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL …
#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL …
#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL …
#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION …
#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET …
#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL …
#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE …
#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY …
#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY …
pMpi2EventDataIrOperationStatus_t;
#define MPI2_EVENT_IR_RAIDOP_RESYNC …
#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION …
#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK …
#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT …
#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT …
pMpi2EventDataIrVolume_t;
#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED …
#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED …
#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED …
pMpi2EventDataIrPhysicalDisk_t;
#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED …
#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED …
#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED …
pMpi2EventIrConfigElement_t;
#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK …
#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT …
#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT …
#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT …
#define MPI2_EVENT_IR_CHANGE_RC_ADDED …
#define MPI2_EVENT_IR_CHANGE_RC_REMOVED …
#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE …
#define MPI2_EVENT_IR_CHANGE_RC_HIDE …
#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE …
#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED …
#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED …
#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED …
#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED …
pMpi2EventDataIrConfigChangeList_t;
#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG …
pMpi2EventDataSasDiscovery_t;
#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE …
#define MPI2_EVENT_SAS_DISC_IN_PROGRESS …
#define MPI2_EVENT_SAS_DISC_RC_STARTED …
#define MPI2_EVENT_SAS_DISC_RC_COMPLETED …
#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED …
#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED …
#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED …
#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED …
#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR …
#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE …
#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE …
#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN …
#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK …
#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE …
#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK …
#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK …
#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR …
#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED …
#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST …
#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES …
#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT …
#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS …
#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE …
#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED …
pMpi2EventDataSasBroadcastPrimitive_t;
#define MPI2_EVENT_PRIMITIVE_CHANGE …
#define MPI2_EVENT_PRIMITIVE_SES …
#define MPI2_EVENT_PRIMITIVE_EXPANDER …
#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT …
#define MPI2_EVENT_PRIMITIVE_RESERVED3 …
#define MPI2_EVENT_PRIMITIVE_RESERVED4 …
#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED …
#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED …
pMpi2EventDataSasNotifyPrimitive_t;
#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP …
#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED …
#define MPI2_EVENT_NOTIFY_RESERVED1 …
#define MPI2_EVENT_NOTIFY_RESERVED2 …
pMpi2EventDataSasInitDevStatusChange_t;
#define MPI2_EVENT_SAS_INIT_RC_ADDED …
#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING …
pMpi2EventDataSasInitTableOverflow_t;
pMpi2EventSasTopoPhyEntry_t;
pMpi2EventDataSasTopologyChangeList_t;
#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER …
#define MPI2_EVENT_SAS_TOPO_ES_ADDED …
#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING …
#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING …
#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING …
#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK …
#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT …
#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK …
#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT …
#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE …
#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED …
#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED …
#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE …
#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR …
#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS …
#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY …
#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 …
#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 …
#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 …
#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 …
#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 …
#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT …
#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE …
#define MPI2_EVENT_SAS_TOPO_RC_MASK …
#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED …
#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING …
#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED …
#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE …
#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING …
pMpi26EventDataEnclDevStatusChange_t;
#define MPI2_EVENT_SAS_ENCL_RC_ADDED …
#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING …
#define MPI26_EVENT_ENCL_RC_ADDED …
#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING …
pMpi25EventDataSasDeviceDiscoveryError_t;
#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED …
#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT …
pMpi2EventDataSasPhyCounter_t;
pMpi2EventDataSasQuiesce_t;
#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED …
#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED …
pMpi2EventHbdPhySas_t;
#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID …
#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME …
pMpi2EventHbdDescriptor_t;
pMpi2EventDataMpi2EventDataHbdPhy_t;
#define MPI2_EVENT_HBD_DT_SAS …
pMpi26EventDataPCIeDeviceStatusChange_t;
#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA …
#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED …
#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET …
#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL …
#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL …
#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL …
#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL …
#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION …
#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET …
#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL …
#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE …
#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED …
pMpi26EventDataPCIeEnumeration_t;
#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE …
#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS …
#define MPI26_EVENT_PCIE_ENUM_RC_STARTED …
#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED …
#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED …
#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED …
#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED …
pMpi26EventPCIeTopoPortEntry_t;
#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED …
#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING …
#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED …
#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE …
#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING …
#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK …
#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN …
#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE …
#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES …
#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES …
#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES …
#define MPI26_EVENT_PCIE_TOPO_PI_16_LANES …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 …
#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 …
pMpi26EventDataPCIeTopologyChangeList_t;
#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH …
#define MPI26_EVENT_PCIE_TOPO_SS_ADDED …
#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING …
#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING …
#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING …
pMpi26EventDataPcieLinkCounter_t;
pMpi2EventAckRequest_t;
pMpi2EventAckReply_t;
pMpi2SendHostMessageRequest_t;
pMpi2SendHostMessageReply_t;
pMpi2FWDownloadRequest;
#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT …
#define MPI2_FW_DOWNLOAD_ITYPE_FW …
#define MPI2_FW_DOWNLOAD_ITYPE_BIOS …
#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING …
#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 …
#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 …
#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID …
#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE …
#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK …
#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY …
#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP …
#define MPI2_FW_DOWNLOAD_ITYPE_SBR …
#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP …
#define MPI2_FW_DOWNLOAD_ITYPE_HIIM …
#define MPI2_FW_DOWNLOAD_ITYPE_HIIA …
#define MPI2_FW_DOWNLOAD_ITYPE_CTLR …
#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE …
#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA …
#define MPI2_FW_DOWNLOAD_ITYPE_CPLD …
#define MPI2_FW_DOWNLOAD_ITYPE_PSOC …
#define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP …
#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC …
pMpi2FWDownloadTCSGE_t;
pMpi25FWDownloadRequest;
pMpi2FWDownloadReply_t;
pMpi2FWUploadRequest_t;
#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT …
#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH …
#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH …
#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP …
#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING …
#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 …
#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 …
#define MPI2_FW_UPLOAD_ITYPE_MEGARAID …
#define MPI2_FW_UPLOAD_ITYPE_COMPLETE …
#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK …
#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP …
#define MPI2_FW_UPLOAD_ITYPE_SBR …
#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP …
#define MPI2_FW_UPLOAD_ITYPE_HIIM …
#define MPI2_FW_UPLOAD_ITYPE_HIIA …
#define MPI2_FW_UPLOAD_ITYPE_CTLR …
#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE …
#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA …
pMpi2FWUploadTCSGE_t;
pMpi25FWUploadRequest_t;
pMPi2FWUploadReply_t;
pMpi2PwrMgmtControlRequest_t;
#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND …
#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION …
#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK …
#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED …
#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE …
#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC …
#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC …
#define MPI2_PM_CONTROL_PARAM2_PARTIAL …
#define MPI2_PM_CONTROL_PARAM2_SLUMBER …
#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT …
#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP …
#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION …
#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP …
#define MPI2_PM_CONTROL_PARAM3_25_PERCENT …
#define MPI2_PM_CONTROL_PARAM3_50_PERCENT …
#define MPI2_PM_CONTROL_PARAM3_75_PERCENT …
#define MPI2_PM_CONTROL_PARAM3_100_PERCENT …
#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS …
#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS …
#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS …
#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 …
#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 …
#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 …
#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 …
#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED …
#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED …
#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED …
#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED …
#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL …
#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE …
#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL …
#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF …
#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF …
#define MPI2_PM_CONTROL_PARAM2_STANDBY …
pMpi2PwrMgmtControlReply_t;
pMpi26IoUnitControlRequest_t;
#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT …
#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET …
#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET …
#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG …
#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG …
#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE …
#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY …
#define MPI26_CTRL_OP_REMOVE_DEVICE …
#define MPI26_CTRL_OP_LOOKUP_MAPPING …
#define MPI26_CTRL_OP_SET_IOC_PARAMETER …
#define MPI26_CTRL_OP_ENABLE_FP_DEVICE …
#define MPI26_CTRL_OP_DISABLE_FP_DEVICE …
#define MPI26_CTRL_OP_ENABLE_FP_ALL …
#define MPI26_CTRL_OP_DISABLE_FP_ALL …
#define MPI26_CTRL_OP_DEV_ENABLE_NCQ …
#define MPI26_CTRL_OP_DEV_DISABLE_NCQ …
#define MPI26_CTRL_OP_SHUTDOWN …
#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION …
#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION …
#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION …
#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT …
#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT …
#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN …
#define MPI26_CTRL_PRIMFLAGS_SINGLE …
#define MPI26_CTRL_PRIMFLAGS_TRIPLE …
#define MPI26_CTRL_PRIMFLAGS_REDUNDANT …
#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS …
#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT …
#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME …
pMpi26IoUnitControlReply_t;
#endif