/* SPDX-License-Identifier: GPL-2.0-only */ /* * Core driver interface to access RICOH_RC5T583 power management chip. * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * Author: Laxman dewangan <[email protected]> * * Based on code * Copyright (C) 2011 RICOH COMPANY,LTD */ #ifndef __LINUX_MFD_RC5T583_H #define __LINUX_MFD_RC5T583_H #include <linux/mutex.h> #include <linux/types.h> #include <linux/regmap.h> /* Maximum number of main interrupts */ #define MAX_MAIN_INTERRUPT … #define RC5T583_MAX_GPEDGE_REG … #define RC5T583_MAX_INTERRUPT_EN_REGS … #define RC5T583_MAX_INTERRUPT_MASK_REGS … /* Interrupt enable register */ #define RC5T583_INT_EN_SYS1 … #define RC5T583_INT_EN_SYS2 … #define RC5T583_INT_EN_DCDC … #define RC5T583_INT_EN_RTC … #define RC5T583_INT_EN_ADC1 … #define RC5T583_INT_EN_ADC2 … #define RC5T583_INT_EN_ADC3 … /* Interrupt status registers (monitor regs in Ricoh)*/ #define RC5T583_INTC_INTPOL … #define RC5T583_INTC_INTEN … #define RC5T583_INTC_INTMON … #define RC5T583_INT_MON_GRP … #define RC5T583_INT_MON_SYS1 … #define RC5T583_INT_MON_SYS2 … #define RC5T583_INT_MON_DCDC … #define RC5T583_INT_MON_RTC … /* Interrupt clearing registers */ #define RC5T583_INT_IR_SYS1 … #define RC5T583_INT_IR_SYS2 … #define RC5T583_INT_IR_DCDC … #define RC5T583_INT_IR_RTC … #define RC5T583_INT_IR_ADCL … #define RC5T583_INT_IR_ADCH … #define RC5T583_INT_IR_ADCEND … #define RC5T583_INT_IR_GPIOR … #define RC5T583_INT_IR_GPIOF … /* Sleep sequence registers */ #define RC5T583_SLPSEQ1 … #define RC5T583_SLPSEQ2 … #define RC5T583_SLPSEQ3 … #define RC5T583_SLPSEQ4 … #define RC5T583_SLPSEQ5 … #define RC5T583_SLPSEQ6 … #define RC5T583_SLPSEQ7 … #define RC5T583_SLPSEQ8 … #define RC5T583_SLPSEQ9 … #define RC5T583_SLPSEQ10 … #define RC5T583_SLPSEQ11 … /* Regulator registers */ #define RC5T583_REG_DC0CTL … #define RC5T583_REG_DC0DAC … #define RC5T583_REG_DC0LATCTL … #define RC5T583_REG_SR0CTL … #define RC5T583_REG_DC1CTL … #define RC5T583_REG_DC1DAC … #define RC5T583_REG_DC1LATCTL … #define RC5T583_REG_SR1CTL … #define RC5T583_REG_DC2CTL … #define RC5T583_REG_DC2DAC … #define RC5T583_REG_DC2LATCTL … #define RC5T583_REG_SR2CTL … #define RC5T583_REG_DC3CTL … #define RC5T583_REG_DC3DAC … #define RC5T583_REG_DC3LATCTL … #define RC5T583_REG_SR3CTL … #define RC5T583_REG_LDOEN1 … #define RC5T583_REG_LDOEN2 … #define RC5T583_REG_LDODIS1 … #define RC5T583_REG_LDODIS2 … #define RC5T583_REG_LDO0DAC … #define RC5T583_REG_LDO1DAC … #define RC5T583_REG_LDO2DAC … #define RC5T583_REG_LDO3DAC … #define RC5T583_REG_LDO4DAC … #define RC5T583_REG_LDO5DAC … #define RC5T583_REG_LDO6DAC … #define RC5T583_REG_LDO7DAC … #define RC5T583_REG_LDO8DAC … #define RC5T583_REG_LDO9DAC … #define RC5T583_REG_DC0DAC_DS … #define RC5T583_REG_DC1DAC_DS … #define RC5T583_REG_DC2DAC_DS … #define RC5T583_REG_DC3DAC_DS … #define RC5T583_REG_LDO0DAC_DS … #define RC5T583_REG_LDO1DAC_DS … #define RC5T583_REG_LDO2DAC_DS … #define RC5T583_REG_LDO3DAC_DS … #define RC5T583_REG_LDO4DAC_DS … #define RC5T583_REG_LDO5DAC_DS … #define RC5T583_REG_LDO6DAC_DS … #define RC5T583_REG_LDO7DAC_DS … #define RC5T583_REG_LDO8DAC_DS … #define RC5T583_REG_LDO9DAC_DS … /* GPIO register base address */ #define RC5T583_GPIO_IOSEL … #define RC5T583_GPIO_PDEN … #define RC5T583_GPIO_IOOUT … #define RC5T583_GPIO_PGSEL … #define RC5T583_GPIO_GPINV … #define RC5T583_GPIO_GPDEB … #define RC5T583_GPIO_GPEDGE1 … #define RC5T583_GPIO_GPEDGE2 … #define RC5T583_GPIO_EN_INT … #define RC5T583_GPIO_MON_IOIN … #define RC5T583_GPIO_GPOFUNC … /* RTC registers */ #define RC5T583_RTC_SEC … #define RC5T583_RTC_MIN … #define RC5T583_RTC_HOUR … #define RC5T583_RTC_WDAY … #define RC5T583_RTC_DAY … #define RC5T583_RTC_MONTH … #define RC5T583_RTC_YEAR … #define RC5T583_RTC_ADJ … #define RC5T583_RTC_AW_MIN … #define RC5T583_RTC_AW_HOUR … #define RC5T583_RTC_AW_WEEK … #define RC5T583_RTC_AD_MIN … #define RC5T583_RTC_AD_HOUR … #define RC5T583_RTC_CTL1 … #define RC5T583_RTC_CTL2 … #define RC5T583_RTC_AY_MIN … #define RC5T583_RTC_AY_HOUR … #define RC5T583_RTC_AY_DAY … #define RC5T583_RTC_AY_MONTH … #define RC5T583_RTC_AY_YEAR … #define RC5T583_MAX_REG … #define RC5T583_NUM_REGS … /* RICOH_RC5T583 IRQ definitions */ enum { … }; /* Ricoh583 gpio definitions */ enum { … }; enum { … }; /* * Ricoh pmic RC5T583 supports sleep through two external controls. * The output of gpios and regulator can be enable/disable through * this external signals. */ enum { … }; enum { … }; struct rc5t583 { … }; /* * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. * The board specific data is provided through this structure. * @irq_base: Irq base number on which this device registers their interrupts. * @gpio_base: GPIO base from which gpio of this device will start. * @enable_shutdown: Enable shutdown through the input pin "shutdown". * @regulator_deepsleep_slot: The slot number on which device goes to sleep * in device sleep mode. * @regulator_ext_pwr_control: External power request regulator control. The * regulator output enable/disable is controlled by the external * power request input state. * @reg_init_data: Regulator init data. */ struct rc5t583_platform_data { … }; static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) { … } static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) { … } static inline int rc5t583_set_bits(struct device *dev, unsigned int reg, unsigned int bit_mask) { … } static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg, unsigned int bit_mask) { … } static inline int rc5t583_update(struct device *dev, unsigned int reg, unsigned int val, unsigned int mask) { … } int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id, int ext_pwr_req, int deepsleep_slot_nr); int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base); int rc5t583_irq_exit(struct rc5t583 *rc5t583); #endif
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