// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2015 Linaro Ltd. * Copyright (c) 2015 Hisilicon Limited. */ #include "hisi_sas.h" #define DRV_NAME … /* global registers need init*/ #define DLVRY_QUEUE_ENABLE … #define IOST_BASE_ADDR_LO … #define IOST_BASE_ADDR_HI … #define ITCT_BASE_ADDR_LO … #define ITCT_BASE_ADDR_HI … #define BROKEN_MSG_ADDR_LO … #define BROKEN_MSG_ADDR_HI … #define PHY_CONTEXT … #define PHY_STATE … #define PHY_PORT_NUM_MA … #define PORT_STATE … #define PHY_CONN_RATE … #define HGC_TRANS_TASK_CNT_LIMIT … #define AXI_AHB_CLK_CFG … #define HGC_SAS_TXFAIL_RETRY_CTRL … #define HGC_GET_ITV_TIME … #define DEVICE_MSG_WORK_MODE … #define I_T_NEXUS_LOSS_TIME … #define BUS_INACTIVE_LIMIT_TIME … #define REJECT_TO_OPEN_LIMIT_TIME … #define CFG_AGING_TIME … #define CFG_AGING_TIME_ITCT_REL_OFF … #define CFG_AGING_TIME_ITCT_REL_MSK … #define HGC_DFX_CFG2 … #define FIS_LIST_BADDR_L … #define CFG_1US_TIMER_TRSH … #define CFG_SAS_CONFIG … #define HGC_IOST_ECC_ADDR … #define HGC_IOST_ECC_ADDR_BAD_OFF … #define HGC_IOST_ECC_ADDR_BAD_MSK … #define HGC_DQ_ECC_ADDR … #define HGC_DQ_ECC_ADDR_BAD_OFF … #define HGC_DQ_ECC_ADDR_BAD_MSK … #define HGC_INVLD_DQE_INFO … #define HGC_INVLD_DQE_INFO_DQ_OFF … #define HGC_INVLD_DQE_INFO_DQ_MSK … #define HGC_INVLD_DQE_INFO_TYPE_OFF … #define HGC_INVLD_DQE_INFO_TYPE_MSK … #define HGC_INVLD_DQE_INFO_FORCE_OFF … #define HGC_INVLD_DQE_INFO_FORCE_MSK … #define HGC_INVLD_DQE_INFO_PHY_OFF … #define HGC_INVLD_DQE_INFO_PHY_MSK … #define HGC_INVLD_DQE_INFO_ABORT_OFF … #define HGC_INVLD_DQE_INFO_ABORT_MSK … #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF … #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK … #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF … #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK … #define HGC_INVLD_DQE_INFO_OFL_OFF … #define HGC_INVLD_DQE_INFO_OFL_MSK … #define HGC_ITCT_ECC_ADDR … #define HGC_ITCT_ECC_ADDR_BAD_OFF … #define HGC_ITCT_ECC_ADDR_BAD_MSK … #define HGC_AXI_FIFO_ERR_INFO … #define INT_COAL_EN … #define OQ_INT_COAL_TIME … #define OQ_INT_COAL_CNT … #define ENT_INT_COAL_TIME … #define ENT_INT_COAL_CNT … #define OQ_INT_SRC … #define OQ_INT_SRC_MSK … #define ENT_INT_SRC1 … #define ENT_INT_SRC2 … #define ENT_INT_SRC2_DQ_CFG_ERR_OFF … #define ENT_INT_SRC2_DQ_CFG_ERR_MSK … #define ENT_INT_SRC2_CQ_CFG_ERR_OFF … #define ENT_INT_SRC2_CQ_CFG_ERR_MSK … #define ENT_INT_SRC2_AXI_WRONG_INT_OFF … #define ENT_INT_SRC2_AXI_WRONG_INT_MSK … #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF … #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK … #define ENT_INT_SRC_MSK1 … #define ENT_INT_SRC_MSK2 … #define SAS_ECC_INTR … #define SAS_ECC_INTR_DQ_ECC1B_OFF … #define SAS_ECC_INTR_DQ_ECC1B_MSK … #define SAS_ECC_INTR_DQ_ECCBAD_OFF … #define SAS_ECC_INTR_DQ_ECCBAD_MSK … #define SAS_ECC_INTR_IOST_ECC1B_OFF … #define SAS_ECC_INTR_IOST_ECC1B_MSK … #define SAS_ECC_INTR_IOST_ECCBAD_OFF … #define SAS_ECC_INTR_IOST_ECCBAD_MSK … #define SAS_ECC_INTR_ITCT_ECC1B_OFF … #define SAS_ECC_INTR_ITCT_ECC1B_MSK … #define SAS_ECC_INTR_ITCT_ECCBAD_OFF … #define SAS_ECC_INTR_ITCT_ECCBAD_MSK … #define SAS_ECC_INTR_MSK … #define HGC_ERR_STAT_EN … #define DLVRY_Q_0_BASE_ADDR_LO … #define DLVRY_Q_0_BASE_ADDR_HI … #define DLVRY_Q_0_DEPTH … #define DLVRY_Q_0_WR_PTR … #define DLVRY_Q_0_RD_PTR … #define COMPL_Q_0_BASE_ADDR_LO … #define COMPL_Q_0_BASE_ADDR_HI … #define COMPL_Q_0_DEPTH … #define COMPL_Q_0_WR_PTR … #define COMPL_Q_0_RD_PTR … #define HGC_ECC_ERR … /* phy registers need init */ #define PORT_BASE … #define PHY_CFG … #define PHY_CFG_ENA_OFF … #define PHY_CFG_ENA_MSK … #define PHY_CFG_DC_OPT_OFF … #define PHY_CFG_DC_OPT_MSK … #define PROG_PHY_LINK_RATE … #define PROG_PHY_LINK_RATE_MAX_OFF … #define PROG_PHY_LINK_RATE_MAX_MSK … #define PROG_PHY_LINK_RATE_MIN_OFF … #define PROG_PHY_LINK_RATE_MIN_MSK … #define PROG_PHY_LINK_RATE_OOB_OFF … #define PROG_PHY_LINK_RATE_OOB_MSK … #define PHY_CTRL … #define PHY_CTRL_RESET_OFF … #define PHY_CTRL_RESET_MSK … #define PHY_RATE_NEGO … #define PHY_PCN … #define SL_TOUT_CFG … #define SL_CONTROL … #define SL_CONTROL_NOTIFY_EN_OFF … #define SL_CONTROL_NOTIFY_EN_MSK … #define TX_ID_DWORD0 … #define TX_ID_DWORD1 … #define TX_ID_DWORD2 … #define TX_ID_DWORD3 … #define TX_ID_DWORD4 … #define TX_ID_DWORD5 … #define TX_ID_DWORD6 … #define RX_IDAF_DWORD0 … #define RX_IDAF_DWORD1 … #define RX_IDAF_DWORD2 … #define RX_IDAF_DWORD3 … #define RX_IDAF_DWORD4 … #define RX_IDAF_DWORD5 … #define RX_IDAF_DWORD6 … #define RXOP_CHECK_CFG_H … #define DONE_RECEIVED_TIME … #define CON_CFG_DRIVER … #define PHY_CONFIG2 … #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF … #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK … #define PHY_CONFIG2_TX_TRAIN_COMP_OFF … #define PHY_CONFIG2_TX_TRAIN_COMP_MSK … #define CHL_INT0 … #define CHL_INT0_PHYCTRL_NOTRDY_OFF … #define CHL_INT0_PHYCTRL_NOTRDY_MSK … #define CHL_INT0_SN_FAIL_NGR_OFF … #define CHL_INT0_SN_FAIL_NGR_MSK … #define CHL_INT0_DWS_LOST_OFF … #define CHL_INT0_DWS_LOST_MSK … #define CHL_INT0_SL_IDAF_FAIL_OFF … #define CHL_INT0_SL_IDAF_FAIL_MSK … #define CHL_INT0_ID_TIMEOUT_OFF … #define CHL_INT0_ID_TIMEOUT_MSK … #define CHL_INT0_SL_OPAF_FAIL_OFF … #define CHL_INT0_SL_OPAF_FAIL_MSK … #define CHL_INT0_SL_PS_FAIL_OFF … #define CHL_INT0_SL_PS_FAIL_MSK … #define CHL_INT1 … #define CHL_INT2 … #define CHL_INT2_SL_RX_BC_ACK_OFF … #define CHL_INT2_SL_RX_BC_ACK_MSK … #define CHL_INT2_SL_PHY_ENA_OFF … #define CHL_INT2_SL_PHY_ENA_MSK … #define CHL_INT0_MSK … #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF … #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK … #define CHL_INT1_MSK … #define CHL_INT2_MSK … #define CHL_INT_COAL_EN … #define DMA_TX_STATUS … #define DMA_TX_STATUS_BUSY_OFF … #define DMA_TX_STATUS_BUSY_MSK … #define DMA_RX_STATUS … #define DMA_RX_STATUS_BUSY_OFF … #define DMA_RX_STATUS_BUSY_MSK … #define AXI_CFG … #define RESET_VALUE … /* HW dma structures */ /* Delivery queue header */ /* dw0 */ #define CMD_HDR_RESP_REPORT_OFF … #define CMD_HDR_RESP_REPORT_MSK … #define CMD_HDR_TLR_CTRL_OFF … #define CMD_HDR_TLR_CTRL_MSK … #define CMD_HDR_PORT_OFF … #define CMD_HDR_PORT_MSK … #define CMD_HDR_PRIORITY_OFF … #define CMD_HDR_PRIORITY_MSK … #define CMD_HDR_MODE_OFF … #define CMD_HDR_MODE_MSK … #define CMD_HDR_CMD_OFF … #define CMD_HDR_CMD_MSK … /* dw1 */ #define CMD_HDR_VERIFY_DTL_OFF … #define CMD_HDR_VERIFY_DTL_MSK … #define CMD_HDR_SSP_FRAME_TYPE_OFF … #define CMD_HDR_SSP_FRAME_TYPE_MSK … #define CMD_HDR_DEVICE_ID_OFF … #define CMD_HDR_DEVICE_ID_MSK … /* dw2 */ #define CMD_HDR_CFL_OFF … #define CMD_HDR_CFL_MSK … #define CMD_HDR_MRFL_OFF … #define CMD_HDR_MRFL_MSK … #define CMD_HDR_FIRST_BURST_OFF … #define CMD_HDR_FIRST_BURST_MSK … /* dw3 */ #define CMD_HDR_IPTT_OFF … #define CMD_HDR_IPTT_MSK … /* dw6 */ #define CMD_HDR_DATA_SGL_LEN_OFF … #define CMD_HDR_DATA_SGL_LEN_MSK … /* Completion header */ #define CMPLT_HDR_IPTT_OFF … #define CMPLT_HDR_IPTT_MSK … #define CMPLT_HDR_CMD_CMPLT_OFF … #define CMPLT_HDR_CMD_CMPLT_MSK … #define CMPLT_HDR_ERR_RCRD_XFRD_OFF … #define CMPLT_HDR_ERR_RCRD_XFRD_MSK … #define CMPLT_HDR_RSPNS_XFRD_OFF … #define CMPLT_HDR_RSPNS_XFRD_MSK … #define CMPLT_HDR_IO_CFG_ERR_OFF … #define CMPLT_HDR_IO_CFG_ERR_MSK … /* ITCT header */ /* qw0 */ #define ITCT_HDR_DEV_TYPE_OFF … #define ITCT_HDR_DEV_TYPE_MSK … #define ITCT_HDR_VALID_OFF … #define ITCT_HDR_VALID_MSK … #define ITCT_HDR_AWT_CONTROL_OFF … #define ITCT_HDR_AWT_CONTROL_MSK … #define ITCT_HDR_MAX_CONN_RATE_OFF … #define ITCT_HDR_MAX_CONN_RATE_MSK … #define ITCT_HDR_VALID_LINK_NUM_OFF … #define ITCT_HDR_VALID_LINK_NUM_MSK … #define ITCT_HDR_PORT_ID_OFF … #define ITCT_HDR_PORT_ID_MSK … #define ITCT_HDR_SMP_TIMEOUT_OFF … #define ITCT_HDR_SMP_TIMEOUT_MSK … /* qw1 */ #define ITCT_HDR_MAX_SAS_ADDR_OFF … #define ITCT_HDR_MAX_SAS_ADDR_MSK … /* qw2 */ #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF … #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK … #define ITCT_HDR_BUS_INACTIVE_TL_OFF … #define ITCT_HDR_BUS_INACTIVE_TL_MSK … #define ITCT_HDR_MAX_CONN_TL_OFF … #define ITCT_HDR_MAX_CONN_TL_MSK … #define ITCT_HDR_REJ_OPEN_TL_OFF … #define ITCT_HDR_REJ_OPEN_TL_MSK … /* Err record header */ #define ERR_HDR_DMA_TX_ERR_TYPE_OFF … #define ERR_HDR_DMA_TX_ERR_TYPE_MSK … #define ERR_HDR_DMA_RX_ERR_TYPE_OFF … #define ERR_HDR_DMA_RX_ERR_TYPE_MSK … struct hisi_sas_complete_v1_hdr { … }; struct hisi_sas_err_record_v1 { … }; enum { … }; enum { … }; #define HISI_SAS_PHY_MAX_INT_NR … #define HISI_SAS_CQ_MAX_INT_NR … #define HISI_SAS_FATAL_INT_NR … #define HISI_SAS_MAX_INT_NR … static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { … } static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { … } static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, u32 off, u32 val) { … } static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, int phy_no, u32 off) { … } static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static int clear_itct_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) { … } static void init_reg_v1_hw(struct hisi_hba *hisi_hba) { … } static int hw_init_v1_hw(struct hisi_hba *hisi_hba) { … } static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void start_phys_v1_hw(struct timer_list *t) { … } static void phys_init_v1_hw(struct hisi_hba *hisi_hba) { … } static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static enum sas_linkrate phy_get_max_linkrate_v1_hw(void) { … } static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no, struct sas_phy_linkrates *r) { … } static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) { … } /* DQ lock must be taken here */ static void start_delivery_v1_hw(struct hisi_sas_dq *dq) { … } static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, struct hisi_sas_cmd_hdr *hdr, struct scatterlist *scatter, int n_elem) { … } static void prep_smp_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } /* by default, task resp is complete */ static void slot_err_v1_hw(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot) { … } static void slot_complete_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } /* Interrupts */ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) { … } static irqreturn_t int_bcast_v1_hw(int irq, void *p) { … } static irqreturn_t int_abnormal_v1_hw(int irq, void *p) { … } static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) { … } static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) { … } static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) { … } static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = …; static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = …; static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) { … } static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) { … } static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) { … } static struct attribute *host_v1_hw_attrs[] = …; ATTRIBUTE_GROUPS(…); static const struct scsi_host_template sht_v1_hw = …; static const struct hisi_sas_hw hisi_sas_v1_hw = …; static int hisi_sas_v1_probe(struct platform_device *pdev) { … } static const struct of_device_id sas_v1_of_match[] = …; MODULE_DEVICE_TABLE(of, sas_v1_of_match); static const struct acpi_device_id sas_v1_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); static struct platform_driver hisi_sas_v1_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_ALIAS(…) …;
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