// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2016 Linaro Ltd. * Copyright (c) 2016 Hisilicon Limited. */ #include "hisi_sas.h" #define DRV_NAME … /* global registers need init*/ #define DLVRY_QUEUE_ENABLE … #define IOST_BASE_ADDR_LO … #define IOST_BASE_ADDR_HI … #define ITCT_BASE_ADDR_LO … #define ITCT_BASE_ADDR_HI … #define IO_BROKEN_MSG_ADDR_LO … #define IO_BROKEN_MSG_ADDR_HI … #define PHY_CONTEXT … #define PHY_STATE … #define PHY_PORT_NUM_MA … #define PORT_STATE … #define PORT_STATE_PHY8_PORT_NUM_OFF … #define PORT_STATE_PHY8_PORT_NUM_MSK … #define PORT_STATE_PHY8_CONN_RATE_OFF … #define PORT_STATE_PHY8_CONN_RATE_MSK … #define PHY_CONN_RATE … #define HGC_TRANS_TASK_CNT_LIMIT … #define AXI_AHB_CLK_CFG … #define ITCT_CLR … #define ITCT_CLR_EN_OFF … #define ITCT_CLR_EN_MSK … #define ITCT_DEV_OFF … #define ITCT_DEV_MSK … #define AXI_USER1 … #define AXI_USER2 … #define IO_SATA_BROKEN_MSG_ADDR_LO … #define IO_SATA_BROKEN_MSG_ADDR_HI … #define SATA_INITI_D2H_STORE_ADDR_LO … #define SATA_INITI_D2H_STORE_ADDR_HI … #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL … #define HGC_SAS_TXFAIL_RETRY_CTRL … #define HGC_GET_ITV_TIME … #define DEVICE_MSG_WORK_MODE … #define OPENA_WT_CONTI_TIME … #define I_T_NEXUS_LOSS_TIME … #define MAX_CON_TIME_LIMIT_TIME … #define BUS_INACTIVE_LIMIT_TIME … #define REJECT_TO_OPEN_LIMIT_TIME … #define CFG_AGING_TIME … #define HGC_DFX_CFG2 … #define HGC_IOMB_PROC1_STATUS … #define CFG_1US_TIMER_TRSH … #define HGC_LM_DFX_STATUS2 … #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF … #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK … #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF … #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK … #define HGC_CQE_ECC_ADDR … #define HGC_CQE_ECC_1B_ADDR_OFF … #define HGC_CQE_ECC_1B_ADDR_MSK … #define HGC_CQE_ECC_MB_ADDR_OFF … #define HGC_CQE_ECC_MB_ADDR_MSK … #define HGC_IOST_ECC_ADDR … #define HGC_IOST_ECC_1B_ADDR_OFF … #define HGC_IOST_ECC_1B_ADDR_MSK … #define HGC_IOST_ECC_MB_ADDR_OFF … #define HGC_IOST_ECC_MB_ADDR_MSK … #define HGC_DQE_ECC_ADDR … #define HGC_DQE_ECC_1B_ADDR_OFF … #define HGC_DQE_ECC_1B_ADDR_MSK … #define HGC_DQE_ECC_MB_ADDR_OFF … #define HGC_DQE_ECC_MB_ADDR_MSK … #define HGC_INVLD_DQE_INFO … #define HGC_INVLD_DQE_INFO_FB_CH0_OFF … #define HGC_INVLD_DQE_INFO_FB_CH0_MSK … #define HGC_INVLD_DQE_INFO_FB_CH3_OFF … #define HGC_ITCT_ECC_ADDR … #define HGC_ITCT_ECC_1B_ADDR_OFF … #define HGC_ITCT_ECC_1B_ADDR_MSK … #define HGC_ITCT_ECC_MB_ADDR_OFF … #define HGC_ITCT_ECC_MB_ADDR_MSK … #define HGC_AXI_FIFO_ERR_INFO … #define AXI_ERR_INFO_OFF … #define AXI_ERR_INFO_MSK … #define FIFO_ERR_INFO_OFF … #define FIFO_ERR_INFO_MSK … #define INT_COAL_EN … #define OQ_INT_COAL_TIME … #define OQ_INT_COAL_CNT … #define ENT_INT_COAL_TIME … #define ENT_INT_COAL_CNT … #define OQ_INT_SRC … #define OQ_INT_SRC_MSK … #define ENT_INT_SRC1 … #define ENT_INT_SRC1_D2H_FIS_CH0_OFF … #define ENT_INT_SRC1_D2H_FIS_CH0_MSK … #define ENT_INT_SRC1_D2H_FIS_CH1_OFF … #define ENT_INT_SRC1_D2H_FIS_CH1_MSK … #define ENT_INT_SRC2 … #define ENT_INT_SRC3 … #define ENT_INT_SRC3_WP_DEPTH_OFF … #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF … #define ENT_INT_SRC3_RP_DEPTH_OFF … #define ENT_INT_SRC3_AXI_OFF … #define ENT_INT_SRC3_FIFO_OFF … #define ENT_INT_SRC3_LM_OFF … #define ENT_INT_SRC3_ITC_INT_OFF … #define ENT_INT_SRC3_ITC_INT_MSK … #define ENT_INT_SRC3_ABT_OFF … #define ENT_INT_SRC_MSK1 … #define ENT_INT_SRC_MSK2 … #define ENT_INT_SRC_MSK3 … #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF … #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK … #define SAS_ECC_INTR … #define SAS_ECC_INTR_DQE_ECC_1B_OFF … #define SAS_ECC_INTR_DQE_ECC_MB_OFF … #define SAS_ECC_INTR_IOST_ECC_1B_OFF … #define SAS_ECC_INTR_IOST_ECC_MB_OFF … #define SAS_ECC_INTR_ITCT_ECC_MB_OFF … #define SAS_ECC_INTR_ITCT_ECC_1B_OFF … #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF … #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF … #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF … #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF … #define SAS_ECC_INTR_CQE_ECC_1B_OFF … #define SAS_ECC_INTR_CQE_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF … #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF … #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF … #define SAS_ECC_INTR_MSK … #define HGC_ERR_STAT_EN … #define CQE_SEND_CNT … #define DLVRY_Q_0_BASE_ADDR_LO … #define DLVRY_Q_0_BASE_ADDR_HI … #define DLVRY_Q_0_DEPTH … #define DLVRY_Q_0_WR_PTR … #define DLVRY_Q_0_RD_PTR … #define HYPER_STREAM_ID_EN_CFG … #define OQ0_INT_SRC_MSK … #define COMPL_Q_0_BASE_ADDR_LO … #define COMPL_Q_0_BASE_ADDR_HI … #define COMPL_Q_0_DEPTH … #define COMPL_Q_0_WR_PTR … #define COMPL_Q_0_RD_PTR … #define HGC_RXM_DFX_STATUS14 … #define HGC_RXM_DFX_STATUS14_MEM0_OFF … #define HGC_RXM_DFX_STATUS14_MEM0_MSK … #define HGC_RXM_DFX_STATUS14_MEM1_OFF … #define HGC_RXM_DFX_STATUS14_MEM1_MSK … #define HGC_RXM_DFX_STATUS14_MEM2_OFF … #define HGC_RXM_DFX_STATUS14_MEM2_MSK … #define HGC_RXM_DFX_STATUS15 … #define HGC_RXM_DFX_STATUS15_MEM3_OFF … #define HGC_RXM_DFX_STATUS15_MEM3_MSK … /* phy registers need init */ #define PORT_BASE … #define PHY_CFG … #define HARD_PHY_LINKRATE … #define PHY_CFG_ENA_OFF … #define PHY_CFG_ENA_MSK … #define PHY_CFG_DC_OPT_OFF … #define PHY_CFG_DC_OPT_MSK … #define PROG_PHY_LINK_RATE … #define PROG_PHY_LINK_RATE_MAX_OFF … #define PROG_PHY_LINK_RATE_MAX_MSK … #define PHY_CTRL … #define PHY_CTRL_RESET_OFF … #define PHY_CTRL_RESET_MSK … #define SAS_PHY_CTRL … #define SL_CFG … #define PHY_PCN … #define SL_TOUT_CFG … #define SL_CONTROL … #define SL_CONTROL_NOTIFY_EN_OFF … #define SL_CONTROL_NOTIFY_EN_MSK … #define SL_CONTROL_CTA_OFF … #define SL_CONTROL_CTA_MSK … #define RX_PRIMS_STATUS … #define RX_BCAST_CHG_OFF … #define RX_BCAST_CHG_MSK … #define TX_ID_DWORD0 … #define TX_ID_DWORD1 … #define TX_ID_DWORD2 … #define TX_ID_DWORD3 … #define TX_ID_DWORD4 … #define TX_ID_DWORD5 … #define TX_ID_DWORD6 … #define TXID_AUTO … #define TXID_AUTO_CT3_OFF … #define TXID_AUTO_CT3_MSK … #define TXID_AUTO_CTB_OFF … #define TXID_AUTO_CTB_MSK … #define TX_HARDRST_OFF … #define TX_HARDRST_MSK … #define RX_IDAF_DWORD0 … #define RX_IDAF_DWORD1 … #define RX_IDAF_DWORD2 … #define RX_IDAF_DWORD3 … #define RX_IDAF_DWORD4 … #define RX_IDAF_DWORD5 … #define RX_IDAF_DWORD6 … #define RXOP_CHECK_CFG_H … #define CON_CONTROL … #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF … #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK … #define DONE_RECEIVED_TIME … #define CHL_INT0 … #define CHL_INT0_HOTPLUG_TOUT_OFF … #define CHL_INT0_HOTPLUG_TOUT_MSK … #define CHL_INT0_SL_RX_BCST_ACK_OFF … #define CHL_INT0_SL_RX_BCST_ACK_MSK … #define CHL_INT0_SL_PHY_ENABLE_OFF … #define CHL_INT0_SL_PHY_ENABLE_MSK … #define CHL_INT0_NOT_RDY_OFF … #define CHL_INT0_NOT_RDY_MSK … #define CHL_INT0_PHY_RDY_OFF … #define CHL_INT0_PHY_RDY_MSK … #define CHL_INT1 … #define CHL_INT1_DMAC_TX_ECC_ERR_OFF … #define CHL_INT1_DMAC_TX_ECC_ERR_MSK … #define CHL_INT1_DMAC_RX_ECC_ERR_OFF … #define CHL_INT1_DMAC_RX_ECC_ERR_MSK … #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF … #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF … #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF … #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF … #define CHL_INT2 … #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF … #define CHL_INT0_MSK … #define CHL_INT1_MSK … #define CHL_INT2_MSK … #define CHL_INT_COAL_EN … #define DMA_TX_DFX0 … #define DMA_TX_DFX1 … #define DMA_TX_DFX1_IPTT_OFF … #define DMA_TX_DFX1_IPTT_MSK … #define DMA_TX_FIFO_DFX0 … #define PORT_DFX0 … #define LINK_DFX2 … #define LINK_DFX2_RCVR_HOLD_STS_OFF … #define LINK_DFX2_RCVR_HOLD_STS_MSK … #define LINK_DFX2_SEND_HOLD_STS_OFF … #define LINK_DFX2_SEND_HOLD_STS_MSK … #define SAS_ERR_CNT4_REG … #define SAS_ERR_CNT6_REG … #define PHY_CTRL_RDY_MSK … #define PHYCTRL_NOT_RDY_MSK … #define PHYCTRL_DWS_RESET_MSK … #define PHYCTRL_PHY_ENA_MSK … #define SL_RX_BCAST_CHK_MSK … #define PHYCTRL_OOB_RESTART_MSK … #define DMA_TX_STATUS … #define DMA_TX_STATUS_BUSY_OFF … #define DMA_TX_STATUS_BUSY_MSK … #define DMA_RX_STATUS … #define DMA_RX_STATUS_BUSY_OFF … #define DMA_RX_STATUS_BUSY_MSK … #define AXI_CFG … #define AM_CFG_MAX_TRANS … #define AM_CFG_SINGLE_PORT_MAX_TRANS … #define AXI_MASTER_CFG_BASE … #define AM_CTRL_GLOBAL … #define AM_CURR_TRANS_RETURN … /* HW dma structures */ /* Delivery queue header */ /* dw0 */ #define CMD_HDR_ABORT_FLAG_OFF … #define CMD_HDR_ABORT_FLAG_MSK … #define CMD_HDR_ABORT_DEVICE_TYPE_OFF … #define CMD_HDR_ABORT_DEVICE_TYPE_MSK … #define CMD_HDR_RESP_REPORT_OFF … #define CMD_HDR_RESP_REPORT_MSK … #define CMD_HDR_TLR_CTRL_OFF … #define CMD_HDR_TLR_CTRL_MSK … #define CMD_HDR_PHY_ID_OFF … #define CMD_HDR_PHY_ID_MSK … #define CMD_HDR_FORCE_PHY_OFF … #define CMD_HDR_FORCE_PHY_MSK … #define CMD_HDR_PORT_OFF … #define CMD_HDR_PORT_MSK … #define CMD_HDR_PRIORITY_OFF … #define CMD_HDR_PRIORITY_MSK … #define CMD_HDR_CMD_OFF … #define CMD_HDR_CMD_MSK … /* dw1 */ #define CMD_HDR_DIR_OFF … #define CMD_HDR_DIR_MSK … #define CMD_HDR_RESET_OFF … #define CMD_HDR_RESET_MSK … #define CMD_HDR_VDTL_OFF … #define CMD_HDR_VDTL_MSK … #define CMD_HDR_FRAME_TYPE_OFF … #define CMD_HDR_FRAME_TYPE_MSK … #define CMD_HDR_DEV_ID_OFF … #define CMD_HDR_DEV_ID_MSK … /* dw2 */ #define CMD_HDR_CFL_OFF … #define CMD_HDR_CFL_MSK … #define CMD_HDR_NCQ_TAG_OFF … #define CMD_HDR_NCQ_TAG_MSK … #define CMD_HDR_MRFL_OFF … #define CMD_HDR_MRFL_MSK … #define CMD_HDR_SG_MOD_OFF … #define CMD_HDR_SG_MOD_MSK … #define CMD_HDR_FIRST_BURST_OFF … #define CMD_HDR_FIRST_BURST_MSK … /* dw3 */ #define CMD_HDR_IPTT_OFF … #define CMD_HDR_IPTT_MSK … /* dw6 */ #define CMD_HDR_DIF_SGL_LEN_OFF … #define CMD_HDR_DIF_SGL_LEN_MSK … #define CMD_HDR_DATA_SGL_LEN_OFF … #define CMD_HDR_DATA_SGL_LEN_MSK … #define CMD_HDR_ABORT_IPTT_OFF … #define CMD_HDR_ABORT_IPTT_MSK … /* Completion header */ /* dw0 */ #define CMPLT_HDR_ERR_PHASE_OFF … #define CMPLT_HDR_ERR_PHASE_MSK … #define CMPLT_HDR_RSPNS_XFRD_OFF … #define CMPLT_HDR_RSPNS_XFRD_MSK … #define CMPLT_HDR_ERX_OFF … #define CMPLT_HDR_ERX_MSK … #define CMPLT_HDR_ABORT_STAT_OFF … #define CMPLT_HDR_ABORT_STAT_MSK … /* abort_stat */ #define STAT_IO_NOT_VALID … #define STAT_IO_NO_DEVICE … #define STAT_IO_COMPLETE … #define STAT_IO_ABORTED … /* dw1 */ #define CMPLT_HDR_IPTT_OFF … #define CMPLT_HDR_IPTT_MSK … #define CMPLT_HDR_DEV_ID_OFF … #define CMPLT_HDR_DEV_ID_MSK … /* ITCT header */ /* qw0 */ #define ITCT_HDR_DEV_TYPE_OFF … #define ITCT_HDR_DEV_TYPE_MSK … #define ITCT_HDR_VALID_OFF … #define ITCT_HDR_VALID_MSK … #define ITCT_HDR_MCR_OFF … #define ITCT_HDR_MCR_MSK … #define ITCT_HDR_VLN_OFF … #define ITCT_HDR_VLN_MSK … #define ITCT_HDR_SMP_TIMEOUT_OFF … #define ITCT_HDR_SMP_TIMEOUT_8US … #define ITCT_HDR_SMP_TIMEOUT … #define ITCT_HDR_AWT_CONTINUE_OFF … #define ITCT_HDR_PORT_ID_OFF … #define ITCT_HDR_PORT_ID_MSK … /* qw2 */ #define ITCT_HDR_INLT_OFF … #define ITCT_HDR_INLT_MSK … #define ITCT_HDR_BITLT_OFF … #define ITCT_HDR_BITLT_MSK … #define ITCT_HDR_MCTLT_OFF … #define ITCT_HDR_MCTLT_MSK … #define ITCT_HDR_RTOLT_OFF … #define ITCT_HDR_RTOLT_MSK … #define HISI_SAS_FATAL_INT_NR … struct hisi_sas_complete_v2_hdr { … }; struct hisi_sas_err_record_v2 { … }; struct signal_attenuation_s { … }; struct sig_atten_lu_s { … }; static const struct hisi_sas_hw_error one_bit_ecc_errors[] = …; static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = …; enum { … }; enum { … }; #define HISI_SAS_COMMAND_ENTRIES_V2_HW … #define HISI_MAX_SATA_SUPPORT_V2_HW … #define DIR_NO_DATA … #define DIR_TO_INI … #define DIR_TO_DEVICE … #define DIR_RESERVED … #define ERR_ON_TX_PHASE(err_phase) … #define ERR_ON_RX_PHASE(err_phase) … static void link_timeout_disable_link(struct timer_list *t); static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { … } static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) { … } static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { … } static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, u32 off, u32 val) { … } static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, int phy_no, u32 off) { … } /* This function needs to be protected from pre-emption. */ static int slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, struct domain_device *device) { … } static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx) { … } static struct hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) { … } static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static int clear_itct_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_device *sas_dev) { … } static void free_device_v2_hw(struct hisi_sas_device *sas_dev) { … } static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) { … } /* This function needs to be called after resetting SAS controller. */ static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba) { … } static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba) { … } static const struct signal_attenuation_s x6000 = …; static const struct sig_atten_lu_s sig_atten_lu[] = …; static void init_reg_v2_hw(struct hisi_hba *hisi_hba) { … } static void link_timeout_enable_link(struct timer_list *t) { … } static void link_timeout_disable_link(struct timer_list *t) { … } static void set_link_timer_quirk(struct hisi_hba *hisi_hba) { … } static int hw_init_v2_hw(struct hisi_hba *hisi_hba) { … } static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static void phys_init_v2_hw(struct hisi_hba *hisi_hba) { … } static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no) { … } static enum sas_linkrate phy_get_max_linkrate_v2_hw(void) { … } static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no, struct sas_phy_linkrates *r) { … } static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) { … } /* DQ lock must be taken here */ static void start_delivery_v2_hw(struct hisi_sas_dq *dq) { … } static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, struct hisi_sas_cmd_hdr *hdr, struct scatterlist *scatter, int n_elem) { … } static void prep_smp_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } #define TRANS_TX_ERR … #define TRANS_RX_ERR … #define DMA_TX_ERR … #define SIPC_RX_ERR … #define DMA_RX_ERR … #define DMA_TX_ERR_OFF … #define DMA_TX_ERR_MSK … #define SIPC_RX_ERR_OFF … #define SIPC_RX_ERR_MSK … static int parse_trans_tx_err_code_v2_hw(u32 err_msk) { … } static int parse_trans_rx_err_code_v2_hw(u32 err_msk) { … } static int parse_dma_tx_err_code_v2_hw(u32 err_msk) { … } static int parse_sipc_rx_err_code_v2_hw(u32 err_msk) { … } static int parse_dma_rx_err_code_v2_hw(u32 err_msk) { … } /* by default, task resp is complete */ static void slot_err_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot, int err_phase) { … } static void slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void prep_ata_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t) { … } static void prep_abort_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) { … } static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba) { … } static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) { … } static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) { … } static const struct hisi_sas_hw_error port_ecc_axi_error[] = …; static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) { … } static void one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { … } static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) { … } static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p) { … } static const struct hisi_sas_hw_error axi_error[] = …; static const struct hisi_sas_hw_error fifo_error[] = …; static const struct hisi_sas_hw_error fatal_axi_errors[] = …; static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) { … } static irqreturn_t cq_thread_v2_hw(int irq_no, void *p) { … } static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) { … } static irqreturn_t sata_int_v2_hw(int irq_no, void *p) { … } static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = …; static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = …; #define CQ0_IRQ_INDEX … static int hisi_sas_v2_interrupt_preinit(struct hisi_hba *hisi_hba) { … } /* * There is a limitation in the hip06 chipset that we need * to map in all mbigen interrupts, even if they are not used. */ static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) { … } static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) { … } static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba) { … } static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba) { … } static int soft_reset_v2_hw(struct hisi_hba *hisi_hba) { … } static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type, u8 reg_index, u8 reg_count, u8 *write_data) { … } static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba, int delay_ms, int timeout_ms) { … } static struct attribute *host_v2_hw_attrs[] = …; ATTRIBUTE_GROUPS(…); static const struct attribute_group *sdev_groups_v2_hw[] = …; static void map_queues_v2_hw(struct Scsi_Host *shost) { … } static const struct scsi_host_template sht_v2_hw = …; static const struct hisi_sas_hw hisi_sas_v2_hw = …; static int hisi_sas_v2_probe(struct platform_device *pdev) { … } static const struct of_device_id sas_v2_of_match[] = …; MODULE_DEVICE_TABLE(of, sas_v2_of_match); static const struct acpi_device_id sas_v2_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match); static struct platform_driver hisi_sas_v2_driver = …; module_platform_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_ALIAS(…) …;
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