// SPDX-License-Identifier: GPL-2.0-or-later /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters * * Copyright (c) 1995-2000 Advanced System Products, Inc. * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. * Copyright (c) 2007 Matthew Wilcox <[email protected]> * Copyright (c) 2014 Hannes Reinecke <[email protected]> * All Rights Reserved. */ /* * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) * changed its name to ConnectCom Solutions, Inc. * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets */ #include <linux/module.h> #include <linux/string.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/ioport.h> #include <linux/interrupt.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/mm.h> #include <linux/proc_fs.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/isa.h> #include <linux/eisa.h> #include <linux/pci.h> #include <linux/spinlock.h> #include <linux/dma-mapping.h> #include <linux/firmware.h> #include <linux/dmapool.h> #include <asm/io.h> #include <asm/dma.h> #include <scsi/scsi_cmnd.h> #include <scsi/scsi_device.h> #include <scsi/scsi_tcq.h> #include <scsi/scsi.h> #include <scsi/scsi_host.h> #define DRV_NAME … #define ASC_VERSION … /* FIXME: * * 1. Use scsi_transport_spi * 2. advansys_info is not safe against multiple simultaneous callers * 3. Add module_param to override ISA/VLB ioport array */ /* Enable driver /proc statistics. */ #define ADVANSYS_STATS /* Enable driver tracing. */ #undef ADVANSYS_DEBUG uchar; #define isodd_word(val) … #define PCI_VENDOR_ID_ASP … #define PCI_DEVICE_ID_ASP_1200A … #define PCI_DEVICE_ID_ASP_ABP940 … #define PCI_DEVICE_ID_ASP_ABP940U … #define PCI_DEVICE_ID_ASP_ABP940UW … #define PCI_DEVICE_ID_38C0800_REV1 … #define PCI_DEVICE_ID_38C1600_REV1 … #define PortAddr … #define inp(port) … #define outp(port, byte) … #define inpw(port) … #define outpw(port, word) … #define ASC_MAX_SG_QUEUE … #define ASC_MAX_SG_LIST … #define ASC_CS_TYPE … #define ASC_IS_EISA … #define ASC_IS_PCI … #define ASC_IS_PCI_ULTRA … #define ASC_IS_PCMCIA … #define ASC_IS_MCA … #define ASC_IS_VL … #define ASC_IS_WIDESCSI_16 … #define ASC_IS_WIDESCSI_32 … #define ASC_IS_BIG_ENDIAN … #define ASC_CHIP_MIN_VER_VL … #define ASC_CHIP_MAX_VER_VL … #define ASC_CHIP_MIN_VER_PCI … #define ASC_CHIP_MAX_VER_PCI … #define ASC_CHIP_VER_PCI_BIT … #define ASC_CHIP_VER_ASYN_BUG … #define ASC_CHIP_VER_PCI … #define ASC_CHIP_VER_PCI_ULTRA_3150 … #define ASC_CHIP_VER_PCI_ULTRA_3050 … #define ASC_CHIP_MIN_VER_EISA … #define ASC_CHIP_MAX_VER_EISA … #define ASC_CHIP_VER_EISA_BIT … #define ASC_CHIP_LATEST_VER_EISA … #define ASC_MAX_VL_DMA_COUNT … #define ASC_MAX_PCI_DMA_COUNT … #define ASC_SCSI_ID_BITS … #define ASC_SCSI_TIX_TYPE … #define ASC_ALL_DEVICE_BIT_SET … #define ASC_SCSI_BIT_ID_TYPE … #define ASC_MAX_TID … #define ASC_MAX_LUN … #define ASC_SCSI_WIDTH_BIT_SET … #define ASC_MAX_SENSE_LEN … #define ASC_MIN_SENSE_LEN … #define ASC_SCSI_RESET_HOLD_TIME_US … /* * Narrow boards only support 12-byte commands, while wide boards * extend to 16-byte commands. */ #define ASC_MAX_CDB_LEN … #define ADV_MAX_CDB_LEN … #define MS_SDTR_LEN … #define MS_WDTR_LEN … #define ASC_SG_LIST_PER_Q … #define QS_FREE … #define QS_READY … #define QS_DISC1 … #define QS_DISC2 … #define QS_BUSY … #define QS_ABORTED … #define QS_DONE … #define QC_NO_CALLBACK … #define QC_SG_SWAP_QUEUE … #define QC_SG_HEAD … #define QC_DATA_IN … #define QC_DATA_OUT … #define QC_URGENT … #define QC_MSG_OUT … #define QC_REQ_SENSE … #define QCSG_SG_XFER_LIST … #define QCSG_SG_XFER_MORE … #define QCSG_SG_XFER_END … #define QD_IN_PROGRESS … #define QD_NO_ERROR … #define QD_ABORTED_BY_HOST … #define QD_WITH_ERROR … #define QD_INVALID_REQUEST … #define QD_INVALID_HOST_NUM … #define QD_INVALID_DEVICE … #define QD_ERR_INTERNAL … #define QHSTA_NO_ERROR … #define QHSTA_M_SEL_TIMEOUT … #define QHSTA_M_DATA_OVER_RUN … #define QHSTA_M_DATA_UNDER_RUN … #define QHSTA_M_UNEXPECTED_BUS_FREE … #define QHSTA_M_BAD_BUS_PHASE_SEQ … #define QHSTA_D_QDONE_SG_LIST_CORRUPTED … #define QHSTA_D_ASC_DVC_ERROR_CODE_SET … #define QHSTA_D_HOST_ABORT_FAILED … #define QHSTA_D_EXE_SCSI_Q_FAILED … #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT … #define QHSTA_D_ASPI_NO_BUF_POOL … #define QHSTA_M_WTM_TIMEOUT … #define QHSTA_M_BAD_CMPL_STATUS_IN … #define QHSTA_M_NO_AUTO_REQ_SENSE … #define QHSTA_M_AUTO_REQ_SENSE_FAIL … #define QHSTA_M_TARGET_STATUS_BUSY … #define QHSTA_M_BAD_TAG_CODE … #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY … #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET … #define QHSTA_D_LRAM_CMP_ERROR … #define QHSTA_M_MICRO_CODE_ERROR_HALT … #define ASC_FLAG_SCSIQ_REQ … #define ASC_FLAG_BIOS_SCSIQ_REQ … #define ASC_FLAG_BIOS_ASYNC_IO … #define ASC_FLAG_SRB_LINEAR_ADDR … #define ASC_FLAG_WIN16 … #define ASC_FLAG_WIN32 … #define ASC_FLAG_DOS_VM_CALLBACK … #define ASC_TAG_FLAG_EXTRA_BYTES … #define ASC_TAG_FLAG_DISABLE_DISCONNECT … #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX … #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST … #define ASC_SCSIQ_CPY_BEG … #define ASC_SCSIQ_SGHD_CPY_BEG … #define ASC_SCSIQ_B_FWD … #define ASC_SCSIQ_B_BWD … #define ASC_SCSIQ_B_STATUS … #define ASC_SCSIQ_B_QNO … #define ASC_SCSIQ_B_CNTL … #define ASC_SCSIQ_B_SG_QUEUE_CNT … #define ASC_SCSIQ_D_DATA_ADDR … #define ASC_SCSIQ_D_DATA_CNT … #define ASC_SCSIQ_B_SENSE_LEN … #define ASC_SCSIQ_DONE_INFO_BEG … #define ASC_SCSIQ_D_SRBPTR … #define ASC_SCSIQ_B_TARGET_IX … #define ASC_SCSIQ_B_CDB_LEN … #define ASC_SCSIQ_B_TAG_CODE … #define ASC_SCSIQ_W_VM_ID … #define ASC_SCSIQ_DONE_STATUS … #define ASC_SCSIQ_HOST_STATUS … #define ASC_SCSIQ_SCSI_STATUS … #define ASC_SCSIQ_CDB_BEG … #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR … #define ASC_SCSIQ_DW_REMAIN_XFER_CNT … #define ASC_SCSIQ_B_FIRST_SG_WK_QP … #define ASC_SCSIQ_B_SG_WK_QP … #define ASC_SCSIQ_B_SG_WK_IX … #define ASC_SCSIQ_W_ALT_DC1 … #define ASC_SCSIQ_B_LIST_CNT … #define ASC_SCSIQ_B_CUR_LIST_CNT … #define ASC_SGQ_B_SG_CNTL … #define ASC_SGQ_B_SG_HEAD_QP … #define ASC_SGQ_B_SG_LIST_CNT … #define ASC_SGQ_B_SG_CUR_LIST_CNT … #define ASC_SGQ_LIST_BEG … #define ASC_DEF_SCSI1_QNG … #define ASC_MAX_SCSI1_QNG … #define ASC_DEF_SCSI2_QNG … #define ASC_MAX_SCSI2_QNG … #define ASC_TAG_CODE_MASK … #define ASC_STOP_REQ_RISC_STOP … #define ASC_STOP_ACK_RISC_STOP … #define ASC_STOP_CLEAN_UP_BUSY_Q … #define ASC_STOP_CLEAN_UP_DISC_Q … #define ASC_STOP_HOST_REQ_RISC_HALT … #define ASC_TIDLUN_TO_IX(tid, lun) … #define ASC_TID_TO_TARGET_ID(tid) … #define ASC_TIX_TO_TARGET_ID(tix) … #define ASC_TIX_TO_TID(tix) … #define ASC_TID_TO_TIX(tid) … #define ASC_TIX_TO_LUN(tix) … #define ASC_QNO_TO_QADDR(q_no) … ASC_SCSIQ_1; ASC_SCSIQ_2; ASC_SCSIQ_3; ASC_SCSIQ_4; ASC_QDONE_INFO; ASC_SG_LIST; ASC_SG_HEAD; ASC_SCSI_Q; ASC_SCSI_BIOS_REQ_Q; ASC_RISC_Q; ASC_SG_LIST_Q; ASC_RISC_SG_LIST_Q; #define ASCQ_ERR_Q_STATUS … #define ASCQ_ERR_CUR_QNG … #define ASCQ_ERR_SG_Q_LINKS … #define ASCQ_ERR_ISR_RE_ENTRY … #define ASCQ_ERR_CRITICAL_RE_ENTRY … #define ASCQ_ERR_ISR_ON_CRITICAL … /* * Warning code values are set in ASC_DVC_VAR 'warn_code'. */ #define ASC_WARN_NO_ERROR … #define ASC_WARN_IO_PORT_ROTATE … #define ASC_WARN_EEPROM_CHKSUM … #define ASC_WARN_IRQ_MODIFIED … #define ASC_WARN_AUTO_CONFIG … #define ASC_WARN_CMD_QNG_CONFLICT … #define ASC_WARN_EEPROM_RECOVER … #define ASC_WARN_CFG_MSW_RECOVER … /* * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'. */ #define ASC_IERR_NO_CARRIER … #define ASC_IERR_MCODE_CHKSUM … #define ASC_IERR_SET_PC_ADDR … #define ASC_IERR_START_STOP_CHIP … #define ASC_IERR_ILLEGAL_CONNECTION … #define ASC_IERR_SINGLE_END_DEVICE … #define ASC_IERR_REVERSED_CABLE … #define ASC_IERR_SET_SCSI_ID … #define ASC_IERR_HVD_DEVICE … #define ASC_IERR_BAD_SIGNATURE … #define ASC_IERR_NO_BUS_TYPE … #define ASC_IERR_BIST_PRE_TEST … #define ASC_IERR_BIST_RAM_TEST … #define ASC_IERR_BAD_CHIPTYPE … #define ASC_DEF_MAX_TOTAL_QNG … #define ASC_MIN_TAG_Q_PER_DVC … #define ASC_MIN_FREE_Q … #define ASC_MIN_TOTAL_QNG … #define ASC_MAX_TOTAL_QNG … #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG … #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG … #define ASC_MAX_PCI_INRAM_TOTAL_QNG … #define ASC_MAX_INRAM_TAG_QNG … #define ASC_IOADR_GAP … #define ASC_SYN_MAX_OFFSET … #define ASC_DEF_SDTR_OFFSET … #define ASC_SDTR_ULTRA_PCI_10MB_INDEX … #define ASYN_SDTR_DATA_FIX_PCI_REV_AB … /* The narrow chip only supports a limited selection of transfer rates. * These are encoded in the range 0..7 or 0..15 depending whether the chip * is Ultra-capable or not. These tables let us convert from one to the other. */ static const unsigned char asc_syn_xfer_period[8] = …; static const unsigned char asc_syn_ultra_xfer_period[16] = …; EXT_MSG; #define xfer_period … #define req_ack_offset … #define wdtr_width … #define mdp_b3 … #define mdp_b2 … #define mdp_b1 … #define mdp_b0 … ASC_DVC_CFG; #define ASC_DEF_DVC_CNTL … #define ASC_DEF_CHIP_SCSI_ID … #define ASC_DEF_ISA_DMA_SPEED … #define ASC_INIT_STATE_BEG_GET_CFG … #define ASC_INIT_STATE_END_GET_CFG … #define ASC_INIT_STATE_BEG_SET_CFG … #define ASC_INIT_STATE_END_SET_CFG … #define ASC_INIT_STATE_BEG_LOAD_MC … #define ASC_INIT_STATE_END_LOAD_MC … #define ASC_INIT_STATE_BEG_INQUIRY … #define ASC_INIT_STATE_END_INQUIRY … #define ASC_INIT_RESET_SCSI_DONE … #define ASC_INIT_STATE_WITHOUT_EEP … #define ASC_BUG_FIX_IF_NOT_DWB … #define ASC_BUG_FIX_ASYN_USE_SYN … #define ASC_MIN_TAGGED_CMD … #define ASC_MAX_SCSI_RESET_WAIT … #define ASC_OVERRUN_BSIZE … struct asc_dvc_var; /* Forward Declaration. */ ASC_DVC_VAR; ASC_DVC_INQ_INFO; ASC_CAP_INFO; ASC_CAP_INFO_ARRAY; #define ASC_MCNTL_NO_SEL_TIMEOUT … #define ASC_MCNTL_NULL_TARGET … #define ASC_CNTL_INITIATOR … #define ASC_CNTL_BIOS_GT_1GB … #define ASC_CNTL_BIOS_GT_2_DISK … #define ASC_CNTL_BIOS_REMOVABLE … #define ASC_CNTL_NO_SCAM … #define ASC_CNTL_INT_MULTI_Q … #define ASC_CNTL_NO_LUN_SUPPORT … #define ASC_CNTL_NO_VERIFY_COPY … #define ASC_CNTL_RESET_SCSI … #define ASC_CNTL_INIT_INQUIRY … #define ASC_CNTL_INIT_VERBOSE … #define ASC_CNTL_SCSI_PARITY … #define ASC_CNTL_BURST_MODE … #define ASC_CNTL_SDTR_ENABLE_ULTRA … #define ASC_EEP_DVC_CFG_BEG_VL … #define ASC_EEP_MAX_DVC_ADDR_VL … #define ASC_EEP_DVC_CFG_BEG … #define ASC_EEP_MAX_DVC_ADDR … #define ASC_EEP_MAX_RETRY … /* * These macros keep the chip SCSI id bitfields in board order. C bitfields * aren't portable between big and little-endian platforms so they are not used. */ #define ASC_EEP_GET_CHIP_ID(cfg) … #define ASC_EEP_GET_DMA_SPD(cfg) … #define ASC_EEP_SET_CHIP_ID(cfg, sid) … #define ASC_EEP_SET_DMA_SPD(cfg, spd) … ASCEEP_CONFIG; #define ASC_EEP_CMD_READ … #define ASC_EEP_CMD_WRITE … #define ASC_EEP_CMD_WRITE_ABLE … #define ASC_EEP_CMD_WRITE_DISABLE … #define ASCV_MSGOUT_BEG … #define ASCV_MSGOUT_SDTR_PERIOD … #define ASCV_MSGOUT_SDTR_OFFSET … #define ASCV_BREAK_SAVED_CODE … #define ASCV_MSGIN_BEG … #define ASCV_MSGIN_SDTR_PERIOD … #define ASCV_MSGIN_SDTR_OFFSET … #define ASCV_SDTR_DATA_BEG … #define ASCV_SDTR_DONE_BEG … #define ASCV_MAX_DVC_QNG_BEG … #define ASCV_BREAK_ADDR … #define ASCV_BREAK_NOTIFY_COUNT … #define ASCV_BREAK_CONTROL … #define ASCV_BREAK_HIT_COUNT … #define ASCV_ASCDVC_ERR_CODE_W … #define ASCV_MCODE_CHKSUM_W … #define ASCV_MCODE_SIZE_W … #define ASCV_STOP_CODE_B … #define ASCV_DVC_ERR_CODE_B … #define ASCV_OVERRUN_PADDR_D … #define ASCV_OVERRUN_BSIZE_D … #define ASCV_HALTCODE_W … #define ASCV_CHKSUM_W … #define ASCV_MC_DATE_W … #define ASCV_MC_VER_W … #define ASCV_NEXTRDY_B … #define ASCV_DONENEXT_B … #define ASCV_USE_TAGGED_QNG_B … #define ASCV_SCSIBUSY_B … #define ASCV_Q_DONE_IN_PROGRESS_B … #define ASCV_CURCDB_B … #define ASCV_RCLUN_B … #define ASCV_BUSY_QHEAD_B … #define ASCV_DISC1_QHEAD_B … #define ASCV_DISC_ENABLE_B … #define ASCV_CAN_TAGGED_QNG_B … #define ASCV_HOSTSCSI_ID_B … #define ASCV_MCODE_CNTL_B … #define ASCV_NULL_TARGET_B … #define ASCV_FREE_Q_HEAD_W … #define ASCV_DONE_Q_TAIL_W … #define ASCV_FREE_Q_HEAD_B … #define ASCV_DONE_Q_TAIL_B … #define ASCV_HOST_FLAG_B … #define ASCV_TOTAL_READY_Q_B … #define ASCV_VER_SERIAL_B … #define ASCV_HALTCODE_SAVED_W … #define ASCV_WTM_FLAG_B … #define ASCV_RISC_FLAG_B … #define ASCV_REQ_SG_LIST_QP … #define ASC_HOST_FLAG_IN_ISR … #define ASC_HOST_FLAG_ACK_INT … #define ASC_RISC_FLAG_GEN_INT … #define ASC_RISC_FLAG_REQ_SG_LIST … #define IOP_CTRL … #define IOP_STATUS … #define IOP_INT_ACK … #define IOP_REG_IFC … #define IOP_SYN_OFFSET … #define IOP_EXTRA_CONTROL … #define IOP_REG_PC … #define IOP_RAM_ADDR … #define IOP_RAM_DATA … #define IOP_EEP_DATA … #define IOP_EEP_CMD … #define IOP_VERSION … #define IOP_CONFIG_HIGH … #define IOP_CONFIG_LOW … #define IOP_SIG_BYTE … #define IOP_SIG_WORD … #define IOP_REG_DC1 … #define IOP_REG_DC0 … #define IOP_REG_SB … #define IOP_REG_DA1 … #define IOP_REG_DA0 … #define IOP_REG_SC … #define IOP_DMA_SPEED … #define IOP_REG_FLAG … #define IOP_FIFO_H … #define IOP_FIFO_L … #define IOP_REG_ID … #define IOP_REG_QP … #define IOP_REG_IH … #define IOP_REG_IX … #define IOP_REG_AX … #define IFC_REG_LOCK … #define IFC_REG_UNLOCK … #define IFC_WR_EN_FILTER … #define IFC_RD_NO_EEPROM … #define IFC_SLEW_RATE … #define IFC_ACT_NEG … #define IFC_INP_FILTER … #define IFC_INIT_DEFAULT … #define SC_SEL … #define SC_BSY … #define SC_ACK … #define SC_REQ … #define SC_ATN … #define SC_IO … #define SC_CD … #define SC_MSG … #define SEC_SCSI_CTL … #define SEC_ACTIVE_NEGATE … #define SEC_SLEW_RATE … #define SEC_ENABLE_FILTER … #define ASC_HALT_EXTMSG_IN … #define ASC_HALT_CHK_CONDITION … #define ASC_HALT_SS_QUEUE_FULL … #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX … #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX … #define ASC_HALT_SDTR_REJECTED … #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC … #define ASC_MAX_QNO … #define ASC_DATA_SEC_BEG … #define ASC_DATA_SEC_END … #define ASC_CODE_SEC_BEG … #define ASC_CODE_SEC_END … #define ASC_QADR_BEG … #define ASC_QADR_USED … #define ASC_QADR_END … #define ASC_QLAST_ADR … #define ASC_QBLK_SIZE … #define ASC_BIOS_DATA_QBEG … #define ASC_MIN_ACTIVE_QNO … #define ASC_QLINK_END … #define ASC_EEPROM_WORDS … #define ASC_MAX_MGS_LEN … #define ASC_BIOS_ADDR_DEF … #define ASC_BIOS_SIZE … #define ASC_BIOS_RAM_OFF … #define ASC_BIOS_RAM_SIZE … #define ASC_BIOS_MIN_ADDR … #define ASC_BIOS_MAX_ADDR … #define ASC_BIOS_BANK_SIZE … #define ASC_MCODE_START_ADDR … #define ASC_CFG0_HOST_INT_ON … #define ASC_CFG0_BIOS_ON … #define ASC_CFG0_VERA_BURST_ON … #define ASC_CFG0_SCSI_PARITY_ON … #define ASC_CFG1_SCSI_TARGET_ON … #define ASC_CFG1_LRAM_8BITS_ON … #define ASC_CFG_MSW_CLR_MASK … #define CSW_TEST1 … #define CSW_AUTO_CONFIG … #define CSW_RESERVED1 … #define CSW_IRQ_WRITTEN … #define CSW_33MHZ_SELECTED … #define CSW_TEST2 … #define CSW_TEST3 … #define CSW_RESERVED2 … #define CSW_DMA_DONE … #define CSW_FIFO_RDY … #define CSW_EEP_READ_DONE … #define CSW_HALTED … #define CSW_SCSI_RESET_ACTIVE … #define CSW_PARITY_ERR … #define CSW_SCSI_RESET_LATCH … #define CSW_INT_PENDING … #define CIW_CLR_SCSI_RESET_INT … #define CIW_INT_ACK … #define CIW_TEST1 … #define CIW_TEST2 … #define CIW_SEL_33MHZ … #define CIW_IRQ_ACT … #define CC_CHIP_RESET … #define CC_SCSI_RESET … #define CC_HALT … #define CC_SINGLE_STEP … #define CC_DMA_ABLE … #define CC_TEST … #define CC_BANK_ONE … #define CC_DIAG … #define ASC_1000_ID0W … #define ASC_1000_ID0W_FIX … #define ASC_1000_ID1B … #define ASC_EISA_REV_IOP_MASK … #define ASC_EISA_CFG_IOP_MASK … #define ASC_GET_EISA_SLOT(iop) … #define INS_HALTINT … #define INS_HALT … #define INS_SINT … #define INS_RFLAG_WTM … #define ASC_MC_SAVE_CODE_WSIZE … #define ASC_MC_SAVE_DATA_WSIZE … ASC_MC_SAVED; #define AscGetQDoneInProgress(port) … #define AscPutQDoneInProgress(port, val) … #define AscGetVarFreeQHead(port) … #define AscGetVarDoneQTail(port) … #define AscPutVarFreeQHead(port, val) … #define AscPutVarDoneQTail(port, val) … #define AscGetRiscVarFreeQHead(port) … #define AscGetRiscVarDoneQTail(port) … #define AscPutRiscVarFreeQHead(port, val) … #define AscPutRiscVarDoneQTail(port, val) … #define AscPutMCodeSDTRDoneAtID(port, id, data) … #define AscGetMCodeSDTRDoneAtID(port, id) … #define AscPutMCodeInitSDTRAtID(port, id, data) … #define AscGetMCodeInitSDTRAtID(port, id) … #define AscGetChipSignatureByte(port) … #define AscGetChipSignatureWord(port) … #define AscGetChipVerNo(port) … #define AscGetChipCfgLsw(port) … #define AscGetChipCfgMsw(port) … #define AscSetChipCfgLsw(port, data) … #define AscSetChipCfgMsw(port, data) … #define AscGetChipEEPCmd(port) … #define AscSetChipEEPCmd(port, data) … #define AscGetChipEEPData(port) … #define AscSetChipEEPData(port, data) … #define AscGetChipLramAddr(port) … #define AscSetChipLramAddr(port, addr) … #define AscGetChipLramData(port) … #define AscSetChipLramData(port, data) … #define AscGetChipIFC(port) … #define AscSetChipIFC(port, data) … #define AscGetChipStatus(port) … #define AscSetChipStatus(port, cs_val) … #define AscGetChipControl(port) … #define AscSetChipControl(port, cc_val) … #define AscGetChipSyn(port) … #define AscSetChipSyn(port, data) … #define AscSetPCAddr(port, data) … #define AscGetPCAddr(port) … #define AscIsIntPending(port) … #define AscGetChipScsiID(port) … #define AscGetExtraControl(port) … #define AscSetExtraControl(port, data) … #define AscReadChipAX(port) … #define AscWriteChipAX(port, data) … #define AscReadChipIX(port) … #define AscWriteChipIX(port, data) … #define AscReadChipIH(port) … #define AscWriteChipIH(port, data) … #define AscReadChipQP(port) … #define AscWriteChipQP(port, data) … #define AscReadChipFIFO_L(port) … #define AscWriteChipFIFO_L(port, data) … #define AscReadChipFIFO_H(port) … #define AscWriteChipFIFO_H(port, data) … #define AscReadChipDmaSpeed(port) … #define AscWriteChipDmaSpeed(port, data) … #define AscReadChipDA0(port) … #define AscWriteChipDA0(port) … #define AscReadChipDA1(port) … #define AscWriteChipDA1(port) … #define AscReadChipDC0(port) … #define AscWriteChipDC0(port) … #define AscReadChipDC1(port) … #define AscWriteChipDC1(port) … #define AscReadChipDvcID(port) … #define AscWriteChipDvcID(port, data) … #define AdvPortAddr … /* * Define Adv Library required memory access macros. */ #define ADV_MEM_READB(addr) … #define ADV_MEM_READW(addr) … #define ADV_MEM_WRITEB(addr, byte) … #define ADV_MEM_WRITEW(addr, word) … #define ADV_MEM_WRITEDW(addr, dword) … /* * Define total number of simultaneous maximum element scatter-gather * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the * maximum number of outstanding commands per wide host adapter. Each * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather * elements. Allow each command to have at least one ADV_SG_BLOCK structure. * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK * structures or 255 scatter-gather elements. */ #define ADV_TOT_SG_BLOCK … /* * Define maximum number of scatter-gather elements per request. */ #define ADV_MAX_SG_LIST … #define NO_OF_SG_PER_BLOCK … #define ADV_EEP_DVC_CFG_BEGIN … #define ADV_EEP_DVC_CFG_END … #define ADV_EEP_DVC_CTL_BEGIN … #define ADV_EEP_MAX_WORD_ADDR … #define ADV_EEP_DELAY_MS … #define ADV_EEPROM_BIG_ENDIAN … #define ADV_EEPROM_BIOS_ENABLE … /* * For the ASC3550 Bit 13 is Termination Polarity control bit. * For later ICs Bit 13 controls whether the CIS (Card Information * Service Section) is loaded from EEPROM. */ #define ADV_EEPROM_TERM_POL … #define ADV_EEPROM_CIS_LD … /* * ASC38C1600 Bit 11 * * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify * INT A in the PCI Configuration Space Int Pin field. If it is 1, then * Function 0 will specify INT B. * * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify * INT B in the PCI Configuration Space Int Pin field. If it is 1, then * Function 1 will specify INT A. */ #define ADV_EEPROM_INTAB … ADVEEP_3550_CONFIG; ADVEEP_38C0800_CONFIG; ADVEEP_38C1600_CONFIG; /* * EEPROM Commands */ #define ASC_EEP_CMD_DONE … /* bios_ctrl */ #define BIOS_CTRL_BIOS … #define BIOS_CTRL_EXTENDED_XLAT … #define BIOS_CTRL_GT_2_DISK … #define BIOS_CTRL_BIOS_REMOVABLE … #define BIOS_CTRL_BOOTABLE_CD … #define BIOS_CTRL_MULTIPLE_LUN … #define BIOS_CTRL_DISPLAY_MSG … #define BIOS_CTRL_NO_SCAM … #define BIOS_CTRL_RESET_SCSI_BUS … #define BIOS_CTRL_INIT_VERBOSE … #define BIOS_CTRL_SCSI_PARITY … #define BIOS_CTRL_AIPP_DIS … #define ADV_3550_MEMSIZE … #define ADV_38C0800_MEMSIZE … /* * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is * a special 16K Adv Library and Microcode version. After the issue is * resolved, should restore 32K support. * * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory * */ #define ADV_38C1600_MEMSIZE … /* * Byte I/O register address from base of 'iop_base'. */ #define IOPB_INTR_STATUS_REG … #define IOPB_CHIP_ID_1 … #define IOPB_INTR_ENABLES … #define IOPB_CHIP_TYPE_REV … #define IOPB_RES_ADDR_4 … #define IOPB_RES_ADDR_5 … #define IOPB_RAM_DATA … #define IOPB_RES_ADDR_7 … #define IOPB_FLAG_REG … #define IOPB_RES_ADDR_9 … #define IOPB_RISC_CSR … #define IOPB_RES_ADDR_B … #define IOPB_RES_ADDR_C … #define IOPB_RES_ADDR_D … #define IOPB_SOFT_OVER_WR … #define IOPB_RES_ADDR_F … #define IOPB_MEM_CFG … #define IOPB_RES_ADDR_11 … #define IOPB_GPIO_DATA … #define IOPB_RES_ADDR_13 … #define IOPB_FLASH_PAGE … #define IOPB_RES_ADDR_15 … #define IOPB_GPIO_CNTL … #define IOPB_RES_ADDR_17 … #define IOPB_FLASH_DATA … #define IOPB_RES_ADDR_19 … #define IOPB_RES_ADDR_1A … #define IOPB_RES_ADDR_1B … #define IOPB_RES_ADDR_1C … #define IOPB_RES_ADDR_1D … #define IOPB_RES_ADDR_1E … #define IOPB_RES_ADDR_1F … #define IOPB_DMA_CFG0 … #define IOPB_DMA_CFG1 … #define IOPB_TICKLE … #define IOPB_DMA_REG_WR … #define IOPB_SDMA_STATUS … #define IOPB_SCSI_BYTE_CNT … #define IOPB_HOST_BYTE_CNT … #define IOPB_BYTE_LEFT_TO_XFER … #define IOPB_BYTE_TO_XFER_0 … #define IOPB_BYTE_TO_XFER_1 … #define IOPB_BYTE_TO_XFER_2 … #define IOPB_BYTE_TO_XFER_3 … #define IOPB_ACC_GRP … #define IOPB_RES_ADDR_2D … #define IOPB_DEV_ID … #define IOPB_RES_ADDR_2F … #define IOPB_SCSI_DATA … #define IOPB_RES_ADDR_31 … #define IOPB_RES_ADDR_32 … #define IOPB_SCSI_DATA_HSHK … #define IOPB_SCSI_CTRL … #define IOPB_RES_ADDR_35 … #define IOPB_RES_ADDR_36 … #define IOPB_RES_ADDR_37 … #define IOPB_RAM_BIST … #define IOPB_PLL_TEST … #define IOPB_PCI_INT_CFG … #define IOPB_RES_ADDR_3B … #define IOPB_RFIFO_CNT … #define IOPB_RES_ADDR_3D … #define IOPB_RES_ADDR_3E … #define IOPB_RES_ADDR_3F … /* * Word I/O register address from base of 'iop_base'. */ #define IOPW_CHIP_ID_0 … #define IOPW_CTRL_REG … #define IOPW_RAM_ADDR … #define IOPW_RAM_DATA … #define IOPW_RES_ADDR_08 … #define IOPW_RISC_CSR … #define IOPW_SCSI_CFG0 … #define IOPW_SCSI_CFG1 … #define IOPW_RES_ADDR_10 … #define IOPW_SEL_MASK … #define IOPW_RES_ADDR_14 … #define IOPW_FLASH_ADDR … #define IOPW_RES_ADDR_18 … #define IOPW_EE_CMD … #define IOPW_EE_DATA … #define IOPW_SFIFO_CNT … #define IOPW_RES_ADDR_20 … #define IOPW_Q_BASE … #define IOPW_QP … #define IOPW_IX … #define IOPW_SP … #define IOPW_PC … #define IOPW_RES_ADDR_2C … #define IOPW_RES_ADDR_2E … #define IOPW_SCSI_DATA … #define IOPW_SCSI_DATA_HSHK … #define IOPW_SCSI_CTRL … #define IOPW_HSHK_CFG … #define IOPW_SXFR_STATUS … #define IOPW_SXFR_CNTL … #define IOPW_SXFR_CNTH … #define IOPW_RES_ADDR_3C … #define IOPW_RFIFO_DATA … /* * Doubleword I/O register address from base of 'iop_base'. */ #define IOPDW_RES_ADDR_0 … #define IOPDW_RAM_DATA … #define IOPDW_RES_ADDR_8 … #define IOPDW_RES_ADDR_C … #define IOPDW_RES_ADDR_10 … #define IOPDW_COMMA … #define IOPDW_COMMB … #define IOPDW_RES_ADDR_1C … #define IOPDW_SDMA_ADDR0 … #define IOPDW_SDMA_ADDR1 … #define IOPDW_SDMA_COUNT … #define IOPDW_SDMA_ERROR … #define IOPDW_RDMA_ADDR0 … #define IOPDW_RDMA_ADDR1 … #define IOPDW_RDMA_COUNT … #define IOPDW_RDMA_ERROR … #define ADV_CHIP_ID_BYTE … #define ADV_CHIP_ID_WORD … #define ADV_INTR_ENABLE_HOST_INTR … #define ADV_INTR_ENABLE_SEL_INTR … #define ADV_INTR_ENABLE_DPR_INTR … #define ADV_INTR_ENABLE_RTA_INTR … #define ADV_INTR_ENABLE_RMA_INTR … #define ADV_INTR_ENABLE_RST_INTR … #define ADV_INTR_ENABLE_DPE_INTR … #define ADV_INTR_ENABLE_GLOBAL_INTR … #define ADV_INTR_STATUS_INTRA … #define ADV_INTR_STATUS_INTRB … #define ADV_INTR_STATUS_INTRC … #define ADV_RISC_CSR_STOP … #define ADV_RISC_TEST_COND … #define ADV_RISC_CSR_RUN … #define ADV_RISC_CSR_SINGLE_STEP … #define ADV_CTRL_REG_HOST_INTR … #define ADV_CTRL_REG_SEL_INTR … #define ADV_CTRL_REG_DPR_INTR … #define ADV_CTRL_REG_RTA_INTR … #define ADV_CTRL_REG_RMA_INTR … #define ADV_CTRL_REG_RES_BIT14 … #define ADV_CTRL_REG_DPE_INTR … #define ADV_CTRL_REG_POWER_DONE … #define ADV_CTRL_REG_ANY_INTR … #define ADV_CTRL_REG_CMD_RESET … #define ADV_CTRL_REG_CMD_WR_IO_REG … #define ADV_CTRL_REG_CMD_RD_IO_REG … #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE … #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE … #define ADV_TICKLE_NOP … #define ADV_TICKLE_A … #define ADV_TICKLE_B … #define ADV_TICKLE_C … #define AdvIsIntPending(port) … /* * SCSI_CFG0 Register bit definitions */ #define TIMER_MODEAB … #define PARITY_EN … #define EVEN_PARITY … #define WD_LONG … #define QUEUE_128 … #define PRIM_MODE … #define SCAM_EN … #define SEL_TMO_LONG … #define CFRM_ID … #define OUR_ID_EN … #define OUR_ID … /* * SCSI_CFG1 Register bit definitions */ #define BIG_ENDIAN … #define TERM_POL … #define SLEW_RATE … #define FILTER_SEL … #define FLTR_DISABLE … #define FLTR_11_TO_20NS … #define FLTR_21_TO_39NS … #define ACTIVE_DBL … #define DIFF_MODE … #define DIFF_SENSE … #define TERM_CTL_SEL … #define TERM_CTL … #define TERM_CTL_H … #define TERM_CTL_L … #define CABLE_DETECT … /* * Addendum for ASC-38C0800 Chip * * The ASC-38C1600 Chip uses the same definitions except that the * bus mode override bits [12:10] have been moved to byte register * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. * Also each ASC-38C1600 function or channel uses only cable bits [5:4] * and [1:0]. Bits [14], [7:6], [3:2] are unused. */ #define DIS_TERM_DRV … #define HVD_LVD_SE … #define HVD … #define LVD … #define SE … #define TERM_LVD … #define TERM_LVD_HI … #define TERM_LVD_LO … #define TERM_SE … #define TERM_SE_HI … #define TERM_SE_LO … #define C_DET_LVD … #define C_DET3 … #define C_DET2 … #define C_DET_SE … #define C_DET1 … #define C_DET0 … #define CABLE_ILLEGAL_A … /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ #define CABLE_ILLEGAL_B … /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ /* * MEM_CFG Register bit definitions */ #define BIOS_EN … #define FAST_EE_CLK … #define RAM_SZ … #define RAM_SZ_2KB … #define RAM_SZ_4KB … #define RAM_SZ_8KB … #define RAM_SZ_16KB … #define RAM_SZ_32KB … #define RAM_SZ_64KB … /* * DMA_CFG0 Register bit definitions * * This register is only accessible to the host. */ #define BC_THRESH_ENB … #define FIFO_THRESH … #define FIFO_THRESH_16B … #define FIFO_THRESH_32B … #define FIFO_THRESH_48B … #define FIFO_THRESH_64B … #define FIFO_THRESH_80B … #define FIFO_THRESH_96B … #define FIFO_THRESH_112B … #define START_CTL … #define START_CTL_TH … #define START_CTL_ID … #define START_CTL_THID … #define START_CTL_EMFU … #define READ_CMD … #define READ_CMD_MR … #define READ_CMD_MRL … #define READ_CMD_MRM … /* * ASC-38C0800 RAM BIST Register bit definitions */ #define RAM_TEST_MODE … #define PRE_TEST_MODE … #define NORMAL_MODE … #define RAM_TEST_DONE … #define RAM_TEST_STATUS … #define RAM_TEST_HOST_ERROR … #define RAM_TEST_INTRAM_ERROR … #define RAM_TEST_RISC_ERROR … #define RAM_TEST_SCSI_ERROR … #define RAM_TEST_SUCCESS … #define PRE_TEST_VALUE … #define NORMAL_VALUE … /* * ASC38C1600 Definitions * * IOPB_PCI_INT_CFG Bit Field Definitions */ #define INTAB_LD … /* * Bit 1 can be set to change the interrupt for the Function to operate in * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in * Open Drain mode. Both functions of the ASC38C1600 must be set to the same * mode, otherwise the operating mode is undefined. */ #define TOTEMPOLE … /* * Bit 0 can be used to change the Int Pin for the Function. The value is * 0 by default for both Functions with Function 0 using INT A and Function * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, * INT A is used. * * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin * value specified in the PCI Configuration Space. */ #define INTAB … /* * Adv Library Status Definitions */ #define ADV_TRUE … #define ADV_FALSE … #define ADV_SUCCESS … #define ADV_BUSY … #define ADV_ERROR … /* * ADV_DVC_VAR 'warn_code' values */ #define ASC_WARN_BUSRESET_ERROR … #define ASC_WARN_EEPROM_CHKSUM … #define ASC_WARN_EEPROM_TERMINATION … #define ASC_WARN_ERROR … #define ADV_MAX_TID … #define ADV_MAX_LUN … /* * Fixed locations of microcode operating variables. */ #define ASC_MC_CODE_BEGIN_ADDR … #define ASC_MC_CODE_END_ADDR … #define ASC_MC_CODE_CHK_SUM … #define ASC_MC_VERSION_DATE … #define ASC_MC_VERSION_NUM … #define ASC_MC_BIOSMEM … #define ASC_MC_BIOSLEN … #define ASC_MC_BIOS_SIGNATURE … #define ASC_MC_BIOS_VERSION … #define ASC_MC_SDTR_SPEED1 … #define ASC_MC_SDTR_SPEED2 … #define ASC_MC_SDTR_SPEED3 … #define ASC_MC_SDTR_SPEED4 … #define ASC_MC_CHIP_TYPE … #define ASC_MC_INTRB_CODE … #define ASC_MC_WDTR_ABLE … #define ASC_MC_SDTR_ABLE … #define ASC_MC_TAGQNG_ABLE … #define ASC_MC_DISC_ENABLE … #define ASC_MC_IDLE_CMD_STATUS … #define ASC_MC_IDLE_CMD … #define ASC_MC_IDLE_CMD_PARAMETER … #define ASC_MC_DEFAULT_SCSI_CFG0 … #define ASC_MC_DEFAULT_SCSI_CFG1 … #define ASC_MC_DEFAULT_MEM_CFG … #define ASC_MC_DEFAULT_SEL_MASK … #define ASC_MC_SDTR_DONE … #define ASC_MC_NUMBER_OF_QUEUED_CMD … #define ASC_MC_NUMBER_OF_MAX_CMD … #define ASC_MC_DEVICE_HSHK_CFG_TABLE … #define ASC_MC_CONTROL_FLAG … #define ASC_MC_WDTR_DONE … #define ASC_MC_CAM_MODE_MASK … #define ASC_MC_ICQ … #define ASC_MC_IRQ … #define ASC_MC_PPR_ABLE … /* * BIOS LRAM variable absolute offsets. */ #define BIOS_CODESEG … #define BIOS_CODELEN … #define BIOS_SIGNATURE … #define BIOS_VERSION … /* * Microcode Control Flags * * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) * and handled by the microcode. */ #define CONTROL_FLAG_IGNORE_PERR … #define CONTROL_FLAG_ENABLE_AIPP … /* * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format */ #define HSHK_CFG_WIDE_XFR … #define HSHK_CFG_RATE … #define HSHK_CFG_OFFSET … #define ASC_DEF_MAX_HOST_QNG … #define ASC_DEF_MIN_HOST_QNG … #define ASC_DEF_MAX_DVC_QNG … #define ASC_DEF_MIN_DVC_QNG … #define ASC_QC_DATA_CHECK … #define ASC_QC_DATA_OUT … #define ASC_QC_START_MOTOR … #define ASC_QC_NO_OVERRUN … #define ASC_QC_FREEZE_TIDQ … #define ASC_QSC_NO_DISC … #define ASC_QSC_NO_TAGMSG … #define ASC_QSC_NO_SYNC … #define ASC_QSC_NO_WIDE … #define ASC_QSC_REDO_DTR … /* * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. */ #define ASC_QSC_HEAD_TAG … #define ASC_QSC_ORDERED_TAG … /* * All fields here are accessed by the board microcode and need to be * little-endian. */ ADV_CARR_T; /* * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. */ #define ADV_NEXT_VPA_MASK … #define ADV_RQ_DONE … #define ADV_RQ_GOOD … #define ADV_CQ_STOPPER … #define ADV_GET_CARRP(carrp) … /* * Each carrier is 64 bytes, and we need three additional * carrier for icq, irq, and the termination carrier. */ #define ADV_CARRIER_COUNT … #define ADV_CARRIER_BUFSIZE … #define ADV_CHIP_ASC3550 … #define ADV_CHIP_ASC38C0800 … #define ADV_CHIP_ASC38C1600 … /* * Adapter temporary configuration structure * * This structure can be discarded after initialization. Don't add * fields here needed after initialization. * * Field naming convention: * * *_enable indicates the field enables or disables a feature. The * value of the field is never reset. */ ADV_DVC_CFG; struct adv_dvc_var; struct adv_scsi_req_q; ADV_SG_BLOCK; /* * ADV_SCSI_REQ_Q - microcode request structure * * All fields in this structure up to byte 60 are used by the microcode. * The microcode makes assumptions about the size and ordering of fields * in this structure. Do not change the structure definition here without * coordinating the change with the microcode. * * All fields accessed by microcode must be maintained in little_endian * order. */ ADV_SCSI_REQ_Q; /* * The following two structures are used to process Wide Board requests. * * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points * to the Mid-Level SCSI request structure. * * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux * up to 255 scatter-gather elements may be used per request or * ADV_SCSI_REQ_Q. * * Both structures must be 32 byte aligned. */ adv_sgblk_t; adv_req_t __aligned(…); /* * Adapter operation variable structure. * * One structure is required per host adapter. * * Field naming convention: * * *_able indicates both whether a feature should be enabled or disabled * and whether a device is capable of the feature. At initialization * this field may be set, but later if a device is found to be incapable * of the feature, the field is cleared. */ ADV_DVC_VAR; /* * Microcode idle loop commands */ #define IDLE_CMD_COMPLETED … #define IDLE_CMD_STOP_CHIP … #define IDLE_CMD_STOP_CHIP_SEND_INT … #define IDLE_CMD_SEND_INT … #define IDLE_CMD_ABORT … #define IDLE_CMD_DEVICE_RESET … #define IDLE_CMD_SCSI_RESET_START … #define IDLE_CMD_SCSI_RESET_END … #define IDLE_CMD_SCSIREQ … #define IDLE_CMD_STATUS_SUCCESS … #define IDLE_CMD_STATUS_FAILURE … /* * AdvSendIdleCmd() flag definitions. */ #define ADV_NOWAIT … /* * Wait loop time out values. */ #define SCSI_WAIT_100_MSEC … #define SCSI_US_PER_MSEC … #define SCSI_MAX_RETRY … #define ADV_ASYNC_RDMA_FAILURE … #define ADV_ASYNC_SCSI_BUS_RESET_DET … #define ADV_ASYNC_CARRIER_READY_FAILURE … #define ADV_RDMA_IN_CARR_AND_Q_INVALID … #define ADV_HOST_SCSI_BUS_RESET … /* Read byte from a register. */ #define AdvReadByteRegister(iop_base, reg_off) … /* Write byte to a register. */ #define AdvWriteByteRegister(iop_base, reg_off, byte) … /* Read word (2 bytes) from a register. */ #define AdvReadWordRegister(iop_base, reg_off) … /* Write word (2 bytes) to a register. */ #define AdvWriteWordRegister(iop_base, reg_off, word) … /* Write dword (4 bytes) to a register. */ #define AdvWriteDWordRegister(iop_base, reg_off, dword) … /* Read byte from LRAM. */ #define AdvReadByteLram(iop_base, addr, byte) … /* Write byte to LRAM. */ #define AdvWriteByteLram(iop_base, addr, byte) … /* Read word (2 bytes) from LRAM. */ #define AdvReadWordLram(iop_base, addr, word) … /* Write word (2 bytes) to LRAM. */ #define AdvWriteWordLram(iop_base, addr, word) … /* Write little-endian double word (4 bytes) to LRAM */ /* Because of unspecified C language ordering don't use auto-increment. */ #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) … /* Read word (2 bytes) from LRAM assuming that the address is already set. */ #define AdvReadWordAutoIncLram(iop_base) … /* Write word (2 bytes) to LRAM assuming that the address is already set. */ #define AdvWriteWordAutoIncLram(iop_base, word) … /* * Define macro to check for Condor signature. * * Evaluate to ADV_TRUE if a Condor chip is found the specified port * address 'iop_base'. Otherwise evalue to ADV_FALSE. */ #define AdvFindSignature(iop_base) … /* * Define macro to Return the version number of the chip at 'iop_base'. * * The second parameter 'bus_type' is currently unused. */ #define AdvGetChipVersion(iop_base, bus_type) … /* * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must * match the ADV_SCSI_REQ_Q 'srb_tag' field. * * If the request has not yet been sent to the device it will simply be * aborted from RISC memory. If the request is disconnected it will be * aborted on reselection by sending an Abort Message to the target ID. * * Return value: * ADV_TRUE(1) - Queue was successfully aborted. * ADV_FALSE(0) - Queue was not found on the active queue list. */ #define AdvAbortQueue(asc_dvc, srb_tag) … /* * Send a Bus Device Reset Message to the specified target ID. * * All outstanding commands will be purged if sending the * Bus Device Reset Message is successful. * * Return Value: * ADV_TRUE(1) - All requests on the target are purged. * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests * are not purged. */ #define AdvResetDevice(asc_dvc, target_id) … /* * SCSI Wide Type definition. */ #define ADV_SCSI_BIT_ID_TYPE … /* * AdvInitScsiTarget() 'cntl_flag' options. */ #define ADV_SCAN_LUN … #define ADV_CAPINFO_NOLUN … /* * Convert target id to target id bit mask. */ #define ADV_TID_TO_TIDMASK(tid) … /* * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values. */ #define QD_NO_STATUS … #define QD_NO_ERROR … #define QD_ABORTED_BY_HOST … #define QD_WITH_ERROR … #define QHSTA_NO_ERROR … #define QHSTA_M_SEL_TIMEOUT … #define QHSTA_M_DATA_OVER_RUN … #define QHSTA_M_UNEXPECTED_BUS_FREE … #define QHSTA_M_QUEUE_ABORTED … #define QHSTA_M_SXFR_SDMA_ERR … #define QHSTA_M_SXFR_SXFR_PERR … #define QHSTA_M_RDMA_PERR … #define QHSTA_M_SXFR_OFF_UFLW … #define QHSTA_M_SXFR_OFF_OFLW … #define QHSTA_M_SXFR_WD_TMO … #define QHSTA_M_SXFR_DESELECTED … /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ #define QHSTA_M_SXFR_XFR_OFLW … #define QHSTA_M_SXFR_XFR_PH_ERR … #define QHSTA_M_SXFR_UNKNOWN_ERROR … #define QHSTA_M_SCSI_BUS_RESET … #define QHSTA_M_SCSI_BUS_RESET_UNSOL … #define QHSTA_M_BUS_DEVICE_RESET … #define QHSTA_M_DIRECTION_ERR … #define QHSTA_M_DIRECTION_ERR_HUNG … #define QHSTA_M_WTM_TIMEOUT … #define QHSTA_M_BAD_CMPL_STATUS_IN … #define QHSTA_M_NO_AUTO_REQ_SENSE … #define QHSTA_M_AUTO_REQ_SENSE_FAIL … #define QHSTA_M_INVALID_DEVICE … #define QHSTA_M_FROZEN_TIDQ … #define QHSTA_M_SGBACKUP_ERROR … /* Return the address that is aligned at the next doubleword >= to 'addr'. */ #define ADV_32BALIGN(addr) … /* * Total contiguous memory needed for driver SG blocks. * * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum * number of scatter-gather elements the driver supports in a * single request. */ #define ADV_SG_LIST_MAX_BYTE_SIZE … /* struct asc_board flags */ #define ASC_IS_WIDE_BOARD … #define ASC_NARROW_BOARD(boardp) … #define NO_ISA_DMA … #define ASC_INFO_SIZE … /* Asc Library return codes */ #define ASC_TRUE … #define ASC_FALSE … #define ASC_NOERROR … #define ASC_BUSY … #define ASC_ERROR … #define ASC_STATS(shost, counter) … #ifndef ADVANSYS_STATS #define ASC_STATS_ADD … #else /* ADVANSYS_STATS */ #define ASC_STATS_ADD(shost, counter, count) … #endif /* ADVANSYS_STATS */ /* If the result wraps when calculating tenths, return 0. */ #define ASC_TENTHS(num, den) … /* * Display a message to the console. */ #define ASC_PRINT(s) … #define ASC_PRINT1(s, a1) … #define ASC_PRINT2(s, a1, a2) … #define ASC_PRINT3(s, a1, a2, a3) … #define ASC_PRINT4(s, a1, a2, a3, a4) … #ifndef ADVANSYS_DEBUG #define ASC_DBG(lvl, s...) … #define ASC_DBG_PRT_SCSI_HOST(lvl, s) … #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) … #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) … #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) … #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) … #define ASC_DBG_PRT_HEX(lvl, name, start, length) … #define ASC_DBG_PRT_CDB(lvl, cdb, len) … #define ASC_DBG_PRT_SENSE(lvl, sense, len) … #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) … #else /* ADVANSYS_DEBUG */ /* * Debugging Message Levels: * 0: Errors Only * 1: High-Level Tracing * 2-N: Verbose Tracing */ #define ASC_DBG … #define ASC_DBG_PRT_SCSI_HOST … #define ASC_DBG_PRT_ASC_SCSI_Q … #define ASC_DBG_PRT_ASC_QDONE_INFO … #define ASC_DBG_PRT_ADV_SCSI_REQ_Q … #define ASC_DBG_PRT_HEX … #define ASC_DBG_PRT_CDB … #define ASC_DBG_PRT_SENSE … #define ASC_DBG_PRT_INQUIRY … #endif /* ADVANSYS_DEBUG */ #ifdef ADVANSYS_STATS /* Per board statistics structure */ struct asc_stats { … }; #endif /* ADVANSYS_STATS */ /* * Structure allocated for each board. * * This structure is allocated by scsi_host_alloc() at the end * of the 'Scsi_Host' structure starting at the 'hostdata' * field. It is guaranteed to be allocated from DMA-able memory. */ struct asc_board { … }; #define asc_dvc_to_board(asc_dvc) … #define adv_dvc_to_board(adv_dvc) … #define adv_dvc_to_pdev(adv_dvc) … struct advansys_cmd { … }; static struct advansys_cmd *advansys_cmd(struct scsi_cmnd *cmd) { … } #ifdef ADVANSYS_DEBUG static int asc_dbglvl = 3; /* * asc_prt_asc_dvc_var() */ static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) { printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, (unsigned)h->init_sdtr); printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " "chip_no 0x%x,\n", (unsigned)h->sdtr_done, (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, (unsigned)h->chip_no); printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " "%u,\n", (unsigned)h->queue_full_or_busy, (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " "in_critical_cnt %u,\n", (unsigned)h->is_in_int, (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, (unsigned)h->in_critical_cnt); printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, (unsigned)h->init_state, (unsigned)h->no_scam, (unsigned)h->pci_fix_asyn_xfer); printk(" cfg 0x%lx\n", (ulong)h->cfg); } /* * asc_prt_asc_dvc_cfg() */ static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) { printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", h->can_tagged_qng, h->cmd_qng_enabled); printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", h->disc_enable, h->sdtr_enable); printk(" chip_scsi_id %d, chip_version %d,\n", h->chip_scsi_id, h->chip_version); printk(" mcode_date 0x%x, mcode_version %d\n", h->mcode_date, h->mcode_version); } /* * asc_prt_adv_dvc_var() * * Display an ADV_DVC_VAR structure. */ static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) { printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); printk(" sdtr_able 0x%x, wdtr_able 0x%x\n", (unsigned)h->sdtr_able, (unsigned)h->wdtr_able); printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n", (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n", (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, h->carr_freelist); printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp); printk(" no_scam 0x%x, tagqng_able 0x%x\n", (unsigned)h->no_scam, (unsigned)h->tagqng_able); printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", (unsigned)h->chip_scsi_id, (ulong)h->cfg); } /* * asc_prt_adv_dvc_cfg() * * Display an ADV_DVC_CFG structure. */ static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) { printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); printk(" disc_enable 0x%x, termination 0x%x\n", h->disc_enable, h->termination); printk(" chip_version 0x%x, mcode_date 0x%x\n", h->chip_version, h->mcode_date); printk(" mcode_version 0x%x, control_flag 0x%x\n", h->mcode_version, h->control_flag); } /* * asc_prt_scsi_host() */ static void asc_prt_scsi_host(struct Scsi_Host *s) { struct asc_board *boardp = shost_priv(s); printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); printk(" host_busy %d, host_no %d,\n", scsi_host_busy(s), s->host_no); printk(" base 0x%lx, io_port 0x%lx, irq %d,\n", (ulong)s->base, (ulong)s->io_port, boardp->irq); printk(" dma_channel %d, this_id %d, can_queue %d,\n", s->dma_channel, s->this_id, s->can_queue); printk(" cmd_per_lun %d, sg_tablesize %d\n", s->cmd_per_lun, s->sg_tablesize); if (ASC_NARROW_BOARD(boardp)) { asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var); asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg); } else { asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var); asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg); } } /* * asc_prt_hex() * * Print hexadecimal output in 4 byte groupings 32 bytes * or 8 double-words per line. */ static void asc_prt_hex(char *f, uchar *s, int l) { int i; int j; int k; int m; printk("%s: (%d bytes)\n", f, l); for (i = 0; i < l; i += 32) { /* Display a maximum of 8 double-words per line. */ if ((k = (l - i) / 4) >= 8) { k = 8; m = 0; } else { m = (l - i) % 4; } for (j = 0; j < k; j++) { printk(" %2.2X%2.2X%2.2X%2.2X", (unsigned)s[i + (j * 4)], (unsigned)s[i + (j * 4) + 1], (unsigned)s[i + (j * 4) + 2], (unsigned)s[i + (j * 4) + 3]); } switch (m) { case 0: default: break; case 1: printk(" %2.2X", (unsigned)s[i + (j * 4)]); break; case 2: printk(" %2.2X%2.2X", (unsigned)s[i + (j * 4)], (unsigned)s[i + (j * 4) + 1]); break; case 3: printk(" %2.2X%2.2X%2.2X", (unsigned)s[i + (j * 4) + 1], (unsigned)s[i + (j * 4) + 2], (unsigned)s[i + (j * 4) + 3]); break; } printk("\n"); } } /* * asc_prt_asc_scsi_q() */ static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) { ASC_SG_HEAD *sgp; int i; printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); printk (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n", q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag, q->q2.tag_code); printk (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", (ulong)le32_to_cpu(q->q1.data_addr), (ulong)le32_to_cpu(q->q1.data_cnt), (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", (ulong)q->cdbptr, q->q2.cdb_len, (ulong)q->sg_head, q->q1.sg_queue_cnt); if (q->sg_head) { sgp = q->sg_head; printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt); for (i = 0; i < sgp->entry_cnt; i++) { printk(" [%u]: addr 0x%lx, bytes %lu\n", i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); } } } /* * asc_prt_asc_qdone_info() */ static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) { printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n", q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len, q->d2.tag_code); printk (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); } /* * asc_prt_adv_sgblock() * * Display an ADV_SG_BLOCK structure. */ static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) { int i; printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", (ulong)b, sgblockno); printk(" sg_cnt %u, sg_ptr 0x%x\n", b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr)); BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); if (b->sg_ptr != 0) BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); for (i = 0; i < b->sg_cnt; i++) { printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n", i, (u32)le32_to_cpu(b->sg_list[i].sg_addr), (u32)le32_to_cpu(b->sg_list[i].sg_count)); } } /* * asc_prt_adv_scsi_req_q() * * Display an ADV_SCSI_REQ_Q structure. */ static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) { int sg_blk_cnt; struct adv_sg_block *sg_ptr; adv_sgblk_t *sgblkp; printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); printk(" target_id %u, target_lun %u, srb_tag 0x%x\n", q->target_id, q->target_lun, q->srb_tag); printk(" cntl 0x%x, data_addr 0x%lx\n", q->cntl, (ulong)le32_to_cpu(q->data_addr)); printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", (ulong)le32_to_cpu(q->data_cnt), (ulong)le32_to_cpu(q->sense_addr), q->sense_len); printk (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", q->cdb_len, q->done_status, q->host_status, q->scsi_status); printk(" sg_working_ix 0x%x, target_cmd %u\n", q->sg_working_ix, q->target_cmd); printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", (ulong)le32_to_cpu(q->scsiq_rptr), (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); /* Display the request's ADV_SG_BLOCK structures. */ if (q->sg_list_ptr != NULL) { sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block); sg_blk_cnt = 0; while (sgblkp) { sg_ptr = &sgblkp->sg_block; asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); if (sg_ptr->sg_ptr == 0) { break; } sgblkp = sgblkp->next_sgblkp; sg_blk_cnt++; } } } #endif /* ADVANSYS_DEBUG */ /* * advansys_info() * * Return suitable for printing on the console with the argument * adapter's configuration information. * * Note: The information line should not exceed ASC_INFO_SIZE bytes, * otherwise the static 'info' array will be overrun. */ static const char *advansys_info(struct Scsi_Host *shost) { … } #ifdef CONFIG_PROC_FS /* * asc_prt_board_devices() * * Print driver information for devices attached to the board. */ static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost) { … } /* * Display Wide Board BIOS Information. */ static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost) { … } /* * Add serial number to information bar if signature AAh * is found in at bit 15-9 (7 bits) of word 1. * * Serial Number consists fo 12 alpha-numeric digits. * * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) * 5 - Product revision (A-J) Word0: " " * * Signature Word1: 15-9 (7 bits) * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) * * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) * * Note 1: Only production cards will have a serial number. * * Note 2: Signature is most significant 7 bits (0xFE). * * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. */ static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) { … } /* * asc_prt_asc_board_eeprom() * * Print board EEPROM configuration. */ static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) { … } /* * asc_prt_adv_board_eeprom() * * Print board EEPROM configuration. */ static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) { … } /* * asc_prt_driver_conf() */ static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost) { … } /* * asc_prt_asc_board_info() * * Print dynamic board configuration information. */ static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost) { … } /* * asc_prt_adv_board_info() * * Print dynamic board configuration information. */ static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost) { … } #ifdef ADVANSYS_STATS /* * asc_prt_board_stats() */ static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost) { … } #endif /* ADVANSYS_STATS */ /* * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...} * * m: seq_file to print into * shost: Scsi_Host * * Return the number of bytes read from or written to a * /proc/scsi/advansys/[0...] file. */ static int advansys_show_info(struct seq_file *m, struct Scsi_Host *shost) { … } #endif /* CONFIG_PROC_FS */ static void asc_scsi_done(struct scsi_cmnd *scp) { … } static void AscSetBank(PortAddr iop_base, uchar bank) { … } static void AscSetChipIH(PortAddr iop_base, ushort ins_code) { … } static int AscStartChip(PortAddr iop_base) { … } static bool AscStopChip(PortAddr iop_base) { … } static bool AscIsChipHalted(PortAddr iop_base) { … } static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) { … } static int AscFindSignature(PortAddr iop_base) { … } static void AscEnableInterrupt(PortAddr iop_base) { … } static void AscDisableInterrupt(PortAddr iop_base) { … } static uchar AscReadLramByte(PortAddr iop_base, ushort addr) { … } static ushort AscReadLramWord(PortAddr iop_base, ushort addr) { … } static void AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) { … } static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) { … } static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) { … } /* * Copy 2 bytes to LRAM. * * The source data is assumed to be in little-endian order in memory * and is maintained in little-endian order when written to LRAM. */ static void AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, const uchar *s_buffer, int words) { … } /* * Copy 4 bytes to LRAM. * * The source data is assumed to be in little-endian order in memory * and is maintained in little-endian order when written to LRAM. */ static void AscMemDWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, uchar *s_buffer, int dwords) { … } /* * Copy 2 bytes from LRAM. * * The source data is assumed to be in little-endian order in LRAM * and is maintained in little-endian order when written to memory. */ static void AscMemWordCopyPtrFromLram(PortAddr iop_base, ushort s_addr, uchar *d_buffer, int words) { … } static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) { … } static void AscInitLram(ASC_DVC_VAR *asc_dvc) { … } static u32 AscLoadMicroCode(PortAddr iop_base, ushort s_addr, const uchar *mcode_buf, ushort mcode_size) { … } static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) { … } static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) { … } static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) { … } /* * Load the Microcode * * Write the microcode image to RISC memory starting at address 0. * * The microcode is stored compressed in the following format: * * 254 word (508 byte) table indexed by byte code followed * by the following byte codes: * * 1-Byte Code: * 00: Emit word 0 in table. * 01: Emit word 1 in table. * . * FD: Emit word 253 in table. * * Multi-Byte Code: * FE WW WW: (3 byte code) Word to emit is the next word WW WW. * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. * * Returns 0 or an error if the checksum doesn't match */ static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf, int size, int memsize, int chksum) { … } static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc) { … } static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset) { … } static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc) { … } /* * 'offset' is the index in the request pointer array */ static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset) { … } /* * Send an idle command to the chip and wait for completion. * * Command completion is polled for once per microsecond. * * The function can be called from anywhere including an interrupt handler. * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() * functions to prevent reentrancy. * * Return Values: * ADV_TRUE - command completed successfully * ADV_FALSE - command failed * ADV_ERROR - command timed out */ static int AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, ushort idle_cmd, u32 idle_cmd_parameter) { … } /* * Reset SCSI Bus and purge all outstanding requests. * * Return Value: * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. * ADV_FALSE(0) - Microcode command failed. * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC * may be hung which requires driver recovery. */ static int AdvResetSB(ADV_DVC_VAR *asc_dvc) { … } /* * Initialize the ASC-3550. * * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Needed after initialization for error recovery. */ static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) { … } /* * Initialize the ASC-38C0800. * * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Needed after initialization for error recovery. */ static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) { … } /* * Initialize the ASC-38C1600. * * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Needed after initialization for error recovery. */ static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) { … } /* * Reset chip and SCSI Bus. * * Return Value: * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. */ static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) { … } /* * adv_async_callback() - Adv Library asynchronous event callback function. */ static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) { … } /* * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). * * Callback function for the Wide SCSI Adv Library. */ static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) { … } /* * Adv Library Interrupt Service Routine * * This function is called by a driver's interrupt service routine. * The function disables and re-enables interrupts. * * When a microcode idle command is completed, the ADV_DVC_VAR * 'idle_cmd_done' field is set to ADV_TRUE. * * Note: AdvISR() can be called when interrupts are disabled or even * when there is no hardware interrupt condition present. It will * always check for completed idle commands and microcode requests. * This is an important feature that shouldn't be changed because it * allows commands to be completed from polling mode loops. * * Return: * ADV_TRUE(1) - interrupt was pending * ADV_FALSE(0) - no interrupt was pending */ static int AdvISR(ADV_DVC_VAR *asc_dvc) { … } static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) { … } static void AscAckInterrupt(PortAddr iop_base) { … } static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) { … } static uchar AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) { … } static uchar AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) { … } static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) { … } static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) { … } static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) { … } /* * void * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) * * Calling/Exit State: * none * * Description: * Input an ASC_QDONE_INFO structure from the chip */ static void DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) { … } static uchar _AscCopyLramScsiDoneQ(PortAddr iop_base, ushort q_addr, ASC_QDONE_INFO *scsiq, unsigned int max_dma_count) { … } /* * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). * * Interrupt callback function for the Narrow SCSI Asc Library. */ static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) { … } static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) { … } static int AscISR(ASC_DVC_VAR *asc_dvc) { … } /* * advansys_reset() * * Reset the host associated with the command 'scp'. * * This function runs its own thread. Interrupts must be blocked but * sleeping is allowed and no locking other than for host structures is * required. Returns SUCCESS or FAILED. */ static int advansys_reset(struct scsi_cmnd *scp) { … } /* * advansys_biosparam() * * Translate disk drive geometry if the "BIOS greater than 1 GB" * support is enabled for a drive. * * ip (information pointer) is an int array with the following definition: * ip[0]: heads * ip[1]: sectors * ip[2]: cylinders */ static int advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev, sector_t capacity, int ip[]) { … } /* * First-level interrupt handler. * * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. */ static irqreturn_t advansys_interrupt(int irq, void *dev_id) { … } static bool AscHostReqRiscHalt(PortAddr iop_base) { … } static bool AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) { … } static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) { … } static void advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) { … } /* * Wide Transfers * * If the EEPROM enabled WDTR for the device and the device supports wide * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and * write the new value to the microcode. */ static void advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) { … } /* * Synchronous Transfers * * If the EEPROM enabled SDTR for the device and the device * supports synchronous transfers, then turn on the device's * 'sdtr_able' bit. Write the new value to the microcode. */ static void advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) { … } /* * PPR (Parallel Protocol Request) Capable * * If the device supports DT mode, then it must be PPR capable. * The PPR message will be used in place of the SDTR and WDTR * messages to negotiate synchronous speed and offset, transfer * width, and protocol options. */ static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, AdvPortAddr iop_base, unsigned short tidmask) { … } static void advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) { … } /* * Set the number of commands to queue per device for the * specified host adapter. */ static int advansys_slave_configure(struct scsi_device *sdev) { … } static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp) { … } static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, struct asc_scsi_q *asc_scsi_q) { … } /* * Build scatter-gather list for Adv Library (Wide Board). * * Additional ADV_SG_BLOCK structures will need to be allocated * if the total number of scatter-gather elements exceeds * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are * assumed to be physically contiguous. * * Return: * ADV_SUCCESS(1) - SG List successfully created * ADV_ERROR(-1) - SG List creation failed */ static int adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg) { … } /* * Build a request structure for the Adv Library (Wide Board). * * If an adv_req_t can not be allocated to issue the request, * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. * * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the * microcode for DMA addresses or math operations are byte swapped * to little-endian order. */ static int adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, adv_req_t **adv_reqpp) { … } static int AscSgListToQueue(int sg_list) { … } static uint AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) { … } static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) { … } static uchar AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) { … } /* * void * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) * * Calling/Exit State: * none * * Description: * Output an ASC_SCSI_Q structure to the chip */ static void DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) { … } static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) { … } static int AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) { … } static int AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) { … } #define ASC_SYN_OFFSET_ONE_DISABLE_LIST … static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = …; static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) { … } /* * AdvExeScsiQueue() - Send a request to the RISC microcode program. * * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, * add the carrier to the ICQ (Initiator Command Queue), and tickle the * RISC to notify it a new command is ready to be executed. * * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be * set to SCSI_MAX_RETRY. * * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode * for DMA addresses or math operations are byte swapped to little-endian * order. * * Return: * ADV_SUCCESS(1) - The request was successfully queued. * ADV_BUSY(0) - Resource unavailable; Retry again after pending * request completes. * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure * host IC error. */ static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp) { … } /* * Execute a single 'struct scsi_cmnd'. */ static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) { … } /* * advansys_queuecommand() - interrupt-driven I/O entrypoint. * * This function always returns 0. Command return status is saved * in the 'scp' result field. */ static int advansys_queuecommand_lck(struct scsi_cmnd *scp) { … } static DEF_SCSI_QCMD(advansys_queuecommand) static ushort AscGetEisaChipCfg(PortAddr iop_base) { … } /* * Return the BIOS address of the adapter at the specified * I/O port and with the specified bus type. */ static unsigned short AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type) { … } static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) { … } static unsigned char AscGetChipScsiCtrl(PortAddr iop_base) { … } static unsigned char AscGetChipVersion(PortAddr iop_base, unsigned short bus_type) { … } static int AscStopQueueExe(PortAddr iop_base) { … } static unsigned int AscGetMaxDmaCount(ushort bus_type) { … } static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) { … } static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) { … } static void AscWaitEEPRead(void) { … } static ushort AscReadEEPWord(PortAddr iop_base, uchar addr) { … } static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) { … } static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc) { … } static void AscWaitEEPWrite(void) { … } static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) { … } static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) { … } static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) { … } static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) { … } static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc) { … } static int AscInitGetConfig(struct Scsi_Host *shost) { … } static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) { … } /* * EEPROM Configuration. * * All drivers should use this structure to set the default EEPROM * configuration. The BIOS now uses this structure when it is built. * Additional structure information can be found in a_condor.h where * the structure is defined. * * The *_Field_IsChar structs are needed to correct for endianness. * These values are read from the board 16 bits at a time directly * into the structs. Because some fields are char, the values will be * in the wrong order. The *_Field_IsChar tells when to flip the * bytes. Data read and written to PCI memory is automatically swapped * on big-endian platforms so char fields read as words are actually being * unswapped on big-endian platforms. */ #ifdef CONFIG_PCI static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = …; static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = …; static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = …; static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = …; static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = …; static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = …; /* * Wait for EEPROM command to complete */ static void AdvWaitEEPCmd(AdvPortAddr iop_base) { … } /* * Read the EEPROM from specified location */ static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) { … } /* * Write the EEPROM from 'cfg_buf'. */ static void AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) { … } /* * Write the EEPROM from 'cfg_buf'. */ static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) { … } /* * Write the EEPROM from 'cfg_buf'. */ static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) { … } /* * Read EEPROM configuration into the specified buffer. * * Return a checksum based on the EEPROM configuration read. */ static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) { … } /* * Read EEPROM configuration into the specified buffer. * * Return a checksum based on the EEPROM configuration read. */ static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) { … } /* * Read EEPROM configuration into the specified buffer. * * Return a checksum based on the EEPROM configuration read. */ static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) { … } /* * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while * all of this is done. * * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Note: Chip is stopped on entry. */ static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) { … } /* * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while * all of this is done. * * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Note: Chip is stopped on entry. */ static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) { … } /* * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while * all of this is done. * * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. * * Note: Chip is stopped on entry. */ static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) { … } /* * Initialize the ADV_DVC_VAR structure. * * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. * * For a non-fatal error return a warning code. If there are no warnings * then 0 is returned. */ static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) { … } #endif static const struct scsi_host_template advansys_template = …; static int advansys_wide_init_chip(struct Scsi_Host *shost) { … } static void advansys_wide_free_mem(struct asc_board *board) { … } static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, int bus_type) { … } /* * advansys_release() * * Release resources allocated for a single AdvanSys adapter. */ static int advansys_release(struct Scsi_Host *shost) { … } #define ASC_IOADR_TABLE_MAX_IX … static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = …; static void advansys_vlb_remove(struct device *dev, unsigned int id) { … } /* * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as: * 000: invalid * 001: 10 * 010: 11 * 011: 12 * 100: invalid * 101: 14 * 110: 15 * 111: invalid */ static unsigned int advansys_vlb_irq_no(PortAddr iop_base) { … } static int advansys_vlb_probe(struct device *dev, unsigned int id) { … } static struct isa_driver advansys_vlb_driver = …; static struct eisa_device_id advansys_eisa_table[] = …; MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); /* * EISA is a little more tricky than PCI; each EISA device may have two * channels, and this driver is written to make each channel its own Scsi_Host */ struct eisa_scsi_data { … }; /* * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as: * 000: 10 * 001: 11 * 010: 12 * 011: invalid * 100: 14 * 101: 15 * 110: invalid * 111: invalid */ static unsigned int advansys_eisa_irq_no(struct eisa_device *edev) { … } static int advansys_eisa_probe(struct device *dev) { … } static int advansys_eisa_remove(struct device *dev) { … } static struct eisa_driver advansys_eisa_driver = …; /* PCI Devices supported by this driver */ static struct pci_device_id advansys_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); static void advansys_set_latency(struct pci_dev *pdev) { … } static int advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static void advansys_pci_remove(struct pci_dev *pdev) { … } static struct pci_driver advansys_pci_driver = …; static int __init advansys_init(void) { … } static void __exit advansys_exit(void) { … } module_init(…) …; module_exit(advansys_exit); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …;
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