/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * include/linux/mfd/wm831x/core.h -- Core interface for WM831x * * Copyright 2009 Wolfson Microelectronics PLC. * * Author: Mark Brown <[email protected]> */ #ifndef __MFD_WM831X_CORE_H__ #define __MFD_WM831X_CORE_H__ #include <linux/completion.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/list.h> #include <linux/regmap.h> #include <linux/mfd/wm831x/auxadc.h> #include <linux/mfd/wm831x/pdata.h> #include <linux/of.h> /* * Register values. */ #define WM831X_RESET_ID … #define WM831X_REVISION … #define WM831X_PARENT_ID … #define WM831X_SYSVDD_CONTROL … #define WM831X_THERMAL_MONITORING … #define WM831X_POWER_STATE … #define WM831X_WATCHDOG … #define WM831X_ON_PIN_CONTROL … #define WM831X_RESET_CONTROL … #define WM831X_CONTROL_INTERFACE … #define WM831X_SECURITY_KEY … #define WM831X_SOFTWARE_SCRATCH … #define WM831X_OTP_CONTROL … #define WM831X_GPIO_LEVEL … #define WM831X_SYSTEM_STATUS … #define WM831X_ON_SOURCE … #define WM831X_OFF_SOURCE … #define WM831X_SYSTEM_INTERRUPTS … #define WM831X_INTERRUPT_STATUS_1 … #define WM831X_INTERRUPT_STATUS_2 … #define WM831X_INTERRUPT_STATUS_3 … #define WM831X_INTERRUPT_STATUS_4 … #define WM831X_INTERRUPT_STATUS_5 … #define WM831X_IRQ_CONFIG … #define WM831X_SYSTEM_INTERRUPTS_MASK … #define WM831X_INTERRUPT_STATUS_1_MASK … #define WM831X_INTERRUPT_STATUS_2_MASK … #define WM831X_INTERRUPT_STATUS_3_MASK … #define WM831X_INTERRUPT_STATUS_4_MASK … #define WM831X_INTERRUPT_STATUS_5_MASK … #define WM831X_RTC_WRITE_COUNTER … #define WM831X_RTC_TIME_1 … #define WM831X_RTC_TIME_2 … #define WM831X_RTC_ALARM_1 … #define WM831X_RTC_ALARM_2 … #define WM831X_RTC_CONTROL … #define WM831X_RTC_TRIM … #define WM831X_TOUCH_CONTROL_1 … #define WM831X_TOUCH_CONTROL_2 … #define WM831X_TOUCH_DATA_X … #define WM831X_TOUCH_DATA_Y … #define WM831X_TOUCH_DATA_Z … #define WM831X_AUXADC_DATA … #define WM831X_AUXADC_CONTROL … #define WM831X_AUXADC_SOURCE … #define WM831X_COMPARATOR_CONTROL … #define WM831X_COMPARATOR_1 … #define WM831X_COMPARATOR_2 … #define WM831X_COMPARATOR_3 … #define WM831X_COMPARATOR_4 … #define WM831X_GPIO1_CONTROL … #define WM831X_GPIO2_CONTROL … #define WM831X_GPIO3_CONTROL … #define WM831X_GPIO4_CONTROL … #define WM831X_GPIO5_CONTROL … #define WM831X_GPIO6_CONTROL … #define WM831X_GPIO7_CONTROL … #define WM831X_GPIO8_CONTROL … #define WM831X_GPIO9_CONTROL … #define WM831X_GPIO10_CONTROL … #define WM831X_GPIO11_CONTROL … #define WM831X_GPIO12_CONTROL … #define WM831X_GPIO13_CONTROL … #define WM831X_GPIO14_CONTROL … #define WM831X_GPIO15_CONTROL … #define WM831X_GPIO16_CONTROL … #define WM831X_CHARGER_CONTROL_1 … #define WM831X_CHARGER_CONTROL_2 … #define WM831X_CHARGER_STATUS … #define WM831X_BACKUP_CHARGER_CONTROL … #define WM831X_STATUS_LED_1 … #define WM831X_STATUS_LED_2 … #define WM831X_CURRENT_SINK_1 … #define WM831X_CURRENT_SINK_2 … #define WM831X_DCDC_ENABLE … #define WM831X_LDO_ENABLE … #define WM831X_DCDC_STATUS … #define WM831X_LDO_STATUS … #define WM831X_DCDC_UV_STATUS … #define WM831X_LDO_UV_STATUS … #define WM831X_DC1_CONTROL_1 … #define WM831X_DC1_CONTROL_2 … #define WM831X_DC1_ON_CONFIG … #define WM831X_DC1_SLEEP_CONTROL … #define WM831X_DC1_DVS_CONTROL … #define WM831X_DC2_CONTROL_1 … #define WM831X_DC2_CONTROL_2 … #define WM831X_DC2_ON_CONFIG … #define WM831X_DC2_SLEEP_CONTROL … #define WM831X_DC2_DVS_CONTROL … #define WM831X_DC3_CONTROL_1 … #define WM831X_DC3_CONTROL_2 … #define WM831X_DC3_ON_CONFIG … #define WM831X_DC3_SLEEP_CONTROL … #define WM831X_DC4_CONTROL … #define WM831X_DC4_SLEEP_CONTROL … #define WM832X_DC4_SLEEP_CONTROL … #define WM831X_EPE1_CONTROL … #define WM831X_EPE2_CONTROL … #define WM831X_LDO1_CONTROL … #define WM831X_LDO1_ON_CONTROL … #define WM831X_LDO1_SLEEP_CONTROL … #define WM831X_LDO2_CONTROL … #define WM831X_LDO2_ON_CONTROL … #define WM831X_LDO2_SLEEP_CONTROL … #define WM831X_LDO3_CONTROL … #define WM831X_LDO3_ON_CONTROL … #define WM831X_LDO3_SLEEP_CONTROL … #define WM831X_LDO4_CONTROL … #define WM831X_LDO4_ON_CONTROL … #define WM831X_LDO4_SLEEP_CONTROL … #define WM831X_LDO5_CONTROL … #define WM831X_LDO5_ON_CONTROL … #define WM831X_LDO5_SLEEP_CONTROL … #define WM831X_LDO6_CONTROL … #define WM831X_LDO6_ON_CONTROL … #define WM831X_LDO6_SLEEP_CONTROL … #define WM831X_LDO7_CONTROL … #define WM831X_LDO7_ON_CONTROL … #define WM831X_LDO7_SLEEP_CONTROL … #define WM831X_LDO8_CONTROL … #define WM831X_LDO8_ON_CONTROL … #define WM831X_LDO8_SLEEP_CONTROL … #define WM831X_LDO9_CONTROL … #define WM831X_LDO9_ON_CONTROL … #define WM831X_LDO9_SLEEP_CONTROL … #define WM831X_LDO10_CONTROL … #define WM831X_LDO10_ON_CONTROL … #define WM831X_LDO10_SLEEP_CONTROL … #define WM831X_LDO11_ON_CONTROL … #define WM831X_LDO11_SLEEP_CONTROL … #define WM831X_POWER_GOOD_SOURCE_1 … #define WM831X_POWER_GOOD_SOURCE_2 … #define WM831X_CLOCK_CONTROL_1 … #define WM831X_CLOCK_CONTROL_2 … #define WM831X_FLL_CONTROL_1 … #define WM831X_FLL_CONTROL_2 … #define WM831X_FLL_CONTROL_3 … #define WM831X_FLL_CONTROL_4 … #define WM831X_FLL_CONTROL_5 … #define WM831X_UNIQUE_ID_1 … #define WM831X_UNIQUE_ID_2 … #define WM831X_UNIQUE_ID_3 … #define WM831X_UNIQUE_ID_4 … #define WM831X_UNIQUE_ID_5 … #define WM831X_UNIQUE_ID_6 … #define WM831X_UNIQUE_ID_7 … #define WM831X_UNIQUE_ID_8 … #define WM831X_FACTORY_OTP_ID … #define WM831X_FACTORY_OTP_1 … #define WM831X_FACTORY_OTP_2 … #define WM831X_FACTORY_OTP_3 … #define WM831X_FACTORY_OTP_4 … #define WM831X_FACTORY_OTP_5 … #define WM831X_CUSTOMER_OTP_ID … #define WM831X_DC1_OTP_CONTROL … #define WM831X_DC2_OTP_CONTROL … #define WM831X_DC3_OTP_CONTROL … #define WM831X_LDO1_2_OTP_CONTROL … #define WM831X_LDO3_4_OTP_CONTROL … #define WM831X_LDO5_6_OTP_CONTROL … #define WM831X_LDO7_8_OTP_CONTROL … #define WM831X_LDO9_10_OTP_CONTROL … #define WM831X_LDO11_EPE_CONTROL … #define WM831X_GPIO1_OTP_CONTROL … #define WM831X_GPIO2_OTP_CONTROL … #define WM831X_GPIO3_OTP_CONTROL … #define WM831X_GPIO4_OTP_CONTROL … #define WM831X_GPIO5_OTP_CONTROL … #define WM831X_GPIO6_OTP_CONTROL … #define WM831X_DBE_CHECK_DATA … /* * R0 (0x00) - Reset ID */ #define WM831X_CHIP_ID_MASK … #define WM831X_CHIP_ID_SHIFT … #define WM831X_CHIP_ID_WIDTH … /* * R1 (0x01) - Revision */ #define WM831X_PARENT_REV_MASK … #define WM831X_PARENT_REV_SHIFT … #define WM831X_PARENT_REV_WIDTH … #define WM831X_CHILD_REV_MASK … #define WM831X_CHILD_REV_SHIFT … #define WM831X_CHILD_REV_WIDTH … /* * R16384 (0x4000) - Parent ID */ #define WM831X_PARENT_ID_MASK … #define WM831X_PARENT_ID_SHIFT … #define WM831X_PARENT_ID_WIDTH … /* * R16389 (0x4005) - ON Pin Control */ #define WM831X_ON_PIN_SECACT_MASK … #define WM831X_ON_PIN_SECACT_SHIFT … #define WM831X_ON_PIN_SECACT_WIDTH … #define WM831X_ON_PIN_PRIMACT_MASK … #define WM831X_ON_PIN_PRIMACT_SHIFT … #define WM831X_ON_PIN_PRIMACT_WIDTH … #define WM831X_ON_PIN_STS … #define WM831X_ON_PIN_STS_MASK … #define WM831X_ON_PIN_STS_SHIFT … #define WM831X_ON_PIN_STS_WIDTH … #define WM831X_ON_PIN_TO_MASK … #define WM831X_ON_PIN_TO_SHIFT … #define WM831X_ON_PIN_TO_WIDTH … /* * R16528 (0x4090) - Clock Control 1 */ #define WM831X_CLKOUT_ENA … #define WM831X_CLKOUT_ENA_MASK … #define WM831X_CLKOUT_ENA_SHIFT … #define WM831X_CLKOUT_ENA_WIDTH … #define WM831X_CLKOUT_OD … #define WM831X_CLKOUT_OD_MASK … #define WM831X_CLKOUT_OD_SHIFT … #define WM831X_CLKOUT_OD_WIDTH … #define WM831X_CLKOUT_SLOT_MASK … #define WM831X_CLKOUT_SLOT_SHIFT … #define WM831X_CLKOUT_SLOT_WIDTH … #define WM831X_CLKOUT_SLPSLOT_MASK … #define WM831X_CLKOUT_SLPSLOT_SHIFT … #define WM831X_CLKOUT_SLPSLOT_WIDTH … #define WM831X_CLKOUT_SRC … #define WM831X_CLKOUT_SRC_MASK … #define WM831X_CLKOUT_SRC_SHIFT … #define WM831X_CLKOUT_SRC_WIDTH … /* * R16529 (0x4091) - Clock Control 2 */ #define WM831X_XTAL_INH … #define WM831X_XTAL_INH_MASK … #define WM831X_XTAL_INH_SHIFT … #define WM831X_XTAL_INH_WIDTH … #define WM831X_XTAL_ENA … #define WM831X_XTAL_ENA_MASK … #define WM831X_XTAL_ENA_SHIFT … #define WM831X_XTAL_ENA_WIDTH … #define WM831X_XTAL_BKUPENA … #define WM831X_XTAL_BKUPENA_MASK … #define WM831X_XTAL_BKUPENA_SHIFT … #define WM831X_XTAL_BKUPENA_WIDTH … #define WM831X_FLL_AUTO … #define WM831X_FLL_AUTO_MASK … #define WM831X_FLL_AUTO_SHIFT … #define WM831X_FLL_AUTO_WIDTH … #define WM831X_FLL_AUTO_FREQ_MASK … #define WM831X_FLL_AUTO_FREQ_SHIFT … #define WM831X_FLL_AUTO_FREQ_WIDTH … /* * R16530 (0x4092) - FLL Control 1 */ #define WM831X_FLL_FRAC … #define WM831X_FLL_FRAC_MASK … #define WM831X_FLL_FRAC_SHIFT … #define WM831X_FLL_FRAC_WIDTH … #define WM831X_FLL_OSC_ENA … #define WM831X_FLL_OSC_ENA_MASK … #define WM831X_FLL_OSC_ENA_SHIFT … #define WM831X_FLL_OSC_ENA_WIDTH … #define WM831X_FLL_ENA … #define WM831X_FLL_ENA_MASK … #define WM831X_FLL_ENA_SHIFT … #define WM831X_FLL_ENA_WIDTH … /* * R16531 (0x4093) - FLL Control 2 */ #define WM831X_FLL_OUTDIV_MASK … #define WM831X_FLL_OUTDIV_SHIFT … #define WM831X_FLL_OUTDIV_WIDTH … #define WM831X_FLL_CTRL_RATE_MASK … #define WM831X_FLL_CTRL_RATE_SHIFT … #define WM831X_FLL_CTRL_RATE_WIDTH … #define WM831X_FLL_FRATIO_MASK … #define WM831X_FLL_FRATIO_SHIFT … #define WM831X_FLL_FRATIO_WIDTH … /* * R16532 (0x4094) - FLL Control 3 */ #define WM831X_FLL_K_MASK … #define WM831X_FLL_K_SHIFT … #define WM831X_FLL_K_WIDTH … /* * R16533 (0x4095) - FLL Control 4 */ #define WM831X_FLL_N_MASK … #define WM831X_FLL_N_SHIFT … #define WM831X_FLL_N_WIDTH … #define WM831X_FLL_GAIN_MASK … #define WM831X_FLL_GAIN_SHIFT … #define WM831X_FLL_GAIN_WIDTH … /* * R16534 (0x4096) - FLL Control 5 */ #define WM831X_FLL_CLK_REF_DIV_MASK … #define WM831X_FLL_CLK_REF_DIV_SHIFT … #define WM831X_FLL_CLK_REF_DIV_WIDTH … #define WM831X_FLL_CLK_SRC_MASK … #define WM831X_FLL_CLK_SRC_SHIFT … #define WM831X_FLL_CLK_SRC_WIDTH … struct regulator_dev; struct irq_domain; #define WM831X_NUM_IRQ_REGS … #define WM831X_NUM_GPIO_REGS … enum wm831x_parent { … }; struct wm831x; wm831x_auxadc_read_fn; struct wm831x { … }; /* Device I/O API */ int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg); int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg, unsigned short val); void wm831x_reg_lock(struct wm831x *wm831x); int wm831x_reg_unlock(struct wm831x *wm831x); int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg, unsigned short mask, unsigned short val); int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, int count, u16 *buf); int wm831x_device_init(struct wm831x *wm831x, int irq); int wm831x_device_suspend(struct wm831x *wm831x); void wm831x_device_shutdown(struct wm831x *wm831x); int wm831x_irq_init(struct wm831x *wm831x, int irq); void wm831x_irq_exit(struct wm831x *wm831x); void wm831x_auxadc_init(struct wm831x *wm831x); static inline int wm831x_irq(struct wm831x *wm831x, int irq) { … } extern struct regmap_config wm831x_regmap_config; extern const struct of_device_id wm831x_of_match[]; #endif
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