/* * Timer/Counter Unit (TC) registers. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __SOC_ATMEL_TCB_H #define __SOC_ATMEL_TCB_H #include <linux/compiler.h> #include <linux/list.h> /* * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds * three general-purpose 16-bit timers. These timers share one register bank. * Depending on the SOC, each timer may have its own clock and IRQ, or those * may be shared by the whole TC block. * * These TC blocks may have up to nine external pins: TCLK0..2 signals for * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM * or triggering. Those pins need to be set up for use with the TC block, * else they will be used as GPIOs or for a different controller. * * Although we expect each TC block to have a platform_device node, those * nodes are not what drivers bind to. Instead, they ask for a specific * TC block, by number ... which is a common approach on systems with many * timers. Then they use clk_get() and platform_get_irq() to get clock and * IRQ resources. */ struct clk; /** * struct atmel_tcb_config - SoC data for a Timer/Counter Block * @counter_width: size in bits of a timer counter register * @has_gclk: boolean indicating if a timer counter has a generic clock * @has_qdec: boolean indicating if a timer counter has a quadrature * decoder. */ struct atmel_tcb_config { … }; /** * struct atmel_tc - information about a Timer/Counter Block * @pdev: physical device * @regs: mapping through which the I/O registers can be accessed * @id: block id * @tcb_config: configuration data from SoC * @irq: irq for each of the three channels * @clk: internal clock source for each of the three channels * @node: list node, for tclib internal use * @allocated: if already used, for tclib internal use * * On some platforms, each TC channel has its own clocks and IRQs, * while on others, all TC channels share the same clock and IRQ. * Drivers should clk_enable() all the clocks they need even though * all the entries in @clk may point to the same physical clock. * Likewise, drivers should request irqs independently for each * channel, but they must use IRQF_SHARED in case some of the entries * in @irq are actually the same IRQ. */ struct atmel_tc { … }; /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */ extern const u8 atmel_tc_divisors[5]; /* * Two registers have block-wide controls. These are: configuring the three * "external" clocks (or event sources) used by the timer channels; and * synchronizing the timers by resetting them all at once. * * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2 * signals. Or, it can mean "external to timer", using the TIOA output from * one of the other two timers that's being run in waveform mode. */ #define ATMEL_TC_BCR … #define ATMEL_TC_SYNC … #define ATMEL_TC_BMR … #define ATMEL_TC_TC0XC0S … #define ATMEL_TC_TC0XC0S_TCLK0 … #define ATMEL_TC_TC0XC0S_NONE … #define ATMEL_TC_TC0XC0S_TIOA1 … #define ATMEL_TC_TC0XC0S_TIOA2 … #define ATMEL_TC_TC1XC1S … #define ATMEL_TC_TC1XC1S_TCLK1 … #define ATMEL_TC_TC1XC1S_NONE … #define ATMEL_TC_TC1XC1S_TIOA0 … #define ATMEL_TC_TC1XC1S_TIOA2 … #define ATMEL_TC_TC2XC2S … #define ATMEL_TC_TC2XC2S_TCLK2 … #define ATMEL_TC_TC2XC2S_NONE … #define ATMEL_TC_TC2XC2S_TIOA0 … #define ATMEL_TC_TC2XC2S_TIOA1 … /* * Each TC block has three "channels", each with one counter and controls. * * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection * when it's not "external") is silicon-specific. AT91 platforms use one * set of definitions; AVR32 platforms use a different set. Don't hard-wire * such knowledge into your code, use the global "atmel_tc_divisors" ... * where index N is the divisor for clock N+1, else zero to indicate it uses * the 32 KiHz clock. * * The timers can be chained in various ways, and operated in "waveform" * generation mode (including PWM) or "capture" mode (to time events). In * both modes, behavior can be configured in many ways. * * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a * PWM output, and TIOB as either another PWM or as a trigger. Capture mode * uses them only as inputs. */ #define ATMEL_TC_CHAN(idx) … #define ATMEL_TC_REG(idx, reg) … #define ATMEL_TC_CCR … #define ATMEL_TC_CLKEN … #define ATMEL_TC_CLKDIS … #define ATMEL_TC_SWTRG … #define ATMEL_TC_CMR … /* Both modes share some CMR bits */ #define ATMEL_TC_TCCLKS … #define ATMEL_TC_TIMER_CLOCK1 … #define ATMEL_TC_TIMER_CLOCK2 … #define ATMEL_TC_TIMER_CLOCK3 … #define ATMEL_TC_TIMER_CLOCK4 … #define ATMEL_TC_TIMER_CLOCK5 … #define ATMEL_TC_XC0 … #define ATMEL_TC_XC1 … #define ATMEL_TC_XC2 … #define ATMEL_TC_CLKI … #define ATMEL_TC_BURST … #define ATMEL_TC_GATE_NONE … #define ATMEL_TC_GATE_XC0 … #define ATMEL_TC_GATE_XC1 … #define ATMEL_TC_GATE_XC2 … #define ATMEL_TC_WAVE … /* CAPTURE mode CMR bits */ #define ATMEL_TC_LDBSTOP … #define ATMEL_TC_LDBDIS … #define ATMEL_TC_ETRGEDG … #define ATMEL_TC_ETRGEDG_NONE … #define ATMEL_TC_ETRGEDG_RISING … #define ATMEL_TC_ETRGEDG_FALLING … #define ATMEL_TC_ETRGEDG_BOTH … #define ATMEL_TC_ABETRG … #define ATMEL_TC_CPCTRG … #define ATMEL_TC_LDRA … #define ATMEL_TC_LDRA_NONE … #define ATMEL_TC_LDRA_RISING … #define ATMEL_TC_LDRA_FALLING … #define ATMEL_TC_LDRA_BOTH … #define ATMEL_TC_LDRB … #define ATMEL_TC_LDRB_NONE … #define ATMEL_TC_LDRB_RISING … #define ATMEL_TC_LDRB_FALLING … #define ATMEL_TC_LDRB_BOTH … /* WAVEFORM mode CMR bits */ #define ATMEL_TC_CPCSTOP … #define ATMEL_TC_CPCDIS … #define ATMEL_TC_EEVTEDG … #define ATMEL_TC_EEVTEDG_NONE … #define ATMEL_TC_EEVTEDG_RISING … #define ATMEL_TC_EEVTEDG_FALLING … #define ATMEL_TC_EEVTEDG_BOTH … #define ATMEL_TC_EEVT … #define ATMEL_TC_EEVT_TIOB … #define ATMEL_TC_EEVT_XC0 … #define ATMEL_TC_EEVT_XC1 … #define ATMEL_TC_EEVT_XC2 … #define ATMEL_TC_ENETRG … #define ATMEL_TC_WAVESEL … #define ATMEL_TC_WAVESEL_UP … #define ATMEL_TC_WAVESEL_UPDOWN … #define ATMEL_TC_WAVESEL_UP_AUTO … #define ATMEL_TC_WAVESEL_UPDOWN_AUTO … #define ATMEL_TC_ACPA … #define ATMEL_TC_ACPA_NONE … #define ATMEL_TC_ACPA_SET … #define ATMEL_TC_ACPA_CLEAR … #define ATMEL_TC_ACPA_TOGGLE … #define ATMEL_TC_ACPC … #define ATMEL_TC_ACPC_NONE … #define ATMEL_TC_ACPC_SET … #define ATMEL_TC_ACPC_CLEAR … #define ATMEL_TC_ACPC_TOGGLE … #define ATMEL_TC_AEEVT … #define ATMEL_TC_AEEVT_NONE … #define ATMEL_TC_AEEVT_SET … #define ATMEL_TC_AEEVT_CLEAR … #define ATMEL_TC_AEEVT_TOGGLE … #define ATMEL_TC_ASWTRG … #define ATMEL_TC_ASWTRG_NONE … #define ATMEL_TC_ASWTRG_SET … #define ATMEL_TC_ASWTRG_CLEAR … #define ATMEL_TC_ASWTRG_TOGGLE … #define ATMEL_TC_BCPB … #define ATMEL_TC_BCPB_NONE … #define ATMEL_TC_BCPB_SET … #define ATMEL_TC_BCPB_CLEAR … #define ATMEL_TC_BCPB_TOGGLE … #define ATMEL_TC_BCPC … #define ATMEL_TC_BCPC_NONE … #define ATMEL_TC_BCPC_SET … #define ATMEL_TC_BCPC_CLEAR … #define ATMEL_TC_BCPC_TOGGLE … #define ATMEL_TC_BEEVT … #define ATMEL_TC_BEEVT_NONE … #define ATMEL_TC_BEEVT_SET … #define ATMEL_TC_BEEVT_CLEAR … #define ATMEL_TC_BEEVT_TOGGLE … #define ATMEL_TC_BSWTRG … #define ATMEL_TC_BSWTRG_NONE … #define ATMEL_TC_BSWTRG_SET … #define ATMEL_TC_BSWTRG_CLEAR … #define ATMEL_TC_BSWTRG_TOGGLE … #define ATMEL_TC_CV … #define ATMEL_TC_RA … #define ATMEL_TC_RB … #define ATMEL_TC_RC … #define ATMEL_TC_SR … /* Status-only flags */ #define ATMEL_TC_CLKSTA … #define ATMEL_TC_MTIOA … #define ATMEL_TC_MTIOB … #define ATMEL_TC_IER … #define ATMEL_TC_IDR … #define ATMEL_TC_IMR … /* Status and IRQ flags */ #define ATMEL_TC_COVFS … #define ATMEL_TC_LOVRS … #define ATMEL_TC_CPAS … #define ATMEL_TC_CPBS … #define ATMEL_TC_CPCS … #define ATMEL_TC_LDRAS … #define ATMEL_TC_LDRBS … #define ATMEL_TC_ETRGS … #define ATMEL_TC_ALL_IRQ … #endif
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