// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Stefan Agner <[email protected]> * Copyright (C) 2014-2015 Lucas Stach <[email protected]> * Copyright (C) 2012 Avionic Design GmbH */ #include <linux/clk.h> #include <linux/completion.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/mtd/partitions.h> #include <linux/mtd/rawnand.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <soc/tegra/common.h> #define COMMAND … #define COMMAND_GO … #define COMMAND_CLE … #define COMMAND_ALE … #define COMMAND_PIO … #define COMMAND_TX … #define COMMAND_RX … #define COMMAND_SEC_CMD … #define COMMAND_AFT_DAT … #define COMMAND_TRANS_SIZE(size) … #define COMMAND_A_VALID … #define COMMAND_B_VALID … #define COMMAND_RD_STATUS_CHK … #define COMMAND_RBSY_CHK … #define COMMAND_CE(x) … #define COMMAND_CLE_SIZE(size) … #define COMMAND_ALE_SIZE(size) … #define STATUS … #define ISR … #define ISR_CORRFAIL_ERR … #define ISR_UND … #define ISR_OVR … #define ISR_CMD_DONE … #define ISR_ECC_ERR … #define IER … #define IER_ERR_TRIG_VAL(x) … #define IER_UND … #define IER_OVR … #define IER_CMD_DONE … #define IER_ECC_ERR … #define IER_GIE … #define CONFIG … #define CONFIG_HW_ECC … #define CONFIG_ECC_SEL … #define CONFIG_ERR_COR … #define CONFIG_PIPE_EN … #define CONFIG_TVAL_4 … #define CONFIG_TVAL_6 … #define CONFIG_TVAL_8 … #define CONFIG_SKIP_SPARE … #define CONFIG_BUS_WIDTH_16 … #define CONFIG_COM_BSY … #define CONFIG_PS_256 … #define CONFIG_PS_512 … #define CONFIG_PS_1024 … #define CONFIG_PS_2048 … #define CONFIG_PS_4096 … #define CONFIG_SKIP_SPARE_SIZE_4 … #define CONFIG_SKIP_SPARE_SIZE_8 … #define CONFIG_SKIP_SPARE_SIZE_12 … #define CONFIG_SKIP_SPARE_SIZE_16 … #define CONFIG_TAG_BYTE_SIZE(x) … #define TIMING_1 … #define TIMING_TRP_RESP(x) … #define TIMING_TWB(x) … #define TIMING_TCR_TAR_TRR(x) … #define TIMING_TWHR(x) … #define TIMING_TCS(x) … #define TIMING_TWH(x) … #define TIMING_TWP(x) … #define TIMING_TRH(x) … #define TIMING_TRP(x) … #define RESP … #define TIMING_2 … #define TIMING_TADL(x) … #define CMD_REG1 … #define CMD_REG2 … #define ADDR_REG1 … #define ADDR_REG2 … #define DMA_MST_CTRL … #define DMA_MST_CTRL_GO … #define DMA_MST_CTRL_IN … #define DMA_MST_CTRL_OUT … #define DMA_MST_CTRL_PERF_EN … #define DMA_MST_CTRL_IE_DONE … #define DMA_MST_CTRL_REUSE … #define DMA_MST_CTRL_BURST_1 … #define DMA_MST_CTRL_BURST_4 … #define DMA_MST_CTRL_BURST_8 … #define DMA_MST_CTRL_BURST_16 … #define DMA_MST_CTRL_IS_DONE … #define DMA_MST_CTRL_EN_A … #define DMA_MST_CTRL_EN_B … #define DMA_CFG_A … #define DMA_CFG_B … #define FIFO_CTRL … #define FIFO_CTRL_CLR_ALL … #define DATA_PTR … #define TAG_PTR … #define ECC_PTR … #define DEC_STATUS … #define DEC_STATUS_A_ECC_FAIL … #define DEC_STATUS_ERR_COUNT_MASK … #define DEC_STATUS_ERR_COUNT_SHIFT … #define HWSTATUS_CMD … #define HWSTATUS_MASK … #define HWSTATUS_RDSTATUS_MASK(x) … #define HWSTATUS_RDSTATUS_VALUE(x) … #define HWSTATUS_RBSY_MASK(x) … #define HWSTATUS_RBSY_VALUE(x) … #define BCH_CONFIG … #define BCH_ENABLE … #define BCH_TVAL_4 … #define BCH_TVAL_8 … #define BCH_TVAL_14 … #define BCH_TVAL_16 … #define DEC_STAT_RESULT … #define DEC_STAT_BUF … #define DEC_STAT_BUF_FAIL_SEC_FLAG_MASK … #define DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT … #define DEC_STAT_BUF_CORR_SEC_FLAG_MASK … #define DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT … #define DEC_STAT_BUF_MAX_CORR_CNT_MASK … #define DEC_STAT_BUF_MAX_CORR_CNT_SHIFT … #define OFFSET(val, off) … #define SKIP_SPARE_BYTES … #define BITS_PER_STEP_RS … #define BITS_PER_STEP_BCH … #define INT_MASK … #define HWSTATUS_CMD_DEFAULT … #define HWSTATUS_MASK_DEFAULT … struct tegra_nand_controller { … }; struct tegra_nand_chip { … }; static inline struct tegra_nand_controller * to_tegra_ctrl(struct nand_controller *hw_ctrl) { … } static inline struct tegra_nand_chip *to_tegra_chip(struct nand_chip *chip) { … } static int tegra_nand_ooblayout_rs_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static int tegra_nand_ooblayout_no_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const struct mtd_ooblayout_ops tegra_nand_oob_rs_ops = …; static int tegra_nand_ooblayout_bch_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion) { … } static const struct mtd_ooblayout_ops tegra_nand_oob_bch_ops = …; static irqreturn_t tegra_nand_irq(int irq, void *data) { … } static const char * const tegra_nand_reg_names[] = …; static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl) { … } static void tegra_nand_controller_abort(struct tegra_nand_controller *ctrl) { … } static int tegra_nand_cmd(struct nand_chip *chip, const struct nand_subop *subop) { … } static const struct nand_op_parser tegra_nand_op_parser = …; static void tegra_nand_select_target(struct nand_chip *chip, unsigned int die_nr) { … } static int tegra_nand_exec_op(struct nand_chip *chip, const struct nand_operation *op, bool check_only) { … } static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl, struct nand_chip *chip, bool enable) { … } static int tegra_nand_page_xfer(struct mtd_info *mtd, struct nand_chip *chip, void *buf, void *oob_buf, int oob_len, int page, bool read) { … } static int tegra_nand_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_required, int page) { … } static int tegra_nand_write_page_raw(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { … } static int tegra_nand_read_oob(struct nand_chip *chip, int page) { … } static int tegra_nand_write_oob(struct nand_chip *chip, int page) { … } static int tegra_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf, int oob_required, int page) { … } static int tegra_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { … } static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl, const struct nand_sdr_timings *timings) { … } static int tegra_nand_setup_interface(struct nand_chip *chip, int csline, const struct nand_interface_config *conf) { … } static const int rs_strength_bootable[] = …; static const int rs_strength[] = …; static const int bch_strength_bootable[] = …; static const int bch_strength[] = …; static int tegra_nand_get_strength(struct nand_chip *chip, const int *strength, int strength_len, int bits_per_step, int oobsize) { … } static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize) { … } static int tegra_nand_attach_chip(struct nand_chip *chip) { … } static const struct nand_controller_ops tegra_nand_controller_ops = …; static int tegra_nand_chips_init(struct device *dev, struct tegra_nand_controller *ctrl) { … } static int tegra_nand_probe(struct platform_device *pdev) { … } static void tegra_nand_remove(struct platform_device *pdev) { … } static int __maybe_unused tegra_nand_runtime_resume(struct device *dev) { … } static int __maybe_unused tegra_nand_runtime_suspend(struct device *dev) { … } static const struct dev_pm_ops tegra_nand_pm = …; static const struct of_device_id tegra_nand_of_match[] = …; MODULE_DEVICE_TABLE(of, tegra_nand_of_match); static struct platform_driver tegra_nand_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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