/* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2021 Xilinx * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> * Davorin Mista <[email protected]> * Jolly Shah <[email protected]> * Rajan Vaja <[email protected]> */ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ #include <linux/types.h> #include <linux/err.h> #define ZYNQMP_PM_VERSION_MAJOR … #define ZYNQMP_PM_VERSION_MINOR … #define ZYNQMP_PM_VERSION … #define ZYNQMP_TZ_VERSION_MAJOR … #define ZYNQMP_TZ_VERSION_MINOR … #define ZYNQMP_TZ_VERSION … /* SMC SIP service Call Function Identifier Prefix */ #define PM_SIP_SVC … /* PM API versions */ #define PM_API_VERSION_1 … #define PM_API_VERSION_2 … #define PM_PINCTRL_PARAM_SET_VERSION … #define ZYNQMP_FAMILY_CODE … #define VERSAL_FAMILY_CODE … /* When all subfamily of platform need to support */ #define ALL_SUB_FAMILY_CODE … #define VERSAL_SUB_FAMILY_CODE … #define VERSALNET_SUB_FAMILY_CODE … #define FAMILY_CODE_MASK … #define SUB_FAMILY_CODE_MASK … #define API_ID_MASK … #define MODULE_ID_MASK … /* Firmware feature check version mask */ #define FIRMWARE_VERSION_MASK … /* ATF only commands */ #define TF_A_PM_REGISTER_SGI … #define PM_GET_TRUSTZONE_VERSION … #define PM_SET_SUSPEND_MODE … #define GET_CALLBACK_DATA … /* Number of 32bits values in payload */ #define PAYLOAD_ARG_CNT … /* Number of arguments for a callback */ #define CB_ARG_CNT … /* Payload size (consists of callback API ID + arguments) */ #define CB_PAYLOAD_SIZE … #define ZYNQMP_PM_MAX_QOS … #define GSS_NUM_REGS … /* Node capabilities */ #define ZYNQMP_PM_CAPABILITY_ACCESS … #define ZYNQMP_PM_CAPABILITY_CONTEXT … #define ZYNQMP_PM_CAPABILITY_WAKEUP … #define ZYNQMP_PM_CAPABILITY_UNUSABLE … /* Loader commands */ #define PM_LOAD_PDI … #define PDI_SRC_DDR … /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration */ #define XILINX_ZYNQMP_PM_FPGA_FULL … #define XILINX_ZYNQMP_PM_FPGA_PARTIAL … /* FPGA Status Reg */ #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET … #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG … /* * Node IDs for the Error Events. */ #define VERSAL_EVENT_ERROR_PMC_ERR1 … #define VERSAL_EVENT_ERROR_PMC_ERR2 … #define VERSAL_EVENT_ERROR_PSM_ERR1 … #define VERSAL_EVENT_ERROR_PSM_ERR2 … #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 … #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 … #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 … #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 … #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 … #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 … #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 … /* ZynqMP SD tap delay tuning */ #define SD_ITAPDLY … #define SD_OTAPDLYSEL … /** * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error. */ #define XPM_EVENT_ERROR_MASK_DDRMC_CR … /** * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error. */ #define XPM_EVENT_ERROR_MASK_DDRMC_NCR … #define XPM_EVENT_ERROR_MASK_NOC_NCR … #define XPM_EVENT_ERROR_MASK_NOC_CR … enum pm_module_id { … }; enum pm_api_cb_id { … }; enum pm_api_id { … }; /* PMU-FW return status codes */ enum pm_ret_status { … }; enum pm_ioctl_id { … }; enum pm_query_id { … }; enum rpu_oper_mode { … }; enum rpu_boot_mem { … }; enum rpu_tcm_comb { … }; enum zynqmp_pm_reset_action { … }; enum zynqmp_pm_reset { … }; enum zynqmp_pm_suspend_reason { … }; enum zynqmp_pm_request_ack { … }; enum pm_node_id { … }; enum tap_delay_type { … }; enum dll_reset_type { … }; enum pm_pinctrl_config_param { … }; enum pm_pinctrl_slew_rate { … }; enum pm_pinctrl_bias_status { … }; enum pm_pinctrl_pull_ctrl { … }; enum pm_pinctrl_schmitt_cmos { … }; enum pm_pinctrl_drive_strength { … }; enum pm_pinctrl_tri_state { … }; enum zynqmp_pm_shutdown_type { … }; enum zynqmp_pm_shutdown_subtype { … }; enum tap_delay_signal_type { … }; enum tap_delay_bypass_ctrl { … }; enum ospi_mux_select_type { … }; enum pm_feature_config_id { … }; /** * enum pm_sd_config_type - PM SD configuration. * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2 * @SD_CONFIG_FIXED: To set fixed config registers */ enum pm_sd_config_type { … }; /** * enum pm_gem_config_type - PM GEM configuration. * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register * @GEM_CONFIG_FIXED: To set fixed config registers */ enum pm_gem_config_type { … }; /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID * @arg1: Argument 1 of query data * @arg2: Argument 2 of query data * @arg3: Argument 3 of query data */ struct zynqmp_pm_query_data { … }; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...); #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) int zynqmp_pm_get_api_version(u32 *version); int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily); int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); int zynqmp_pm_clock_enable(u32 clock_id); int zynqmp_pm_clock_disable(u32 clock_id); int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select); int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, const enum zynqmp_pm_reset_action assert_flag); int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); int zynqmp_pm_bootmode_write(u32 ps_mode); int zynqmp_pm_init_finalize(void); int zynqmp_pm_set_suspend_mode(u32 mode); int zynqmp_pm_request_node(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_release_node(const u32 node); int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_efuse_access(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); int zynqmp_pm_fpga_get_config_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); int zynqmp_pm_read_ggs(u32 index, u32 *value); int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); int zynqmp_pm_pinctrl_request(const u32 pin); int zynqmp_pm_pinctrl_release(const u32 pin); int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value); int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value); int zynqmp_pm_load_pdi(const u32 src, const u64 address); int zynqmp_pm_register_notifier(const u32 node, const u32 event, const u32 wake, const u32 enable); int zynqmp_pm_feature(const u32 api_id); int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); int zynqmp_pm_force_pwrdwn(const u32 target, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_request_wake(const u32 node, const bool set_addr, const u64 address, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode); int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode); int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); #else static inline int zynqmp_pm_get_api_version(u32 *version) { … } static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) { … } static inline int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily) { … } static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) { … } static inline int zynqmp_pm_clock_enable(u32 clock_id) { … } static inline int zynqmp_pm_clock_disable(u32 clock_id) { … } static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) { … } static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { … } static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) { … } static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) { … } static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) { … } static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) { … } static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) { … } static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) { … } static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) { … } static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) { … } static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) { … } static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select) { … } static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, const enum zynqmp_pm_reset_action assert_flag) { … } static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status) { … } static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) { … } static inline int zynqmp_pm_bootmode_write(u32 ps_mode) { … } static inline int zynqmp_pm_init_finalize(void) { … } static inline int zynqmp_pm_set_suspend_mode(u32 mode) { … } static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack) { … } static inline int zynqmp_pm_release_node(const u32 node) { … } static inline int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack) { … } static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) { … } static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) { … } static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) { … } static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { … } static inline int zynqmp_pm_fpga_get_status(u32 *value) { … } static inline int zynqmp_pm_fpga_get_config_status(u32 *value) { … } static inline int zynqmp_pm_write_ggs(u32 index, u32 value) { … } static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) { … } static inline int zynqmp_pm_write_pggs(u32 index, u32 value) { … } static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) { … } static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value) { … } static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) { … } static inline int zynqmp_pm_set_boot_health_status(u32 value) { … } static inline int zynqmp_pm_pinctrl_request(const u32 pin) { … } static inline int zynqmp_pm_pinctrl_release(const u32 pin) { … } static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) { … } static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) { … } static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value) { … } static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value) { … } static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) { … } static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event, const u32 wake, const u32 enable) { … } static inline int zynqmp_pm_feature(const u32 api_id) { … } static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value) { … } static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload) { … } static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) { … } static inline int zynqmp_pm_force_pwrdwn(const u32 target, const enum zynqmp_pm_request_ack ack) { … } static inline int zynqmp_pm_request_wake(const u32 node, const bool set_addr, const u64 address, const enum zynqmp_pm_request_ack ack) { … } static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) { … } static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) { … } static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) { … } static inline int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) { … } static inline int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) { … } #endif #endif /* __FIRMWARE_ZYNQMP_H__ */
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