/* SPDX-License-Identifier: GPL-2.0 */ /* HWMON driver for Aquantia PHY * * Author: Nikita Yushchenko <[email protected]> * Author: Andrew Lunn <[email protected]> * Author: Heiner Kallweit <[email protected]> */ #ifndef AQUANTIA_H #define AQUANTIA_H #include <linux/device.h> #include <linux/phy.h> /* Vendor specific 1, MDIO_MMD_VEND1 */ #define VEND1_GLOBAL_SC … #define VEND1_GLOBAL_SC_SOFT_RESET … #define VEND1_GLOBAL_SC_LOW_POWER … #define VEND1_GLOBAL_FW_ID … #define VEND1_GLOBAL_FW_ID_MAJOR … #define VEND1_GLOBAL_FW_ID_MINOR … #define VEND1_GLOBAL_MAILBOX_INTERFACE1 … #define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE … #define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE … #define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET … #define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY … #define VEND1_GLOBAL_MAILBOX_INTERFACE2 … #define VEND1_GLOBAL_MAILBOX_INTERFACE3 … #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK … #define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x) … #define VEND1_GLOBAL_MAILBOX_INTERFACE4 … #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK … #define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x) … #define VEND1_GLOBAL_MAILBOX_INTERFACE5 … #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK … #define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x) … #define VEND1_GLOBAL_MAILBOX_INTERFACE6 … #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK … #define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x) … /* The following registers all have similar layouts; first the registers... */ #define VEND1_GLOBAL_CFG_10M … #define VEND1_GLOBAL_CFG_100M … #define VEND1_GLOBAL_CFG_1G … #define VEND1_GLOBAL_CFG_2_5G … #define VEND1_GLOBAL_CFG_5G … #define VEND1_GLOBAL_CFG_10G … /* ...and now the fields */ #define VEND1_GLOBAL_CFG_SERDES_MODE … #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI … #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII … #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII … #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G … #define VEND1_GLOBAL_CFG_RATE_ADAPT … #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE … #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX … #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE … /* Vendor specific 1, MDIO_MMD_VEND2 */ #define VEND1_GLOBAL_CONTROL2 … #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST … #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD … #define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL … #define VEND1_GLOBAL_LED_PROV … #define AQR_LED_PROV(x) … #define VEND1_GLOBAL_LED_PROV_LINK2500 … #define VEND1_GLOBAL_LED_PROV_LINK5000 … #define VEND1_GLOBAL_LED_PROV_FORCE_ON … #define VEND1_GLOBAL_LED_PROV_LINK10000 … #define VEND1_GLOBAL_LED_PROV_LINK1000 … #define VEND1_GLOBAL_LED_PROV_LINK100 … #define VEND1_GLOBAL_LED_PROV_RX_ACT … #define VEND1_GLOBAL_LED_PROV_TX_ACT … #define VEND1_GLOBAL_LED_PROV_ACT_STRETCH … #define VEND1_GLOBAL_LED_PROV_LINK_MASK … #define VEND1_GLOBAL_LED_DRIVE … #define VEND1_GLOBAL_LED_DRIVE_VDD … #define AQR_LED_DRIVE(x) … #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL … #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL … #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN … #define VEND1_THERMAL_PROV_LOW_TEMP_WARN … #define VEND1_THERMAL_STAT1 … #define VEND1_THERMAL_STAT2 … #define VEND1_THERMAL_STAT2_VALID … #define VEND1_GENERAL_STAT1 … #define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL … #define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL … #define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN … #define VEND1_GENERAL_STAT1_LOW_TEMP_WARN … #define VEND1_GLOBAL_GEN_STAT2 … #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG … #define VEND1_GLOBAL_RSVD_STAT1 … #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID … #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID … #define VEND1_GLOBAL_RSVD_STAT9 … #define VEND1_GLOBAL_RSVD_STAT9_MODE … #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 … /* MDIO_MMD_C22EXT */ #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES … #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES … #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER … #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES … #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES … #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER … #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS … #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS … #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR … #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES … #define VEND1_GLOBAL_INT_STD_STATUS … #define VEND1_GLOBAL_INT_VEND_STATUS … #define VEND1_GLOBAL_INT_STD_MASK … #define VEND1_GLOBAL_INT_STD_MASK_PMA1 … #define VEND1_GLOBAL_INT_STD_MASK_PMA2 … #define VEND1_GLOBAL_INT_STD_MASK_PCS1 … #define VEND1_GLOBAL_INT_STD_MASK_PCS2 … #define VEND1_GLOBAL_INT_STD_MASK_PCS3 … #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 … #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 … #define VEND1_GLOBAL_INT_STD_MASK_AN1 … #define VEND1_GLOBAL_INT_STD_MASK_AN2 … #define VEND1_GLOBAL_INT_STD_MASK_GBE … #define VEND1_GLOBAL_INT_STD_MASK_ALL … #define VEND1_GLOBAL_INT_VEND_MASK … #define VEND1_GLOBAL_INT_VEND_MASK_PMA … #define VEND1_GLOBAL_INT_VEND_MASK_PCS … #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS … #define VEND1_GLOBAL_INT_VEND_MASK_AN … #define VEND1_GLOBAL_INT_VEND_MASK_GBE … #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 … #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 … #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 … #define AQR_MAX_LEDS … struct aqr107_hw_stat { … }; #define SGMII_STAT(n, r, s) … static const struct aqr107_hw_stat aqr107_hw_stats[] = …; #define AQR107_SGMII_STAT_SZ … struct aqr107_priv { … }; #if IS_REACHABLE(CONFIG_HWMON) int aqr_hwmon_probe(struct phy_device *phydev); #else static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; } #endif int aqr_firmware_load(struct phy_device *phydev); int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index, unsigned long *delay_on, unsigned long *delay_off); int aqr_phy_led_brightness_set(struct phy_device *phydev, u8 index, enum led_brightness value); int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsigned long rules); int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index, unsigned long *rules); int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index, unsigned long rules); int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable); int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes); int aqr_wait_reset_complete(struct phy_device *phydev); #endif /* AQUANTIA_H */
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