linux/drivers/net/phy/aquantia/aquantia_firmware.c

// SPDX-License-Identifier: GPL-2.0

#include <linux/bitfield.h>
#include <linux/of.h>
#include <linux/firmware.h>
#include <linux/crc-itu-t.h>
#include <linux/nvmem-consumer.h>

#include <linux/unaligned.h>

#include "aquantia.h"

#define UP_RESET_SLEEP …

/* addresses of memory segments in the phy */
#define DRAM_BASE_ADDR …
#define IRAM_BASE_ADDR …

/* firmware image format constants */
#define VERSION_STRING_SIZE …
#define VERSION_STRING_OFFSET …
/* primary offset is written at an offset from the start of the fw blob */
#define PRIMARY_OFFSET_OFFSET …
/* primary offset needs to be then added to a base offset */
#define PRIMARY_OFFSET_SHIFT …
#define PRIMARY_OFFSET(x) …
#define HEADER_OFFSET …

struct aqr_fw_header { … } __packed;

enum aqr_fw_src { … };

static const char * const aqr_fw_src_string[] = …;

/* AQR firmware doesn't have fixed offsets for iram and dram section
 * but instead provide an header with the offset to use on reading
 * and parsing the firmware.
 *
 * AQR firmware can't be trusted and each offset is validated to be
 * not negative and be in the size of the firmware itself.
 */
static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)
{ … }

static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)
{ … }

static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)
{ … }

static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)
{ … }

/* load data into the phy's memory */
static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,
			      const u8 *data, size_t len)
{ … }

static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,
		       enum aqr_fw_src fw_src)
{ … }

static int aqr_firmware_load_nvmem(struct phy_device *phydev)
{ … }

static int aqr_firmware_load_fs(struct phy_device *phydev)
{ … }

int aqr_firmware_load(struct phy_device *phydev)
{ … }