linux/drivers/net/phy/mscc/mscc_serdes.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Driver for Microsemi VSC85xx PHYs
 *
 * Author: Bjarni Jonasson <[email protected]>
 * License: Dual MIT/GPL
 * Copyright (c) 2021 Microsemi Corporation
 */

#include <linux/phy.h>
#include "mscc_serdes.h"
#include "mscc.h"

static int pll5g_detune(struct phy_device *phydev)
{ … }

static int pll5g_tune(struct phy_device *phydev)
{ … }

static int vsc85xx_sd6g_pll_cfg_wr(struct phy_device *phydev,
				   const u32 pll_ena_offs,
				   const u32 pll_fsm_ctrl_data,
				   const u32 pll_fsm_ena)
{ … }

static int vsc85xx_sd6g_common_cfg_wr(struct phy_device *phydev,
				      const u32 sys_rst,
				      const u32 ena_lane,
				      const u32 ena_loop,
				      const u32 qrate,
				      const u32 if_mode,
				      const u32 pwd_tx)
{ … }

static int vsc85xx_sd6g_des_cfg_wr(struct phy_device *phydev,
				   const u32 des_phy_ctrl,
				   const u32 des_mbtr_ctrl,
				   const u32 des_bw_hyst,
				   const u32 des_bw_ana,
				   const u32 des_cpmd_sel)
{ … }

static int vsc85xx_sd6g_ib_cfg0_wr(struct phy_device *phydev,
				   const u32 ib_rtrm_adj,
				   const u32 ib_sig_det_clk_sel,
				   const u32 ib_reg_pat_sel_offset,
				   const u32 ib_cal_ena)
{ … }

static int vsc85xx_sd6g_ib_cfg1_wr(struct phy_device *phydev,
				   const u32 ib_tjtag,
				   const u32 ib_tsdet,
				   const u32 ib_scaly,
				   const u32 ib_frc_offset,
				   const u32 ib_filt_offset)
{ … }

static int vsc85xx_sd6g_ib_cfg2_wr(struct phy_device *phydev,
				   const u32 ib_tinfv,
				   const u32 ib_tcalv,
				   const u32 ib_ureg)
{ … }

static int vsc85xx_sd6g_ib_cfg3_wr(struct phy_device *phydev,
				   const u32 ib_ini_hp,
				   const u32 ib_ini_mid,
				   const u32 ib_ini_lp,
				   const u32 ib_ini_offset)
{ … }

static int vsc85xx_sd6g_ib_cfg4_wr(struct phy_device *phydev,
				   const u32 ib_max_hp,
				   const u32 ib_max_mid,
				   const u32 ib_max_lp,
				   const u32 ib_max_offset)
{ … }

static int vsc85xx_sd6g_misc_cfg_wr(struct phy_device *phydev,
				    const u32 lane_rst)
{ … }

static int vsc85xx_sd6g_gp_cfg_wr(struct phy_device *phydev, const u32 gp_cfg_val)
{ … }

static int vsc85xx_sd6g_dft_cfg2_wr(struct phy_device *phydev,
				    const u32 rx_ji_ampl,
				    const u32 rx_step_freq,
				    const u32 rx_ji_ena,
				    const u32 rx_waveform_sel,
				    const u32 rx_freqoff_dir,
				    const u32 rx_freqoff_ena)
{ … }

static int vsc85xx_sd6g_dft_cfg0_wr(struct phy_device *phydev,
				    const u32 prbs_sel,
				    const u32 test_mode,
				    const u32 rx_dft_ena)
{ … }

/* Access LCPLL Cfg_0 */
static int vsc85xx_pll5g_cfg0_wr(struct phy_device *phydev,
				 const u32 selbgv820)
{ … }

int vsc85xx_sd6g_config_v2(struct phy_device *phydev)
{ … }