// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Driver for Microsemi VSC85xx PHYs * * Author: Nagaraju Lakkaraju * License: Dual MIT/GPL * Copyright (c) 2016 Microsemi Corporation */ #include <linux/firmware.h> #include <linux/jiffies.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/mdio.h> #include <linux/mii.h> #include <linux/phy.h> #include <linux/of.h> #include <linux/netdevice.h> #include <dt-bindings/net/mscc-phy-vsc8531.h> #include "mscc_serdes.h" #include "mscc.h" static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = …; static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = …; #if IS_ENABLED(CONFIG_OF_MDIO) static const struct vsc8531_edge_rate_table edge_table[] = …; #endif static const int vsc85xx_internal_delay[] = …; static int vsc85xx_phy_read_page(struct phy_device *phydev) { … } static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) { … } static int vsc85xx_get_sset_count(struct phy_device *phydev) { … } static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) { … } static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) { … } static void vsc85xx_get_stats(struct phy_device *phydev, struct ethtool_stats *stats, u64 *data) { … } static int vsc85xx_led_cntl_set(struct phy_device *phydev, u8 led_num, u8 mode) { … } static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) { … } static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) { … } static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) { … } static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) { … } static int vsc85xx_wol_set(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } static void vsc85xx_wol_get(struct phy_device *phydev, struct ethtool_wolinfo *wol) { … } #if IS_ENABLED(CONFIG_OF_MDIO) static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) { … } static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led, u32 default_mode) { … } #else static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) { return 0; } static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led, u8 default_mode) { return default_mode; } #endif /* CONFIG_OF_MDIO */ static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, u32 *default_mode) { … } static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) { … } static int vsc85xx_mac_if_set(struct phy_device *phydev, phy_interface_t interface) { … } /* Set the RGMII RX and TX clock skews individually, according to the PHY * interface type, to: * * 0.2 ns (their default, and lowest, hardware value) if delays should * not be enabled * * 2.0 ns (which causes the data to be sampled at exactly half way between * clock transitions at 1000 Mbps) if delays should be enabled */ static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, u16 rgmii_rx_delay_mask, u16 rgmii_tx_delay_mask) { … } static int vsc85xx_default_config(struct phy_device *phydev) { … } static int vsc85xx_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data) { … } static int vsc85xx_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data) { … } /* mdiobus lock should be locked when using this function */ static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) { … } static int vsc8531_pre_init_seq_set(struct phy_device *phydev) { … } static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) { … } /* phydev->bus->mdio_lock should be locked when using this function */ int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) { … } /* phydev->bus->mdio_lock should be locked when using this function */ int phy_base_read(struct phy_device *phydev, u32 regnum) { … } u32 vsc85xx_csr_read(struct phy_device *phydev, enum csr_target target, u32 reg) { … } int vsc85xx_csr_write(struct phy_device *phydev, enum csr_target target, u32 reg, u32 val) { … } /* bus->mdio_lock should be locked when using this function */ static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) { … } /* bus->mdio_lock should be locked when using this function */ int vsc8584_cmd(struct phy_device *phydev, u16 val) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8584_micro_deassert_reset(struct phy_device *phydev, bool patch_en) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8584_micro_assert_reset(struct phy_device *phydev) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, u16 *crc) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8584_patch_fw(struct phy_device *phydev, const struct firmware *fw) { … } /* bus->mdio_lock should be locked when using this function */ static bool vsc8574_is_serdes_init(struct phy_device *phydev) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8574_config_pre_init(struct phy_device *phydev) { … } /* Access LCPLL Cfg_2 */ static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, bool disable_fsm) { … } /* trigger a read to the spcified MCB */ static int vsc8584_mcb_rd_trig(struct phy_device *phydev, u32 mcb_reg_addr, u8 mcb_slave_num) { … } /* trigger a write to the spcified MCB */ static int vsc8584_mcb_wr_trig(struct phy_device *phydev, u32 mcb_reg_addr, u8 mcb_slave_num) { … } /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */ static int vsc8584_pll5g_reset(struct phy_device *phydev) { … } /* bus->mdio_lock should be locked when using this function */ static int vsc8584_config_pre_init(struct phy_device *phydev) { … } static void vsc8584_get_base_addr(struct phy_device *phydev) { … } static void vsc85xx_coma_mode_release(struct phy_device *phydev) { … } static int vsc8584_config_host_serdes(struct phy_device *phydev) { … } static int vsc8574_config_host_serdes(struct phy_device *phydev) { … } static int vsc8584_config_init(struct phy_device *phydev) { … } static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) { … } static int vsc85xx_config_init(struct phy_device *phydev) { … } static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, u32 op) { … } /* Trigger a read to the specified MCB */ int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) { … } /* Trigger a write to the specified MCB */ int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) { … } static int vsc8514_config_host_serdes(struct phy_device *phydev) { … } static int vsc8514_config_pre_init(struct phy_device *phydev) { … } static int vsc8514_config_init(struct phy_device *phydev) { … } static int vsc85xx_ack_interrupt(struct phy_device *phydev) { … } static int vsc85xx_config_intr(struct phy_device *phydev) { … } static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) { … } static int vsc85xx_config_aneg(struct phy_device *phydev) { … } static int vsc85xx_read_status(struct phy_device *phydev) { … } static int vsc8514_probe(struct phy_device *phydev) { … } static int vsc8574_probe(struct phy_device *phydev) { … } static int vsc8584_probe(struct phy_device *phydev) { … } static int vsc85xx_probe(struct phy_device *phydev) { … } /* Microsemi VSC85xx PHYs */ static struct phy_driver vsc85xx_driver[] = …; module_phy_driver(vsc85xx_driver); static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = …; MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_FIRMWARE(…); MODULE_FIRMWARE(…);
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