linux/drivers/net/phy/bcm7xxx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014-2017 Broadcom
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include "bcm-phy-lib.h"
#include <linux/bitops.h>
#include <linux/brcmphy.h>
#include <linux/clk.h>
#include <linux/mdio.h>

/* Broadcom BCM7xxx internal PHY registers */

/* EPHY only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL
#define MII_BCM7XXX_100TX_FALSE_CAR
#define MII_BCM7XXX_100TX_DISC
#define MII_BCM7XXX_AUX_MODE
#define MII_BCM7XXX_64CLK_MDIO
#define MII_BCM7XXX_TEST
#define MII_BCM7XXX_SHD_MODE_2
#define MII_BCM7XXX_SHD_2_ADDR_CTRL
#define MII_BCM7XXX_SHD_2_CTRL_STAT
#define MII_BCM7XXX_SHD_2_BIAS_TRIM
#define MII_BCM7XXX_SHD_3_PCS_CTRL
#define MII_BCM7XXX_SHD_3_PCS_STATUS
#define MII_BCM7XXX_SHD_3_EEE_CAP
#define MII_BCM7XXX_SHD_3_AN_EEE_ADV
#define MII_BCM7XXX_SHD_3_EEE_LP
#define MII_BCM7XXX_SHD_3_EEE_WK_ERR
#define MII_BCM7XXX_SHD_3_PCS_CTRL_2
#define MII_BCM7XXX_PCS_CTRL_2_DEF
#define MII_BCM7XXX_SHD_3_AN_STAT
#define MII_BCM7XXX_AN_NULL_MSG_EN
#define MII_BCM7XXX_AN_EEE_EN
#define MII_BCM7XXX_SHD_3_EEE_THRESH
#define MII_BCM7XXX_EEE_THRESH_DEF
#define MII_BCM7XXX_SHD_3_TL4
#define MII_BCM7XXX_TL4_RST_MSK

struct bcm7xxx_phy_priv {};

static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{}

static int __phy_set_clr_bits(struct phy_device *dev, int location,
			      int set_mask, int clr_mask)
{}

static int phy_set_clr_bits(struct phy_device *dev, int location,
			    int set_mask, int clr_mask)
{}

static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
{}

/* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev)
{}

static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev)
{}

static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev)
{}

#define MII_BCM7XXX_REG_INVALID

static u8 bcm7xxx_28nm_ephy_regnum_to_shd(u16 regnum)
{}

static bool bcm7xxx_28nm_ephy_dev_valid(int devnum)
{}

static int bcm7xxx_28nm_ephy_read_mmd(struct phy_device *phydev,
				      int devnum, u16 regnum)
{}

static int bcm7xxx_28nm_ephy_write_mmd(struct phy_device *phydev,
				       int devnum, u16 regnum, u16 val)
{}

static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
{}

static int bcm7xxx_config_init(struct phy_device *phydev)
{}

/* Workaround for putting the PHY in IDDQ mode, required
 * for all BCM7XXX 40nm and 65nm PHYs
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{}

static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
				    struct ethtool_tunable *tuna,
				    void *data)
{}

static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
				    struct ethtool_tunable *tuna,
				    const void *data)
{}

static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
				       struct ethtool_stats *stats, u64 *data)
{}

static int bcm7xxx_28nm_probe(struct phy_device *phydev)
{}

#define BCM7XXX_28NM_GPHY(_oui, _name)

#define BCM7XXX_28NM_EPHY(_oui, _name)

#define BCM7XXX_40NM_EPHY(_oui, _name)

#define BCM7XXX_16NM_EPHY(_oui, _name)

static struct phy_driver bcm7xxx_driver[] =;

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] =;

module_phy_driver(bcm7xxx_driver);

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION();
MODULE_LICENSE();
MODULE_AUTHOR();