linux/drivers/net/phy/dp83822.c

// SPDX-License-Identifier: GPL-2.0
/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
 *
 * Copyright (C) 2017 Texas Instruments Inc.
 */

#include <linux/ethtool.h>
#include <linux/etherdevice.h>
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/bitfield.h>

#define DP83822_PHY_ID
#define DP83825S_PHY_ID
#define DP83825I_PHY_ID
#define DP83825CM_PHY_ID
#define DP83825CS_PHY_ID
#define DP83826C_PHY_ID
#define DP83826NC_PHY_ID

#define DP83822_DEVADDR

#define MII_DP83822_CTRL_2
#define MII_DP83822_PHYSTS
#define MII_DP83822_PHYSCR
#define MII_DP83822_MISR1
#define MII_DP83822_MISR2
#define MII_DP83822_FCSCR
#define MII_DP83822_RCSR
#define MII_DP83822_RESET_CTRL
#define MII_DP83822_GENCFG
#define MII_DP83822_SOR1

/* DP83826 specific registers */
#define MII_DP83826_VOD_CFG1
#define MII_DP83826_VOD_CFG2

/* GENCFG */
#define DP83822_SIG_DET_LOW

/* Control Register 2 bits */
#define DP83822_FX_ENABLE

#define DP83822_SW_RESET
#define DP83822_DIG_RESTART

/* PHY STS bits */
#define DP83822_PHYSTS_DUPLEX
#define DP83822_PHYSTS_10
#define DP83822_PHYSTS_LINK

/* PHYSCR Register Fields */
#define DP83822_PHYSCR_INT_OE
#define DP83822_PHYSCR_INTEN

/* MISR1 bits */
#define DP83822_RX_ERR_HF_INT_EN
#define DP83822_FALSE_CARRIER_HF_INT_EN
#define DP83822_ANEG_COMPLETE_INT_EN
#define DP83822_DUP_MODE_CHANGE_INT_EN
#define DP83822_SPEED_CHANGED_INT_EN
#define DP83822_LINK_STAT_INT_EN
#define DP83822_ENERGY_DET_INT_EN
#define DP83822_LINK_QUAL_INT_EN

/* MISR2 bits */
#define DP83822_JABBER_DET_INT_EN
#define DP83822_WOL_PKT_INT_EN
#define DP83822_SLEEP_MODE_INT_EN
#define DP83822_MDI_XOVER_INT_EN
#define DP83822_LB_FIFO_INT_EN
#define DP83822_PAGE_RX_INT_EN
#define DP83822_ANEG_ERR_INT_EN
#define DP83822_EEE_ERROR_CHANGE_INT_EN

/* INT_STAT1 bits */
#define DP83822_WOL_INT_EN
#define DP83822_WOL_INT_STAT

#define MII_DP83822_RXSOP1
#define MII_DP83822_RXSOP2
#define MII_DP83822_RXSOP3

/* WoL Registers */
#define MII_DP83822_WOL_CFG
#define MII_DP83822_WOL_STAT
#define MII_DP83822_WOL_DA1
#define MII_DP83822_WOL_DA2
#define MII_DP83822_WOL_DA3

/* WoL bits */
#define DP83822_WOL_MAGIC_EN
#define DP83822_WOL_SECURE_ON
#define DP83822_WOL_EN
#define DP83822_WOL_INDICATION_SEL
#define DP83822_WOL_CLR_INDICATION

/* RCSR bits */
#define DP83822_RMII_MODE_EN
#define DP83822_RMII_MODE_SEL
#define DP83822_RGMII_MODE_EN
#define DP83822_RX_CLK_SHIFT
#define DP83822_TX_CLK_SHIFT

/* SOR1 mode */
#define DP83822_STRAP_MODE1
#define DP83822_STRAP_MODE2
#define DP83822_STRAP_MODE3
#define DP83822_STRAP_MODE4

#define DP83822_COL_STRAP_MASK
#define DP83822_COL_SHIFT
#define DP83822_RX_ER_STR_MASK
#define DP83822_RX_ER_SHIFT

/* DP83826: VOD_CFG1 & VOD_CFG2 */
#define DP83826_VOD_CFG1_MINUS_MDIX_MASK
#define DP83826_VOD_CFG1_MINUS_MDI_MASK
#define DP83826_VOD_CFG2_MINUS_MDIX_MASK
#define DP83826_VOD_CFG2_PLUS_MDIX_MASK
#define DP83826_VOD_CFG2_PLUS_MDI_MASK
#define DP83826_CFG_DAC_MINUS_MDIX_5_TO_4
#define DP83826_CFG_DAC_MINUS_MDIX_3_TO_0
#define DP83826_CFG_DAC_PERCENT_PER_STEP
#define DP83826_CFG_DAC_PERCENT_DEFAULT
#define DP83826_CFG_DAC_MINUS_DEFAULT
#define DP83826_CFG_DAC_PLUS_DEFAULT

#define MII_DP83822_FIBER_ADVERTISE

struct dp83822_private {};

static int dp83822_config_wol(struct phy_device *phydev,
			      struct ethtool_wolinfo *wol)
{}

static int dp83822_set_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{}

static void dp83822_get_wol(struct phy_device *phydev,
			    struct ethtool_wolinfo *wol)
{}

static int dp83822_config_intr(struct phy_device *phydev)
{}

static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
{}

static int dp83822_read_status(struct phy_device *phydev)
{}

static int dp83822_config_init(struct phy_device *phydev)
{}

static int dp83826_config_rmii_mode(struct phy_device *phydev)
{}

static int dp83826_config_init(struct phy_device *phydev)
{}

static int dp8382x_config_init(struct phy_device *phydev)
{}

static int dp83822_phy_reset(struct phy_device *phydev)
{}

#ifdef CONFIG_OF_MDIO
static int dp83822_of_init(struct phy_device *phydev)
{}

static int dp83826_to_dac_minus_one_regval(int percent)
{}

static int dp83826_to_dac_plus_one_regval(int percent)
{}

static void dp83826_of_init(struct phy_device *phydev)
{}
#else
static int dp83822_of_init(struct phy_device *phydev)
{
	return 0;
}

static void dp83826_of_init(struct phy_device *phydev)
{
}
#endif /* CONFIG_OF_MDIO */

static int dp83822_read_straps(struct phy_device *phydev)
{}

static int dp8382x_probe(struct phy_device *phydev)
{}

static int dp83822_probe(struct phy_device *phydev)
{}

static int dp83826_probe(struct phy_device *phydev)
{}

static int dp83822_suspend(struct phy_device *phydev)
{}

static int dp83822_resume(struct phy_device *phydev)
{}

#define DP83822_PHY_DRIVER(_id, _name)

#define DP83826_PHY_DRIVER(_id, _name)

#define DP8382X_PHY_DRIVER(_id, _name)

static struct phy_driver dp83822_driver[] =;
module_phy_driver(dp83822_driver);

static struct mdio_device_id __maybe_unused dp83822_tbl[] =;
MODULE_DEVICE_TABLE(mdio, dp83822_tbl);

MODULE_DESCRIPTION();
MODULE_AUTHOR();
MODULE_LICENSE();