// SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2018 Microchip Technology #include <linux/kernel.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/mii.h> #include <linux/phy.h> #include <linux/ethtool.h> #include <linux/ethtool_netlink.h> #include <linux/bitfield.h> #define PHY_ID_LAN87XX … #define PHY_ID_LAN937X … #define PHY_ID_LAN887X … /* External Register Control Register */ #define LAN87XX_EXT_REG_CTL … #define LAN87XX_EXT_REG_CTL_RD_CTL … #define LAN87XX_EXT_REG_CTL_WR_CTL … #define LAN87XX_REG_BANK_SEL_MASK … #define LAN87XX_REG_ADDR_MASK … /* External Register Read Data Register */ #define LAN87XX_EXT_REG_RD_DATA … /* External Register Write Data Register */ #define LAN87XX_EXT_REG_WR_DATA … /* Interrupt Source Register */ #define LAN87XX_INTERRUPT_SOURCE … #define LAN87XX_INTERRUPT_SOURCE_2 … /* Interrupt Mask Register */ #define LAN87XX_INTERRUPT_MASK … #define LAN87XX_MASK_LINK_UP … #define LAN87XX_MASK_LINK_DOWN … #define LAN87XX_INTERRUPT_MASK_2 … #define LAN87XX_MASK_COMM_RDY … /* MISC Control 1 Register */ #define LAN87XX_CTRL_1 … #define LAN87XX_MASK_RGMII_TXC_DLY_EN … #define LAN87XX_MASK_RGMII_RXC_DLY_EN … /* phyaccess nested types */ #define PHYACC_ATTR_MODE_READ … #define PHYACC_ATTR_MODE_WRITE … #define PHYACC_ATTR_MODE_MODIFY … #define PHYACC_ATTR_MODE_POLL … #define PHYACC_ATTR_BANK_SMI … #define PHYACC_ATTR_BANK_MISC … #define PHYACC_ATTR_BANK_PCS … #define PHYACC_ATTR_BANK_AFE … #define PHYACC_ATTR_BANK_DSP … #define PHYACC_ATTR_BANK_MAX … /* measurement defines */ #define LAN87XX_CABLE_TEST_OK … #define LAN87XX_CABLE_TEST_OPEN … #define LAN87XX_CABLE_TEST_SAME_SHORT … /* T1 Registers */ #define T1_AFE_PORT_CFG1_REG … #define T1_POWER_DOWN_CONTROL_REG … #define T1_SLV_FD_MULT_CFG_REG … #define T1_CDR_CFG_PRE_LOCK_REG … #define T1_CDR_CFG_POST_LOCK_REG … #define T1_LCK_STG2_MUFACT_CFG_REG … #define T1_LCK_STG3_MUFACT_CFG_REG … #define T1_POST_LCK_MUFACT_CFG_REG … #define T1_TX_RX_FIFO_CFG_REG … #define T1_TX_LPF_FIR_CFG_REG … #define T1_COEF_CLK_PWR_DN_CFG … #define T1_COEF_RW_CTL_CFG … #define T1_SQI_CONFIG_REG … #define T1_SQI_CONFIG2_REG … #define T1_DCQ_SQI_REG … #define T1_DCQ_SQI_MSK … #define T1_MDIO_CONTROL2_REG … #define T1_INTERRUPT_SOURCE_REG … #define T1_INTERRUPT2_SOURCE_REG … #define T1_EQ_FD_STG1_FRZ_CFG … #define T1_EQ_FD_STG2_FRZ_CFG … #define T1_EQ_FD_STG3_FRZ_CFG … #define T1_EQ_FD_STG4_FRZ_CFG … #define T1_EQ_WT_FD_LCK_FRZ_CFG … #define T1_PST_EQ_LCK_STG1_FRZ_CFG … #define T1_MODE_STAT_REG … #define T1_LINK_UP_MSK … /* SQI defines */ #define LAN87XX_MAX_SQI … /* Chiptop registers */ #define LAN887X_PMA_EXT_ABILITY_2 … #define LAN887X_PMA_EXT_ABILITY_2_1000T1 … #define LAN887X_PMA_EXT_ABILITY_2_100T1 … /* DSP 100M registers */ #define LAN887x_CDR_CONFIG1_100 … #define LAN887x_LOCK1_EQLSR_CONFIG_100 … #define LAN887x_SLV_HD_MUFAC_CONFIG_100 … #define LAN887x_PLOCK_MUFAC_CONFIG_100 … #define LAN887x_PROT_DISABLE_100 … #define LAN887x_KF_LOOP_SAT_CONFIG_100 … /* DSP 1000M registers */ #define LAN887X_LOCK1_EQLSR_CONFIG … #define LAN887X_LOCK3_EQLSR_CONFIG … #define LAN887X_PROT_DISABLE … #define LAN887X_FFE_GAIN6 … #define LAN887X_FFE_GAIN7 … #define LAN887X_FFE_GAIN8 … #define LAN887X_FFE_GAIN9 … #define LAN887X_ECHO_DELAY_CONFIG … #define LAN887X_FFE_MAX_CONFIG … /* PCS 1000M registers */ #define LAN887X_SCR_CONFIG_3 … #define LAN887X_INFO_FLD_CONFIG_5 … /* T1 afe registers */ #define LAN887X_ZQCAL_CONTROL_1 … #define LAN887X_AFE_PORT_TESTBUS_CTRL2 … #define LAN887X_AFE_PORT_TESTBUS_CTRL4 … #define LAN887X_AFE_PORT_TESTBUS_CTRL6 … #define LAN887X_TX_AMPLT_1000T1_REG … #define LAN887X_INIT_COEFF_DFE1_100 … /* PMA registers */ #define LAN887X_DSP_PMA_CONTROL … #define LAN887X_DSP_PMA_CONTROL_LNK_SYNC … /* PCS 100M registers */ #define LAN887X_IDLE_ERR_TIMER_WIN … #define LAN887X_IDLE_ERR_CNT_THRESH … /* Misc registers */ #define LAN887X_REG_REG26 … #define LAN887X_REG_REG26_HW_INIT_SEQ_EN … /* Mis registers */ #define LAN887X_MIS_CFG_REG0 … #define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS … #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL … #define LAN887X_MAC_MODE_RGMII … #define LAN887X_MAC_MODE_SGMII … #define LAN887X_MIS_DLL_CFG_REG0 … #define LAN887X_MIS_DLL_CFG_REG1 … #define LAN887X_MIS_DLL_DELAY_EN … #define LAN887X_MIS_DLL_EN … #define LAN887X_MIS_DLL_CONF … #define LAN887X_MIS_CFG_REG2 … #define LAN887X_MIS_CFG_REG2_FE_LPBK_EN … #define LAN887X_MIS_PKT_STAT_REG0 … #define LAN887X_MIS_PKT_STAT_REG1 … #define LAN887X_MIS_PKT_STAT_REG3 … #define LAN887X_MIS_PKT_STAT_REG4 … #define LAN887X_MIS_PKT_STAT_REG5 … #define LAN887X_MIS_PKT_STAT_REG6 … /* Chiptop common registers */ #define LAN887X_COMMON_LED3_LED2 … #define LAN887X_COMMON_LED2_MODE_SEL_MASK … #define LAN887X_LED_LINK_ACT_ANY_SPEED … /* MX chip top registers */ #define LAN887X_CHIP_HARD_RST … #define LAN887X_CHIP_HARD_RST_RESET … #define LAN887X_CHIP_SOFT_RST … #define LAN887X_CHIP_SOFT_RST_RESET … #define LAN887X_SGMII_CTL … #define LAN887X_SGMII_CTL_SGMII_MUX_EN … #define LAN887X_SGMII_PCS_CFG … #define LAN887X_SGMII_PCS_CFG_PCS_ENA … #define LAN887X_EFUSE_READ_DAT9 … #define LAN887X_EFUSE_READ_DAT9_SGMII_DIS … #define LAN887X_EFUSE_READ_DAT9_MAC_MODE … #define LAN887X_CALIB_CONFIG_100 … #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL … #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE … #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE … #define LAN887X_CALIB_CONFIG_100_VAL … #define LAN887X_MAX_PGA_GAIN_100 … #define LAN887X_MIN_PGA_GAIN_100 … #define LAN887X_START_CBL_DIAG_100 … #define LAN887X_CBL_DIAG_DONE … #define LAN887X_CBL_DIAG_START … #define LAN887X_CBL_DIAG_STOP … #define LAN887X_CBL_DIAG_TDR_THRESH_100 … #define LAN887X_CBL_DIAG_AGC_THRESH_100 … #define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 … #define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 … #define LAN887X_CBL_DIAG_CYC_CONFIG_100 … #define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 … #define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 … #define LAN887X_CBL_DIAG_AGC_GAIN_100 … #define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 … #define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 … #define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 … #define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 … #define MICROCHIP_CABLE_NOISE_MARGIN … #define MICROCHIP_CABLE_TIME_MARGIN … #define MICROCHIP_CABLE_MIN_TIME_DIFF … #define MICROCHIP_CABLE_MAX_TIME_DIFF … #define DRIVER_AUTHOR … #define DRIVER_DESC … /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok) * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault */ enum cable_diag_mode { … }; /* CD_TEST_INIT: Cable test is initated * CD_TEST_DONE: Cable test is done */ enum cable_diag_state { … }; struct access_ereg_val { … }; struct lan887x_hw_stat { … }; static const struct lan887x_hw_stat lan887x_hw_stats[] = …; struct lan887x_regwr_map { … }; struct lan887x_priv { … }; static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank) { … } static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank, u8 offset, u16 val) { … } static int access_ereg_modify_changed(struct phy_device *phydev, u8 bank, u8 offset, u16 val, u16 mask) { … } static int access_smi_poll_timeout(struct phy_device *phydev, u8 offset, u16 mask, u16 clr) { … } static int lan87xx_config_rgmii_delay(struct phy_device *phydev) { … } static int lan87xx_phy_init_cmd(struct phy_device *phydev, const struct access_ereg_val *cmd_seq, int cnt) { … } static int lan87xx_phy_init(struct phy_device *phydev) { … } static int lan87xx_phy_config_intr(struct phy_device *phydev) { … } static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev) { … } static int lan87xx_config_init(struct phy_device *phydev) { … } static int microchip_cable_test_start_common(struct phy_device *phydev) { … } static int lan87xx_cable_test_start(struct phy_device *phydev) { … } static int lan87xx_cable_test_report_trans(u32 result) { … } static int lan87xx_cable_test_report(struct phy_device *phydev) { … } static int lan87xx_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } static int lan87xx_read_status(struct phy_device *phydev) { … } static int lan87xx_config_aneg(struct phy_device *phydev) { … } static int lan87xx_get_sqi(struct phy_device *phydev) { … } static int lan87xx_get_sqi_max(struct phy_device *phydev) { … } static int lan887x_rgmii_init(struct phy_device *phydev) { … } static int lan887x_sgmii_init(struct phy_device *phydev) { … } static int lan887x_config_rgmii_en(struct phy_device *phydev) { … } static int lan887x_config_phy_interface(struct phy_device *phydev) { … } static int lan887x_get_features(struct phy_device *phydev) { … } static int lan887x_phy_init(struct phy_device *phydev) { … } static int lan887x_phy_config(struct phy_device *phydev, const struct lan887x_regwr_map *reg_map, int cnt) { … } static int lan887x_phy_setup(struct phy_device *phydev) { … } static int lan887x_100M_setup(struct phy_device *phydev) { … } static int lan887x_1000M_setup(struct phy_device *phydev) { … } static int lan887x_link_setup(struct phy_device *phydev) { … } /* LAN887x Errata: speed configuration changes require soft reset * and chip soft reset */ static int lan887x_phy_reset(struct phy_device *phydev) { … } static int lan887x_phy_reconfig(struct phy_device *phydev) { … } static int lan887x_config_aneg(struct phy_device *phydev) { … } static int lan887x_probe(struct phy_device *phydev) { … } static u64 lan887x_get_stat(struct phy_device *phydev, int i) { … } static void lan887x_get_stats(struct phy_device *phydev, struct ethtool_stats *stats, u64 *data) { … } static int lan887x_get_sset_count(struct phy_device *phydev) { … } static void lan887x_get_strings(struct phy_device *phydev, u8 *data) { … } static int lan887x_cd_reset(struct phy_device *phydev, enum cable_diag_state cd_done) { … } static int lan887x_cable_test_prep(struct phy_device *phydev, enum cable_diag_mode mode) { … } static int lan887x_cable_test_chk(struct phy_device *phydev, enum cable_diag_mode mode) { … } static int lan887x_cable_test_start(struct phy_device *phydev) { … } static int lan887x_cable_test_report(struct phy_device *phydev) { … } static int lan887x_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } static struct phy_driver microchip_t1_phy_driver[] = …; module_phy_driver(microchip_t1_phy_driver); static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = …; MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl); MODULE_AUTHOR(…); MODULE_DESCRIPTION(…); MODULE_LICENSE(…) …;
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