// SPDX-License-Identifier: GPL-2.0 /* NXP C45 PHY driver * Copyright 2021-2023 NXP * Author: Radu Pirea <[email protected]> */ #include <linux/delay.h> #include <linux/ethtool.h> #include <linux/ethtool_netlink.h> #include <linux/kernel.h> #include <linux/mii.h> #include <linux/module.h> #include <linux/phy.h> #include <linux/processor.h> #include <linux/property.h> #include <linux/ptp_classify.h> #include <linux/net_tstamp.h> #include "nxp-c45-tja11xx.h" #define PHY_ID_TJA_1103 … #define PHY_ID_TJA_1120 … #define VEND1_DEVICE_CONTROL … #define DEVICE_CONTROL_RESET … #define DEVICE_CONTROL_CONFIG_GLOBAL_EN … #define DEVICE_CONTROL_CONFIG_ALL_EN … #define VEND1_DEVICE_CONFIG … #define TJA1120_VEND1_EXT_TS_MODE … #define TJA1120_GLOBAL_INFRA_IRQ_ACK … #define TJA1120_GLOBAL_INFRA_IRQ_EN … #define TJA1120_GLOBAL_INFRA_IRQ_STATUS … #define TJA1120_DEV_BOOT_DONE … #define TJA1120_VEND1_PTP_TRIG_DATA_S … #define TJA1120_EGRESS_TS_DATA_S … #define TJA1120_EGRESS_TS_END … #define TJA1120_TS_VALID … #define TJA1120_MORE_TS … #define VEND1_PHY_IRQ_ACK … #define VEND1_PHY_IRQ_EN … #define VEND1_PHY_IRQ_STATUS … #define PHY_IRQ_LINK_EVENT … #define VEND1_ALWAYS_ACCESSIBLE … #define FUSA_PASS … #define VEND1_PHY_CONTROL … #define PHY_CONFIG_EN … #define PHY_START_OP … #define VEND1_PHY_CONFIG … #define PHY_CONFIG_AUTO … #define TJA1120_EPHY_RESETS … #define EPHY_PCS_RESET … #define VEND1_SIGNAL_QUALITY … #define SQI_VALID … #define SQI_MASK … #define MAX_SQI … #define CABLE_TEST_ENABLE … #define CABLE_TEST_START … #define CABLE_TEST_OK … #define CABLE_TEST_SHORTED … #define CABLE_TEST_OPEN … #define CABLE_TEST_UNKNOWN … #define VEND1_PORT_CONTROL … #define PORT_CONTROL_EN … #define VEND1_PORT_ABILITIES … #define MACSEC_ABILITY … #define PTP_ABILITY … #define VEND1_PORT_FUNC_IRQ_EN … #define MACSEC_IRQS … #define PTP_IRQS … #define VEND1_PTP_IRQ_ACK … #define EGR_TS_IRQ … #define VEND1_PORT_INFRA_CONTROL … #define PORT_INFRA_CONTROL_EN … #define VEND1_RXID … #define VEND1_TXID … #define ID_ENABLE … #define VEND1_ABILITIES … #define RGMII_ID_ABILITY … #define RGMII_ABILITY … #define RMII_ABILITY … #define REVMII_ABILITY … #define MII_ABILITY … #define SGMII_ABILITY … #define VEND1_MII_BASIC_CONFIG … #define MII_BASIC_CONFIG_REV … #define MII_BASIC_CONFIG_SGMII … #define MII_BASIC_CONFIG_RGMII … #define MII_BASIC_CONFIG_RMII … #define MII_BASIC_CONFIG_MII … #define VEND1_SYMBOL_ERROR_CNT_XTD … #define EXTENDED_CNT_EN … #define VEND1_MONITOR_STATUS … #define MONITOR_RESET … #define VEND1_MONITOR_CONFIG … #define LOST_FRAMES_CNT_EN … #define ALL_FRAMES_CNT_EN … #define VEND1_SYMBOL_ERROR_COUNTER … #define VEND1_LINK_DROP_COUNTER … #define VEND1_LINK_LOSSES_AND_FAILURES … #define VEND1_RX_PREAMBLE_COUNT … #define VEND1_TX_PREAMBLE_COUNT … #define VEND1_RX_IPG_LENGTH … #define VEND1_TX_IPG_LENGTH … #define COUNTER_EN … #define VEND1_PTP_CONFIG … #define EXT_TRG_EDGE … #define TJA1120_SYNC_TRIG_FILTER … #define PTP_TRIG_RISE_TS … #define PTP_TRIG_FALLING_TS … #define CLK_RATE_ADJ_LD … #define CLK_RATE_ADJ_DIR … #define VEND1_RX_TS_INSRT_CTRL … #define TJA1103_RX_TS_INSRT_MODE2 … #define TJA1120_RX_TS_INSRT_CTRL … #define TJA1120_RX_TS_INSRT_EN … #define TJA1120_TS_INSRT_MODE … #define VEND1_EGR_RING_DATA_0 … #define VEND1_EGR_RING_CTRL … #define RING_DATA_0_TS_VALID … #define RING_DONE … #define TS_SEC_MASK … #define PTP_ENABLE … #define PHY_TEST_ENABLE … #define VEND1_PORT_PTP_CONTROL … #define PORT_PTP_CONTROL_BYPASS … #define PTP_CLK_PERIOD_100BT1 … #define PTP_CLK_PERIOD_1000BT1 … #define EVENT_MSG_FILT_ALL … #define EVENT_MSG_FILT_NONE … #define VEND1_GPIO_FUNC_CONFIG_BASE … #define GPIO_FUNC_EN … #define GPIO_FUNC_PTP … #define GPIO_SIGNAL_PTP_TRIGGER … #define GPIO_SIGNAL_PPS_OUT … #define GPIO_DISABLE … #define GPIO_PPS_OUT_CFG … #define GPIO_EXTTS_OUT_CFG … #define RGMII_PERIOD_PS … #define PS_PER_DEGREE … #define MIN_ID_PS … #define MAX_ID_PS … #define DEFAULT_ID_PS … #define PPM_TO_SUBNS_INC(ppb, ptp_clk_period) … #define NXP_C45_SKB_CB(skb) … struct nxp_c45_phy; struct nxp_c45_skb_cb { … }; #define NXP_C45_REG_FIELD(_reg, _devad, _offset, _size) … struct nxp_c45_reg_field { … }; struct nxp_c45_hwts { … }; struct nxp_c45_regmap { … }; struct nxp_c45_phy_stats { … }; struct nxp_c45_phy_data { … }; static const struct nxp_c45_phy_data *nxp_c45_get_data(struct phy_device *phydev) { … } static const struct nxp_c45_regmap *nxp_c45_get_regmap(struct phy_device *phydev) { … } static int nxp_c45_read_reg_field(struct phy_device *phydev, const struct nxp_c45_reg_field *reg_field) { … } static int nxp_c45_write_reg_field(struct phy_device *phydev, const struct nxp_c45_reg_field *reg_field, u16 val) { … } static int nxp_c45_set_reg_field(struct phy_device *phydev, const struct nxp_c45_reg_field *reg_field) { … } static int nxp_c45_clear_reg_field(struct phy_device *phydev, const struct nxp_c45_reg_field *reg_field) { … } static bool nxp_c45_poll_txts(struct phy_device *phydev) { … } static int _nxp_c45_ptp_gettimex64(struct ptp_clock_info *ptp, struct timespec64 *ts, struct ptp_system_timestamp *sts) { … } static int nxp_c45_ptp_gettimex64(struct ptp_clock_info *ptp, struct timespec64 *ts, struct ptp_system_timestamp *sts) { … } static int _nxp_c45_ptp_settime64(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int nxp_c45_ptp_settime64(struct ptp_clock_info *ptp, const struct timespec64 *ts) { … } static int nxp_c45_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { … } static int nxp_c45_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) { … } static void nxp_c45_reconstruct_ts(struct timespec64 *ts, struct nxp_c45_hwts *hwts) { … } static bool nxp_c45_match_ts(struct ptp_header *header, struct nxp_c45_hwts *hwts, unsigned int type) { … } static bool nxp_c45_get_extts(struct nxp_c45_phy *priv, struct timespec64 *extts) { … } static bool tja1120_extts_is_valid(struct phy_device *phydev) { … } static bool tja1120_get_extts(struct nxp_c45_phy *priv, struct timespec64 *extts) { … } static void nxp_c45_read_egress_ts(struct nxp_c45_phy *priv, struct nxp_c45_hwts *hwts) { … } static bool nxp_c45_get_hwtxts(struct nxp_c45_phy *priv, struct nxp_c45_hwts *hwts) { … } static bool tja1120_egress_ts_is_valid(struct phy_device *phydev) { … } static bool tja1120_get_hwtxts(struct nxp_c45_phy *priv, struct nxp_c45_hwts *hwts) { … } static void nxp_c45_process_txts(struct nxp_c45_phy *priv, struct nxp_c45_hwts *txts) { … } static long nxp_c45_do_aux_work(struct ptp_clock_info *ptp) { … } static void nxp_c45_gpio_config(struct nxp_c45_phy *priv, int pin, u16 pin_cfg) { … } static int nxp_c45_perout_enable(struct nxp_c45_phy *priv, struct ptp_perout_request *perout, int on) { … } static void nxp_c45_set_rising_or_falling(struct phy_device *phydev, struct ptp_extts_request *extts) { … } static void nxp_c45_set_rising_and_falling(struct phy_device *phydev, struct ptp_extts_request *extts) { … } static int nxp_c45_extts_enable(struct nxp_c45_phy *priv, struct ptp_extts_request *extts, int on) { … } static int nxp_c45_ptp_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *req, int on) { … } static struct ptp_pin_desc nxp_c45_ptp_pins[] = …; static int nxp_c45_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin, enum ptp_pin_function func, unsigned int chan) { … } static int nxp_c45_init_ptp_clock(struct nxp_c45_phy *priv) { … } static void nxp_c45_txtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type) { … } static bool nxp_c45_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type) { … } static int nxp_c45_hwtstamp(struct mii_timestamper *mii_ts, struct kernel_hwtstamp_config *cfg, struct netlink_ext_ack *extack) { … } static int nxp_c45_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *ts_info) { … } static const struct nxp_c45_phy_stats common_hw_stats[] = …; static const struct nxp_c45_phy_stats tja1103_hw_stats[] = …; static const struct nxp_c45_phy_stats tja1120_hw_stats[] = …; static int nxp_c45_get_sset_count(struct phy_device *phydev) { … } static void nxp_c45_get_strings(struct phy_device *phydev, u8 *data) { … } static void nxp_c45_get_stats(struct phy_device *phydev, struct ethtool_stats *stats, u64 *data) { … } static int nxp_c45_config_enable(struct phy_device *phydev) { … } static int nxp_c45_start_op(struct phy_device *phydev) { … } static int nxp_c45_config_intr(struct phy_device *phydev) { … } static int tja1103_config_intr(struct phy_device *phydev) { … } static int tja1120_config_intr(struct phy_device *phydev) { … } static irqreturn_t nxp_c45_handle_interrupt(struct phy_device *phydev) { … } static int nxp_c45_soft_reset(struct phy_device *phydev) { … } static int nxp_c45_cable_test_start(struct phy_device *phydev) { … } static int nxp_c45_cable_test_get_status(struct phy_device *phydev, bool *finished) { … } static int nxp_c45_get_sqi(struct phy_device *phydev) { … } static void tja1120_link_change_notify(struct phy_device *phydev) { … } static int nxp_c45_get_sqi_max(struct phy_device *phydev) { … } static int nxp_c45_check_delay(struct phy_device *phydev, u32 delay) { … } static void nxp_c45_counters_enable(struct phy_device *phydev) { … } static void nxp_c45_ptp_init(struct phy_device *phydev) { … } static u64 nxp_c45_get_phase_shift(u64 phase_offset_raw) { … } static void nxp_c45_disable_delays(struct phy_device *phydev) { … } static void nxp_c45_set_delays(struct phy_device *phydev) { … } static int nxp_c45_get_delays(struct phy_device *phydev) { … } static int nxp_c45_set_phy_mode(struct phy_device *phydev) { … } static int nxp_c45_config_init(struct phy_device *phydev) { … } static int nxp_c45_get_features(struct phy_device *phydev) { … } static int nxp_c45_probe(struct phy_device *phydev) { … } static void nxp_c45_remove(struct phy_device *phydev) { … } static void tja1103_counters_enable(struct phy_device *phydev) { … } static void tja1103_ptp_init(struct phy_device *phydev) { … } static void tja1103_ptp_enable(struct phy_device *phydev, bool enable) { … } static void tja1103_nmi_handler(struct phy_device *phydev, irqreturn_t *irq_status) { … } static const struct nxp_c45_regmap tja1103_regmap = …; static const struct nxp_c45_phy_data tja1103_phy_data = …; static void tja1120_counters_enable(struct phy_device *phydev) { … } static void tja1120_ptp_init(struct phy_device *phydev) { … } static void tja1120_ptp_enable(struct phy_device *phydev, bool enable) { … } static void tja1120_nmi_handler(struct phy_device *phydev, irqreturn_t *irq_status) { … } static const struct nxp_c45_regmap tja1120_regmap = …; static const struct nxp_c45_phy_data tja1120_phy_data = …; static struct phy_driver nxp_c45_driver[] = …; module_phy_driver(nxp_c45_driver); static struct mdio_device_id __maybe_unused nxp_c45_tbl[] = …; MODULE_DEVICE_TABLE(mdio, nxp_c45_tbl); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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