// SPDX-License-Identifier: GPL-2.0 /* NXP C45 PTP PHY driver interface * Copyright 2023 NXP * Author: Radu Pirea <[email protected]> */ #include <linux/delay.h> #include <linux/ethtool_netlink.h> #include <linux/kernel.h> #include <linux/mii.h> #include <linux/module.h> #include <linux/phy.h> #include <linux/processor.h> #include <net/dst_metadata.h> #include <net/macsec.h> #include "nxp-c45-tja11xx.h" #define MACSEC_REG_SIZE … #define TX_SC_MAX … #define TX_SC_BIT(secy_id) … #define VEND1_MACSEC_BASE … #define MACSEC_CFG … #define MACSEC_CFG_BYPASS … #define MACSEC_CFG_S0I … #define MACSEC_TPNET … #define PN_WRAP_THRESHOLD … #define MACSEC_RXSCA … #define MACSEC_RXSCKA … #define MACSEC_TXSCA … #define MACSEC_TXSCKA … #define MACSEC_RXSC_SCI_1H … #define MACSEC_RXSC_CFG … #define MACSEC_RXSC_CFG_XPN … #define MACSEC_RXSC_CFG_AES_256 … #define MACSEC_RXSC_CFG_SCI_EN … #define MACSEC_RXSC_CFG_RP … #define MACSEC_RXSC_CFG_VF_MASK … #define MACSEC_RXSC_CFG_VF_OFF … #define MACSEC_RPW … #define MACSEC_RXSA_A_CS … #define MACSEC_RXSA_A_NPN … #define MACSEC_RXSA_A_XNPN … #define MACSEC_RXSA_A_LNPN … #define MACSEC_RXSA_A_LXNPN … #define MACSEC_RXSA_B_CS … #define MACSEC_RXSA_B_NPN … #define MACSEC_RXSA_B_XNPN … #define MACSEC_RXSA_B_LNPN … #define MACSEC_RXSA_B_LXNPN … #define MACSEC_RXSA_CS_AN_OFF … #define MACSEC_RXSA_CS_EN … #define MACSEC_TXSC_SCI_1H … #define MACSEC_TXSC_CFG … #define MACSEC_TXSC_CFG_XPN … #define MACSEC_TXSC_CFG_AES_256 … #define MACSEC_TXSC_CFG_AN_MASK … #define MACSEC_TXSC_CFG_AN_OFF … #define MACSEC_TXSC_CFG_ASA … #define MACSEC_TXSC_CFG_SCE … #define MACSEC_TXSC_CFG_ENCRYPT … #define MACSEC_TXSC_CFG_PROTECT … #define MACSEC_TXSC_CFG_SEND_SCI … #define MACSEC_TXSC_CFG_END_STATION … #define MACSEC_TXSC_CFG_SCB … #define MACSEC_TXSA_A_CS … #define MACSEC_TXSA_A_NPN … #define MACSEC_TXSA_A_XNPN … #define MACSEC_TXSA_B_CS … #define MACSEC_TXSA_B_NPN … #define MACSEC_TXSA_B_XNPN … #define MACSEC_SA_CS_A … #define MACSEC_EVR … #define MACSEC_EVER … #define MACSEC_RXSA_A_KA … #define MACSEC_RXSA_A_SSCI … #define MACSEC_RXSA_A_SALT … #define MACSEC_RXSA_B_KA … #define MACSEC_RXSA_B_SSCI … #define MACSEC_RXSA_B_SALT … #define MACSEC_TXSA_A_KA … #define MACSEC_TXSA_A_SSCI … #define MACSEC_TXSA_A_SALT … #define MACSEC_TXSA_B_KA … #define MACSEC_TXSA_B_SSCI … #define MACSEC_TXSA_B_SALT … #define MACSEC_UPFR0D2 … #define MACSEC_UPFR0M1 … #define MACSEC_OVP … #define MACSEC_UPFR0M2 … #define ETYPE_MASK … #define MACSEC_UPFR0R … #define MACSEC_UPFR_EN … #define ADPTR_CNTRL … #define ADPTR_CNTRL_CONFIG_EN … #define ADPTR_CNTRL_ADPTR_EN … #define ADPTR_TX_TAG_CNTRL … #define ADPTR_TX_TAG_CNTRL_ENA … #define TX_SC_FLT_BASE … #define TX_SC_FLT_SIZE … #define TX_FLT_BASE(flt_id) … #define TX_SC_FLT_OFF_MAC_DA_SA … #define TX_SC_FLT_OFF_MAC_SA … #define TX_SC_FLT_OFF_MAC_CFG … #define TX_SC_FLT_BY_SA … #define TX_SC_FLT_EN … #define TX_SC_FLT_MAC_DA_SA(base) … #define TX_SC_FLT_MAC_SA(base) … #define TX_SC_FLT_MAC_CFG(base) … #define ADAPTER_EN … #define MACSEC_EN … #define MACSEC_INOV1HS … #define MACSEC_INOV2HS … #define MACSEC_INOD1HS … #define MACSEC_INOD2HS … #define MACSEC_RXSCIPUS … #define MACSEC_RXSCIPDS … #define MACSEC_RXSCIPLS … #define MACSEC_RXAN0INUSS … #define MACSEC_RXAN0IPUSS … #define MACSEC_RXSA_A_IPOS … #define MACSEC_RXSA_A_IPIS … #define MACSEC_RXSA_A_IPNVS … #define MACSEC_RXSA_B_IPOS … #define MACSEC_RXSA_B_IPIS … #define MACSEC_RXSA_B_IPNVS … #define MACSEC_OPUS … #define MACSEC_OPTLS … #define MACSEC_OOP1HS … #define MACSEC_OOP2HS … #define MACSEC_OOE1HS … #define MACSEC_OOE2HS … #define MACSEC_TXSA_A_OPPS … #define MACSEC_TXSA_A_OPES … #define MACSEC_TXSA_B_OPPS … #define MACSEC_TXSA_B_OPES … #define MACSEC_INPWTS … #define MACSEC_INPBTS … #define MACSEC_IPSNFS … #define TJA11XX_TLV_TX_NEEDED_HEADROOM … #define TJA11XX_TLV_NEEDED_TAILROOM … #define ETH_P_TJA11XX_TLV … enum nxp_c45_sa_type { … }; struct nxp_c45_sa { … }; struct nxp_c45_secy { … }; struct nxp_c45_macsec { … }; struct nxp_c45_sa_regs { … }; static const struct nxp_c45_sa_regs rx_sa_a_regs = …; static const struct nxp_c45_sa_regs rx_sa_b_regs = …; static const struct nxp_c45_sa_regs tx_sa_a_regs = …; static const struct nxp_c45_sa_regs tx_sa_b_regs = …; static const struct nxp_c45_sa_regs *nxp_c45_sa_regs_get(enum nxp_c45_sa_type sa_type, bool key_a) { … } static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value) { … } static int nxp_c45_macsec_read(struct phy_device *phydev, u16 addr, u32 *value) { … } static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr, u64 *value) { … } static void nxp_c45_macsec_read64(struct phy_device *phydev, u16 addr, u64 *value) { … } static void nxp_c45_secy_irq_en(struct phy_device *phydev, struct nxp_c45_secy *phy_secy, bool en) { … } static struct nxp_c45_secy *nxp_c45_find_secy(struct list_head *secy_list, sci_t sci) { … } static struct nxp_c45_secy *nxp_c45_find_secy_by_id(struct list_head *secy_list, int id) { … } static void nxp_c45_secy_free(struct nxp_c45_secy *phy_secy) { … } static struct nxp_c45_sa *nxp_c45_find_sa(struct list_head *sa_list, enum nxp_c45_sa_type sa_type, u8 an) { … } static struct nxp_c45_sa *nxp_c45_sa_alloc(struct list_head *sa_list, void *sa, enum nxp_c45_sa_type sa_type, u8 an) { … } static void nxp_c45_sa_free(struct nxp_c45_sa *sa) { … } static void nxp_c45_sa_list_free(struct list_head *sa_list) { … } static void nxp_c45_sa_set_pn(struct phy_device *phydev, struct nxp_c45_sa *sa, u64 pn, u32 replay_window) { … } static void nxp_c45_sa_set_key(struct macsec_context *ctx, const struct nxp_c45_sa_regs *sa_regs, u8 *salt, ssci_t ssci) { … } static void nxp_c45_rx_sa_clear_stats(struct phy_device *phydev, struct nxp_c45_sa *sa) { … } static void nxp_c45_rx_sa_read_stats(struct phy_device *phydev, struct nxp_c45_sa *sa, struct macsec_rx_sa_stats *stats) { … } static void nxp_c45_tx_sa_clear_stats(struct phy_device *phydev, struct nxp_c45_sa *sa) { … } static void nxp_c45_tx_sa_read_stats(struct phy_device *phydev, struct nxp_c45_sa *sa, struct macsec_tx_sa_stats *stats) { … } static void nxp_c45_rx_sa_update(struct phy_device *phydev, struct nxp_c45_sa *sa, bool en) { … } static void nxp_c45_tx_sa_update(struct phy_device *phydev, struct nxp_c45_sa *sa, bool en) { … } static void nxp_c45_set_sci(struct phy_device *phydev, u16 sci_base_addr, sci_t sci) { … } static bool nxp_c45_port_is_1(sci_t sci) { … } static void nxp_c45_select_secy(struct phy_device *phydev, u8 id) { … } static bool nxp_c45_secy_valid(struct nxp_c45_secy *phy_secy, bool can_rx_sc0_impl) { … } static bool nxp_c45_rx_sc0_impl(struct nxp_c45_secy *phy_secy) { … } static bool nxp_c45_mac_addr_free(struct macsec_context *ctx) { … } static void nxp_c45_tx_sc_en_flt(struct phy_device *phydev, int secy_id, bool en) { … } static void nxp_c45_tx_sc_set_flt(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_tx_sc_update(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_tx_sc_clear_stats(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_set_rx_sc0_impl(struct phy_device *phydev, bool enable) { … } static bool nxp_c45_is_rx_sc0_impl(struct list_head *secy_list) { … } static void nxp_c45_rx_sc_en(struct phy_device *phydev, struct macsec_rx_sc *rx_sc, bool en) { … } static void nxp_c45_rx_sc_update(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_rx_sc_clear_stats(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_rx_sc_del(struct phy_device *phydev, struct nxp_c45_secy *phy_secy) { … } static void nxp_c45_clear_global_stats(struct phy_device *phydev) { … } static void nxp_c45_macsec_en(struct phy_device *phydev, bool en) { … } static int nxp_c45_mdo_dev_open(struct macsec_context *ctx) { … } static int nxp_c45_mdo_dev_stop(struct macsec_context *ctx) { … } static int nxp_c45_mdo_add_secy(struct macsec_context *ctx) { … } static void nxp_c45_tx_sa_next(struct nxp_c45_secy *phy_secy, struct nxp_c45_sa *next_sa, u8 encoding_sa) { … } static int nxp_c45_mdo_upd_secy(struct macsec_context *ctx) { … } static int nxp_c45_mdo_del_secy(struct macsec_context *ctx) { … } static int nxp_c45_mdo_add_rxsc(struct macsec_context *ctx) { … } static int nxp_c45_mdo_upd_rxsc(struct macsec_context *ctx) { … } static int nxp_c45_mdo_del_rxsc(struct macsec_context *ctx) { … } static int nxp_c45_mdo_add_rxsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_upd_rxsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_del_rxsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_add_txsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_upd_txsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_del_txsa(struct macsec_context *ctx) { … } static int nxp_c45_mdo_get_dev_stats(struct macsec_context *ctx) { … } static int nxp_c45_mdo_get_tx_sc_stats(struct macsec_context *ctx) { … } static int nxp_c45_mdo_get_tx_sa_stats(struct macsec_context *ctx) { … } static int nxp_c45_mdo_get_rx_sc_stats(struct macsec_context *ctx) { … } static int nxp_c45_mdo_get_rx_sa_stats(struct macsec_context *ctx) { … } struct tja11xx_tlv_header { … }; static int nxp_c45_mdo_insert_tx_tag(struct phy_device *phydev, struct sk_buff *skb) { … } static const struct macsec_ops nxp_c45_macsec_ops = …; int nxp_c45_macsec_config_init(struct phy_device *phydev) { … } int nxp_c45_macsec_probe(struct phy_device *phydev) { … } void nxp_c45_macsec_remove(struct phy_device *phydev) { … } void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev, irqreturn_t *ret) { … }
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