linux/drivers/net/mdio/mdio-cavium.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2009-2016 Cavium, Inc.
 */

enum cavium_mdiobus_mode { … };

#define SMI_CMD …
#define SMI_WR_DAT …
#define SMI_RD_DAT …
#define SMI_CLK …
#define SMI_EN …

#ifdef __BIG_ENDIAN_BITFIELD
#define OCT_MDIO_BITFIELD_FIELD …

#else
#define OCT_MDIO_BITFIELD_FIELD(field, more) …

#endif

cvmx_smix_clk;

cvmx_smix_cmd;

cvmx_smix_en;

cvmx_smix_rd_dat;

cvmx_smix_wr_dat;

struct cavium_mdiobus { … };

#ifdef CONFIG_CAVIUM_OCTEON_SOC

#include <asm/octeon/octeon.h>

static inline void oct_mdio_writeq(u64 val, void __iomem *addr)
{
	cvmx_write_csr((u64 __force)addr, val);
}

static inline u64 oct_mdio_readq(void __iomem *addr)
{
	return cvmx_read_csr((u64 __force)addr);
}
#else
#include <linux/io-64-nonatomic-lo-hi.h>

#define oct_mdio_writeq(val, addr) …
#define oct_mdio_readq(addr) …
#endif

int cavium_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int regnum);
int cavium_mdiobus_write_c22(struct mii_bus *bus, int phy_id, int regnum,
			     u16 val);
int cavium_mdiobus_read_c45(struct mii_bus *bus, int phy_id, int devad,
			    int regnum);
int cavium_mdiobus_write_c45(struct mii_bus *bus, int phy_id, int devad,
			     int regnum, u16 val);