// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2007 Wolfgang Grandegger <[email protected]> * Copyright (C) 2008 Markus Plessing <[email protected]> * Copyright (C) 2008 Sebastian Haas <[email protected]> * Copyright (C) 2023 EMS Dr. Thomas Wuensche */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/interrupt.h> #include <linux/netdevice.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/pci.h> #include <linux/can/dev.h> #include <linux/io.h> #include "sja1000.h" #define DRV_NAME … MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; #define EMS_PCI_V1_MAX_CHAN … #define EMS_PCI_V2_MAX_CHAN … #define EMS_PCI_V3_MAX_CHAN … #define EMS_PCI_MAX_CHAN … struct ems_pci_card { … }; #define EMS_PCI_CAN_CLOCK … /* Register definitions and descriptions are from LinCAN 0.3.3. * * PSB4610 PITA-2 bridge control registers */ #define PITA2_ICR … #define PITA2_ICR_INT0 … #define PITA2_ICR_INT0_EN … #define PITA2_MISC … #define PITA2_MISC_CONFIG … /* Register definitions for the PLX 9030 */ #define PLX_ICSR … #define PLX_ICSR_LINTI1_ENA … #define PLX_ICSR_PCIINT_ENA … #define PLX_ICSR_LINTI1_CLR … #define PLX_ICSR_ENA_CLR … /* Register definitions for the ASIX99100 */ #define ASIX_LINTSR … #define ASIX_LINTSR_INT0AC … #define ASIX_LIEMR … #define ASIX_LIEMR_L0EINTEN … #define ASIX_LIEMR_LRST … /* The board configuration is probably following: * RX1 is connected to ground. * TX1 is not connected. * CLKO is not connected. * Setting the OCR register to 0xDA is a good idea. * This means normal output mode, push-pull and the correct polarity. */ #define EMS_PCI_OCR … /* In the CDR register, you should set CBP to 1. * You will probably also want to set the clock divider value to 7 * (meaning direct oscillator output) because the second SJA1000 chip * is driven by the first one CLKOUT output. */ #define EMS_PCI_CDR … #define EMS_PCI_V1_BASE_BAR … #define EMS_PCI_V1_CONF_BAR … #define EMS_PCI_V1_CONF_SIZE … #define EMS_PCI_V1_CAN_BASE_OFFSET … #define EMS_PCI_V1_CAN_CTRL_SIZE … #define EMS_PCI_V2_BASE_BAR … #define EMS_PCI_V2_CONF_BAR … #define EMS_PCI_V2_CONF_SIZE … #define EMS_PCI_V2_CAN_BASE_OFFSET … #define EMS_PCI_V2_CAN_CTRL_SIZE … #define EMS_PCI_V3_BASE_BAR … #define EMS_PCI_V3_CONF_BAR … #define EMS_PCI_V3_CONF_SIZE … #define EMS_PCI_V3_CAN_BASE_OFFSET … #define EMS_PCI_V3_CAN_CTRL_SIZE … #define EMS_PCI_BASE_SIZE … #define PCI_SUBDEVICE_ID_EMS … static const struct pci_device_id ems_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, ems_pci_tbl); /* Helper to read internal registers from card logic (not CAN) */ static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port) { … } static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port) { … } static void ems_pci_v1_write_reg(const struct sja1000_priv *priv, int port, u8 val) { … } static void ems_pci_v1_post_irq(const struct sja1000_priv *priv) { … } static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port) { … } static void ems_pci_v2_write_reg(const struct sja1000_priv *priv, int port, u8 val) { … } static void ems_pci_v2_post_irq(const struct sja1000_priv *priv) { … } static u8 ems_pci_v3_read_reg(const struct sja1000_priv *priv, int port) { … } static void ems_pci_v3_write_reg(const struct sja1000_priv *priv, int port, u8 val) { … } static void ems_pci_v3_post_irq(const struct sja1000_priv *priv) { … } /* Check if a CAN controller is present at the specified location * by trying to set 'em into the PeliCAN mode */ static inline int ems_pci_check_chan(const struct sja1000_priv *priv) { … } static void ems_pci_del_card(struct pci_dev *pdev) { … } static void ems_pci_card_reset(struct ems_pci_card *card) { … } /* Probe PCI device for EMS CAN signature and register each available * CAN channel to SJA1000 Socket-CAN subsystem. */ static int ems_pci_add_card(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static struct pci_driver ems_pci_driver = …; module_pci_driver(…) …;
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