/* * B53 register definitions * * Copyright (C) 2004 Broadcom Corporation * Copyright (C) 2011-2013 Jonas Gorski <[email protected]> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef __B53_REGS_H #define __B53_REGS_H /* Management Port (SMP) Page offsets */ #define B53_CTRL_PAGE … #define B53_STAT_PAGE … #define B53_MGMT_PAGE … #define B53_MIB_AC_PAGE … #define B53_ARLCTRL_PAGE … #define B53_ARLIO_PAGE … #define B53_FRAMEBUF_PAGE … #define B53_MEM_ACCESS_PAGE … /* PHY Registers */ #define B53_PORT_MII_PAGE(i) … #define B53_IM_PORT_PAGE … #define B53_ALL_PORT_PAGE … /* MIB registers */ #define B53_MIB_PAGE(i) … /* Quality of Service (QoS) Registers */ #define B53_QOS_PAGE … /* Port VLAN Page */ #define B53_PVLAN_PAGE … /* VLAN Registers */ #define B53_VLAN_PAGE … /* Jumbo Frame Registers */ #define B53_JUMBO_PAGE … /* EEE Control Registers Page */ #define B53_EEE_PAGE … /* CFP Configuration Registers Page */ #define B53_CFP_PAGE … /************************************************************************* * Control Page registers *************************************************************************/ /* Port Control Register (8 bit) */ #define B53_PORT_CTRL(i) … #define PORT_CTRL_RX_DISABLE … #define PORT_CTRL_TX_DISABLE … #define PORT_CTRL_RX_BCST_EN … #define PORT_CTRL_RX_MCST_EN … #define PORT_CTRL_RX_UCST_EN … #define PORT_CTRL_STP_STATE_S … #define PORT_CTRL_NO_STP … #define PORT_CTRL_DIS_STATE … #define PORT_CTRL_BLOCK_STATE … #define PORT_CTRL_LISTEN_STATE … #define PORT_CTRL_LEARN_STATE … #define PORT_CTRL_FWD_STATE … #define PORT_CTRL_STP_STATE_MASK … /* SMP Control Register (8 bit) */ #define B53_SMP_CTRL … /* Switch Mode Control Register (8 bit) */ #define B53_SWITCH_MODE … #define SM_SW_FWD_MODE … #define SM_SW_FWD_EN … /* IMP Port state override register (8 bit) */ #define B53_PORT_OVERRIDE_CTRL … #define PORT_OVERRIDE_LINK … #define PORT_OVERRIDE_FULL_DUPLEX … #define PORT_OVERRIDE_SPEED_S … #define PORT_OVERRIDE_SPEED_10M … #define PORT_OVERRIDE_SPEED_100M … #define PORT_OVERRIDE_SPEED_1000M … #define PORT_OVERRIDE_RV_MII_25 … #define PORT_OVERRIDE_RX_FLOW … #define PORT_OVERRIDE_TX_FLOW … #define PORT_OVERRIDE_SPEED_2000M … #define PORT_OVERRIDE_EN … /* Power-down mode control */ #define B53_PD_MODE_CTRL_25 … /* IP Multicast control (8 bit) */ #define B53_IP_MULTICAST_CTRL … #define B53_IPMC_FWD_EN … #define B53_UC_FWD_EN … #define B53_MC_FWD_EN … /* Switch control (8 bit) */ #define B53_SWITCH_CTRL … #define B53_MII_DUMB_FWDG_EN … /* (16 bit) */ #define B53_UC_FLOOD_MASK … #define B53_MC_FLOOD_MASK … #define B53_IPMC_FLOOD_MASK … #define B53_DIS_LEARNING … /* * Override Ports 0-7 State on devices with xMII interfaces (8 bit) * * For port 8 still use B53_PORT_OVERRIDE_CTRL * Please note that not all ports are available on every hardware, e.g. BCM5301X * don't include overriding port 6, BCM63xx also have some limitations. */ #define B53_GMII_PORT_OVERRIDE_CTRL(i) … #define GMII_PO_LINK … #define GMII_PO_FULL_DUPLEX … #define GMII_PO_SPEED_S … #define GMII_PO_SPEED_10M … #define GMII_PO_SPEED_100M … #define GMII_PO_SPEED_1000M … #define GMII_PO_RX_FLOW … #define GMII_PO_TX_FLOW … #define GMII_PO_EN … #define GMII_PO_SPEED_2000M … #define B53_RGMII_CTRL_IMP … #define RGMII_CTRL_ENABLE_GMII … #define RGMII_CTRL_MII_OVERRIDE … #define RGMII_CTRL_TIMING_SEL … #define RGMII_CTRL_DLL_RXC … #define RGMII_CTRL_DLL_TXC … #define B53_RGMII_CTRL_P(i) … /* Software reset register (8 bit) */ #define B53_SOFTRESET … #define SW_RST … #define EN_CH_RST … #define EN_SW_RST … /* Fast Aging Control register (8 bit) */ #define B53_FAST_AGE_CTRL … #define FAST_AGE_STATIC … #define FAST_AGE_DYNAMIC … #define FAST_AGE_PORT … #define FAST_AGE_VLAN … #define FAST_AGE_STP … #define FAST_AGE_MC … #define FAST_AGE_DONE … /* Fast Aging Port Control register (8 bit) */ #define B53_FAST_AGE_PORT_CTRL … /* Fast Aging VID Control register (16 bit) */ #define B53_FAST_AGE_VID_CTRL … /************************************************************************* * Status Page registers *************************************************************************/ /* Link Status Summary Register (16bit) */ #define B53_LINK_STAT … /* Link Status Change Register (16 bit) */ #define B53_LINK_STAT_CHANGE … /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ #define B53_SPEED_STAT … #define SPEED_PORT_FE(reg, port) … #define SPEED_PORT_GE(reg, port) … #define SPEED_STAT_10M … #define SPEED_STAT_100M … #define SPEED_STAT_1000M … /* Duplex Status Summary (16 bit) */ #define B53_DUPLEX_STAT_FE … #define B53_DUPLEX_STAT_GE … #define B53_DUPLEX_STAT_63XX … /* Revision ID register for BCM5325 */ #define B53_REV_ID_25 … /* Strap Value (48 bit) */ #define B53_STRAP_VALUE … #define SV_GMII_CTRL_115 … /************************************************************************* * Management Mode Page Registers *************************************************************************/ /* Global Management Config Register (8 bit) */ #define B53_GLOBAL_CONFIG … #define GC_RESET_MIB … #define GC_RX_BPDU_EN … #define GC_MIB_AC_HDR_EN … #define GC_MIB_AC_EN … #define GC_FRM_MGMT_PORT_M … #define GC_FRM_MGMT_PORT_04 … #define GC_FRM_MGMT_PORT_MII … /* Broadcom Header control register (8 bit) */ #define B53_BRCM_HDR … #define BRCM_HDR_P8_EN … #define BRCM_HDR_P5_EN … #define BRCM_HDR_P7_EN … /* Mirror capture control register (16 bit) */ #define B53_MIR_CAP_CTL … #define CAP_PORT_MASK … #define BLK_NOT_MIR … #define MIRROR_EN … /* Ingress mirror control register (16 bit) */ #define B53_IG_MIR_CTL … #define MIRROR_MASK … #define DIV_EN … #define MIRROR_FILTER_MASK … #define MIRROR_FILTER_SHIFT … #define MIRROR_ALL … #define MIRROR_DA … #define MIRROR_SA … /* Ingress mirror divider register (16 bit) */ #define B53_IG_MIR_DIV … #define IN_MIRROR_DIV_MASK … /* Ingress mirror MAC address register (48 bit) */ #define B53_IG_MIR_MAC … /* Egress mirror control register (16 bit) */ #define B53_EG_MIR_CTL … /* Egress mirror divider register (16 bit) */ #define B53_EG_MIR_DIV … /* Egress mirror MAC address register (48 bit) */ #define B53_EG_MIR_MAC … /* Device ID register (8 or 32 bit) */ #define B53_DEVICE_ID … /* Revision ID register (8 bit) */ #define B53_REV_ID … /* Broadcom header RX control (16 bit) */ #define B53_BRCM_HDR_RX_DIS … /* Broadcom header TX control (16 bit) */ #define B53_BRCM_HDR_TX_DIS … /************************************************************************* * ARL Access Page Registers *************************************************************************/ /* VLAN Table Access Register (8 bit) */ #define B53_VT_ACCESS … #define B53_VT_ACCESS_9798 … #define B53_VT_ACCESS_63XX … #define VTA_CMD_WRITE … #define VTA_CMD_READ … #define VTA_CMD_CLEAR … #define VTA_START_CMD … /* VLAN Table Index Register (16 bit) */ #define B53_VT_INDEX … #define B53_VT_INDEX_9798 … #define B53_VT_INDEX_63XX … /* VLAN Table Entry Register (32 bit) */ #define B53_VT_ENTRY … #define B53_VT_ENTRY_9798 … #define B53_VT_ENTRY_63XX … #define VTE_MEMBERS … #define VTE_UNTAG_S … #define VTE_UNTAG … /************************************************************************* * ARL I/O Registers *************************************************************************/ /* ARL Table Read/Write Register (8 bit) */ #define B53_ARLTBL_RW_CTRL … #define ARLTBL_RW … #define ARLTBL_IVL_SVL_SELECT … #define ARLTBL_START_DONE … /* MAC Address Index Register (48 bit) */ #define B53_MAC_ADDR_IDX … /* VLAN ID Index Register (16 bit) */ #define B53_VLAN_ID_IDX … /* ARL Table MAC/VID Entry N Registers (64 bit) * * BCM5325 and BCM5365 share most definitions below */ #define B53_ARLTBL_MAC_VID_ENTRY(n) … #define ARLTBL_MAC_MASK … #define ARLTBL_VID_S … #define ARLTBL_VID_MASK_25 … #define ARLTBL_VID_MASK … #define ARLTBL_DATA_PORT_ID_S_25 … #define ARLTBL_DATA_PORT_ID_MASK_25 … #define ARLTBL_AGE_25 … #define ARLTBL_STATIC_25 … #define ARLTBL_VALID_25 … /* ARL Table Data Entry N Registers (32 bit) */ #define B53_ARLTBL_DATA_ENTRY(n) … #define ARLTBL_DATA_PORT_ID_MASK … #define ARLTBL_TC(tc) … #define ARLTBL_AGE … #define ARLTBL_STATIC … #define ARLTBL_VALID … /* Maximum number of bin entries in the ARL for all switches */ #define B53_ARLTBL_MAX_BIN_ENTRIES … /* ARL Search Control Register (8 bit) */ #define B53_ARL_SRCH_CTL … #define B53_ARL_SRCH_CTL_25 … #define ARL_SRCH_VLID … #define ARL_SRCH_STDN … /* ARL Search Address Register (16 bit) */ #define B53_ARL_SRCH_ADDR … #define B53_ARL_SRCH_ADDR_25 … #define B53_ARL_SRCH_ADDR_65 … #define ARL_ADDR_MASK … /* ARL Search MAC/VID Result (64 bit) */ #define B53_ARL_SRCH_RSTL_0_MACVID … /* Single register search result on 5325 */ #define B53_ARL_SRCH_RSTL_0_MACVID_25 … /* Single register search result on 5365 */ #define B53_ARL_SRCH_RSTL_0_MACVID_65 … /* ARL Search Data Result (32 bit) */ #define B53_ARL_SRCH_RSTL_0 … #define B53_ARL_SRCH_RSTL_MACVID(x) … #define B53_ARL_SRCH_RSTL(x) … /************************************************************************* * Port VLAN Registers *************************************************************************/ /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ #define B53_PVLAN_PORT_MASK(i) … /* Join all VLANs register (16 bit) */ #define B53_JOIN_ALL_VLAN_EN … /************************************************************************* * 802.1Q Page Registers *************************************************************************/ /* Global QoS Control (8 bit) */ #define B53_QOS_GLOBAL_CTL … /* Enable 802.1Q for individual Ports (16 bit) */ #define B53_802_1P_EN … /************************************************************************* * VLAN Page Registers *************************************************************************/ /* VLAN Control 0 (8 bit) */ #define B53_VLAN_CTRL0 … #define VC0_8021PF_CTRL_MASK … #define VC0_8021PF_CTRL_NONE … #define VC0_8021PF_CTRL_CHANGE_PRI … #define VC0_8021PF_CTRL_CHANGE_VID … #define VC0_8021PF_CTRL_CHANGE_BOTH … #define VC0_8021QF_CTRL_MASK … #define VC0_8021QF_CTRL_CHANGE_PRI … #define VC0_8021QF_CTRL_CHANGE_VID … #define VC0_8021QF_CTRL_CHANGE_BOTH … #define VC0_RESERVED_1 … #define VC0_DROP_VID_MISS … #define VC0_VID_HASH_VID … #define VC0_VID_CHK_EN … #define VC0_VLAN_EN … /* VLAN Control 1 (8 bit) */ #define B53_VLAN_CTRL1 … #define VC1_RX_MCST_TAG_EN … #define VC1_RX_MCST_FWD_EN … #define VC1_RX_MCST_UNTAG_EN … /* VLAN Control 2 (8 bit) */ #define B53_VLAN_CTRL2 … /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ #define B53_VLAN_CTRL3 … #define B53_VLAN_CTRL3_63XX … #define VC3_MAXSIZE_1532 … #define VC3_HIGH_8BIT_EN … /* VLAN Control 4 (8 bit) */ #define B53_VLAN_CTRL4 … #define B53_VLAN_CTRL4_25 … #define B53_VLAN_CTRL4_63XX … #define VC4_ING_VID_CHECK_S … #define VC4_ING_VID_CHECK_MASK … #define VC4_ING_VID_VIO_FWD … #define VC4_ING_VID_VIO_DROP … #define VC4_NO_ING_VID_CHK … #define VC4_ING_VID_VIO_TO_IMP … /* VLAN Control 5 (8 bit) */ #define B53_VLAN_CTRL5 … #define B53_VLAN_CTRL5_25 … #define B53_VLAN_CTRL5_63XX … #define VC5_VID_FFF_EN … #define VC5_DROP_VTABLE_MISS … /* VLAN Control 6 (8 bit) */ #define B53_VLAN_CTRL6 … #define B53_VLAN_CTRL6_63XX … /* VLAN Table Access Register (16 bit) */ #define B53_VLAN_TABLE_ACCESS_25 … #define B53_VLAN_TABLE_ACCESS_65 … #define VTA_VID_LOW_MASK_25 … #define VTA_VID_LOW_MASK_65 … #define VTA_VID_HIGH_S_25 … #define VTA_VID_HIGH_S_65 … #define VTA_VID_HIGH_MASK_25 … #define VTA_VID_HIGH_MASK_65 … #define VTA_RW_STATE … #define VTA_RW_STATE_RD … #define VTA_RW_STATE_WR … #define VTA_RW_OP_EN … /* VLAN Read/Write Registers for (16/32 bit) */ #define B53_VLAN_WRITE_25 … #define B53_VLAN_WRITE_65 … #define B53_VLAN_READ … #define VA_MEMBER_MASK … #define VA_UNTAG_S_25 … #define VA_UNTAG_MASK_25 … #define VA_UNTAG_S_65 … #define VA_UNTAG_MASK_65 … #define VA_VID_HIGH_S … #define VA_VID_HIGH_MASK … #define VA_VALID_25 … #define VA_VALID_25_R4 … #define VA_VALID_65 … /* VLAN Port Default Tag (16 bit) */ #define B53_VLAN_PORT_DEF_TAG(i) … /************************************************************************* * Jumbo Frame Page Registers *************************************************************************/ /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ #define B53_JUMBO_PORT_MASK … #define B53_JUMBO_PORT_MASK_63XX … #define JPM_10_100_JUMBO_EN … /* Good Frame Max Size without 802.1Q TAG (16 bit) */ #define B53_JUMBO_MAX_SIZE … #define B53_JUMBO_MAX_SIZE_63XX … #define JMS_MIN_SIZE … #define JMS_MAX_SIZE … /************************************************************************* * EEE Configuration Page Registers *************************************************************************/ /* EEE Enable control register (16 bit) */ #define B53_EEE_EN_CTRL … /* EEE LPI assert status register (16 bit) */ #define B53_EEE_LPI_ASSERT_STS … /* EEE LPI indicate status register (16 bit) */ #define B53_EEE_LPI_INDICATE … /* EEE Receiving idle symbols status register (16 bit) */ #define B53_EEE_RX_IDLE_SYM_STS … /* EEE Pipeline timer register (32 bit) */ #define B53_EEE_PIP_TIMER … /* EEE Sleep timer Gig register (32 bit) */ #define B53_EEE_SLEEP_TIMER_GIG(i) … /* EEE Sleep timer FE register (32 bit) */ #define B53_EEE_SLEEP_TIMER_FE(i) … /* EEE Minimum LP timer Gig register (32 bit) */ #define B53_EEE_MIN_LP_TIMER_GIG(i) … /* EEE Minimum LP timer FE register (32 bit) */ #define B53_EEE_MIN_LP_TIMER_FE(i) … /* EEE Wake timer Gig register (16 bit) */ #define B53_EEE_WAKE_TIMER_GIG(i) … /* EEE Wake timer FE register (16 bit) */ #define B53_EEE_WAKE_TIMER_FE(i) … /************************************************************************* * CFP Configuration Page Registers *************************************************************************/ /* CFP Control Register with ports map (8 bit) */ #define B53_CFP_CTRL … #endif /* !__B53_REGS_H */
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