// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause /* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved. * Parts of this driver are based on the following: * - Kvaser linux pciefd driver (version 5.42) * - PEAK linux canfd driver */ #include <linux/bitfield.h> #include <linux/can/dev.h> #include <linux/device.h> #include <linux/ethtool.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/minmax.h> #include <linux/module.h> #include <linux/netdevice.h> #include <linux/pci.h> #include <linux/timer.h> MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; #define KVASER_PCIEFD_DRV_NAME … #define KVASER_PCIEFD_WAIT_TIMEOUT … #define KVASER_PCIEFD_BEC_POLL_FREQ … #define KVASER_PCIEFD_MAX_ERR_REP … #define KVASER_PCIEFD_CAN_TX_MAX_COUNT … #define KVASER_PCIEFD_MAX_CAN_CHANNELS … #define KVASER_PCIEFD_DMA_COUNT … #define KVASER_PCIEFD_DMA_SIZE … #define KVASER_PCIEFD_VENDOR … /* Altera based devices */ #define KVASER_PCIEFD_4HS_DEVICE_ID … #define KVASER_PCIEFD_2HS_V2_DEVICE_ID … #define KVASER_PCIEFD_HS_V2_DEVICE_ID … #define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID … #define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID … /* SmartFusion2 based devices */ #define KVASER_PCIEFD_2CAN_V3_DEVICE_ID … #define KVASER_PCIEFD_1CAN_V3_DEVICE_ID … #define KVASER_PCIEFD_4CAN_V2_DEVICE_ID … #define KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID … #define KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID … /* Xilinx based devices */ #define KVASER_PCIEFD_M2_4CAN_DEVICE_ID … #define KVASER_PCIEFD_8CAN_DEVICE_ID … /* Altera SerDes Enable 64-bit DMA address translation */ #define KVASER_PCIEFD_ALTERA_DMA_64BIT … /* SmartFusion2 SerDes LSB address translation mask */ #define KVASER_PCIEFD_SF2_DMA_LSB_MASK … /* Xilinx SerDes LSB address translation mask */ #define KVASER_PCIEFD_XILINX_DMA_LSB_MASK … /* Kvaser KCAN CAN controller registers */ #define KVASER_PCIEFD_KCAN_FIFO_REG … #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG … #define KVASER_PCIEFD_KCAN_CTRL_REG … #define KVASER_PCIEFD_KCAN_CMD_REG … #define KVASER_PCIEFD_KCAN_IEN_REG … #define KVASER_PCIEFD_KCAN_IRQ_REG … #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG … #define KVASER_PCIEFD_KCAN_STAT_REG … #define KVASER_PCIEFD_KCAN_MODE_REG … #define KVASER_PCIEFD_KCAN_BTRN_REG … #define KVASER_PCIEFD_KCAN_BUS_LOAD_REG … #define KVASER_PCIEFD_KCAN_BTRD_REG … #define KVASER_PCIEFD_KCAN_PWM_REG … /* System identification and information registers */ #define KVASER_PCIEFD_SYSID_VERSION_REG … #define KVASER_PCIEFD_SYSID_CANFREQ_REG … #define KVASER_PCIEFD_SYSID_BUSFREQ_REG … #define KVASER_PCIEFD_SYSID_BUILD_REG … /* Shared receive buffer FIFO registers */ #define KVASER_PCIEFD_SRB_FIFO_LAST_REG … /* Shared receive buffer registers */ #define KVASER_PCIEFD_SRB_CMD_REG … #define KVASER_PCIEFD_SRB_IEN_REG … #define KVASER_PCIEFD_SRB_IRQ_REG … #define KVASER_PCIEFD_SRB_STAT_REG … #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG … #define KVASER_PCIEFD_SRB_CTRL_REG … /* System build information fields */ #define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK … #define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK … #define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK … #define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK … /* Reset DMA buffer 0, 1 and FIFO offset */ #define KVASER_PCIEFD_SRB_CMD_RDB1 … #define KVASER_PCIEFD_SRB_CMD_RDB0 … #define KVASER_PCIEFD_SRB_CMD_FOR … /* DMA underflow, buffer 0 and 1 */ #define KVASER_PCIEFD_SRB_IRQ_DUF1 … #define KVASER_PCIEFD_SRB_IRQ_DUF0 … /* DMA overflow, buffer 0 and 1 */ #define KVASER_PCIEFD_SRB_IRQ_DOF1 … #define KVASER_PCIEFD_SRB_IRQ_DOF0 … /* DMA packet done, buffer 0 and 1 */ #define KVASER_PCIEFD_SRB_IRQ_DPD1 … #define KVASER_PCIEFD_SRB_IRQ_DPD0 … /* Got DMA support */ #define KVASER_PCIEFD_SRB_STAT_DMA … /* DMA idle */ #define KVASER_PCIEFD_SRB_STAT_DI … /* SRB current packet level */ #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK … /* DMA Enable */ #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE … /* KCAN CTRL packet types */ #define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK … #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH … #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME … /* Command sequence number */ #define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK … /* Command bits */ #define KVASER_PCIEFD_KCAN_CMD_MASK … /* Abort, flush and reset */ #define KVASER_PCIEFD_KCAN_CMD_AT … /* Request status packet */ #define KVASER_PCIEFD_KCAN_CMD_SRQ … /* Transmitter unaligned */ #define KVASER_PCIEFD_KCAN_IRQ_TAL … /* Tx FIFO empty */ #define KVASER_PCIEFD_KCAN_IRQ_TE … /* Tx FIFO overflow */ #define KVASER_PCIEFD_KCAN_IRQ_TOF … /* Tx buffer flush done */ #define KVASER_PCIEFD_KCAN_IRQ_TFD … /* Abort done */ #define KVASER_PCIEFD_KCAN_IRQ_ABD … /* Rx FIFO overflow */ #define KVASER_PCIEFD_KCAN_IRQ_ROF … /* FDF bit when controller is in classic CAN mode */ #define KVASER_PCIEFD_KCAN_IRQ_FDIC … /* Bus parameter protection error */ #define KVASER_PCIEFD_KCAN_IRQ_BPP … /* Tx FIFO unaligned end */ #define KVASER_PCIEFD_KCAN_IRQ_TAE … /* Tx FIFO unaligned read */ #define KVASER_PCIEFD_KCAN_IRQ_TAR … /* Tx FIFO size */ #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK … /* Tx FIFO current packet level */ #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK … /* Current status packet sequence number */ #define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK … /* Controller got CAN FD capability */ #define KVASER_PCIEFD_KCAN_STAT_FD … /* Controller got one-shot capability */ #define KVASER_PCIEFD_KCAN_STAT_CAP … /* Controller in reset mode */ #define KVASER_PCIEFD_KCAN_STAT_IRM … /* Reset mode request */ #define KVASER_PCIEFD_KCAN_STAT_RMR … /* Bus off */ #define KVASER_PCIEFD_KCAN_STAT_BOFF … /* Idle state. Controller in reset mode and no abort or flush pending */ #define KVASER_PCIEFD_KCAN_STAT_IDLE … /* Abort request */ #define KVASER_PCIEFD_KCAN_STAT_AR … /* Controller is bus off */ #define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK … /* Classic CAN mode */ #define KVASER_PCIEFD_KCAN_MODE_CCM … /* Active error flag enable. Clear to force error passive */ #define KVASER_PCIEFD_KCAN_MODE_EEN … /* Acknowledgment packet type */ #define KVASER_PCIEFD_KCAN_MODE_APT … /* CAN FD non-ISO */ #define KVASER_PCIEFD_KCAN_MODE_NIFDEN … /* Error packet enable */ #define KVASER_PCIEFD_KCAN_MODE_EPEN … /* Listen only mode */ #define KVASER_PCIEFD_KCAN_MODE_LOM … /* Reset mode */ #define KVASER_PCIEFD_KCAN_MODE_RM … /* BTRN and BTRD fields */ #define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK … #define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK … #define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK … #define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK … /* PWM Control fields */ #define KVASER_PCIEFD_KCAN_PWM_TOP_MASK … #define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK … /* KCAN packet type IDs */ #define KVASER_PCIEFD_PACK_TYPE_DATA … #define KVASER_PCIEFD_PACK_TYPE_ACK … #define KVASER_PCIEFD_PACK_TYPE_TXRQ … #define KVASER_PCIEFD_PACK_TYPE_ERROR … #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK … #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK … #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA … #define KVASER_PCIEFD_PACK_TYPE_STATUS … #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD … /* Common KCAN packet definitions, second word */ #define KVASER_PCIEFD_PACKET_TYPE_MASK … #define KVASER_PCIEFD_PACKET_CHID_MASK … #define KVASER_PCIEFD_PACKET_SEQ_MASK … /* KCAN Transmit/Receive data packet, first word */ #define KVASER_PCIEFD_RPACKET_IDE … #define KVASER_PCIEFD_RPACKET_RTR … #define KVASER_PCIEFD_RPACKET_ID_MASK … /* KCAN Transmit data packet, second word */ #define KVASER_PCIEFD_TPACKET_AREQ … #define KVASER_PCIEFD_TPACKET_SMS … /* KCAN Transmit/Receive data packet, second word */ #define KVASER_PCIEFD_RPACKET_FDF … #define KVASER_PCIEFD_RPACKET_BRS … #define KVASER_PCIEFD_RPACKET_ESI … #define KVASER_PCIEFD_RPACKET_DLC_MASK … /* KCAN Transmit acknowledge packet, first word */ #define KVASER_PCIEFD_APACKET_NACK … #define KVASER_PCIEFD_APACKET_ABL … #define KVASER_PCIEFD_APACKET_CT … #define KVASER_PCIEFD_APACKET_FLU … /* KCAN Status packet, first word */ #define KVASER_PCIEFD_SPACK_RMCD … #define KVASER_PCIEFD_SPACK_IRM … #define KVASER_PCIEFD_SPACK_IDET … #define KVASER_PCIEFD_SPACK_BOFF … #define KVASER_PCIEFD_SPACK_RXERR_MASK … #define KVASER_PCIEFD_SPACK_TXERR_MASK … /* KCAN Status packet, second word */ #define KVASER_PCIEFD_SPACK_EPLR … #define KVASER_PCIEFD_SPACK_EWLR … #define KVASER_PCIEFD_SPACK_AUTO … /* KCAN Error detected packet, second word */ #define KVASER_PCIEFD_EPACK_DIR_TX … /* Macros for calculating addresses of registers */ #define KVASER_PCIEFD_GET_BLOCK_ADDR(pcie, block) … #define KVASER_PCIEFD_PCI_IEN_ADDR(pcie) … #define KVASER_PCIEFD_PCI_IRQ_ADDR(pcie) … #define KVASER_PCIEFD_SERDES_ADDR(pcie) … #define KVASER_PCIEFD_SYSID_ADDR(pcie) … #define KVASER_PCIEFD_LOOPBACK_ADDR(pcie) … #define KVASER_PCIEFD_SRB_FIFO_ADDR(pcie) … #define KVASER_PCIEFD_SRB_ADDR(pcie) … #define KVASER_PCIEFD_KCAN_CH0_ADDR(pcie) … #define KVASER_PCIEFD_KCAN_CH1_ADDR(pcie) … #define KVASER_PCIEFD_KCAN_CHANNEL_SPAN(pcie) … #define KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i) … struct kvaser_pciefd; static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie, dma_addr_t addr, int index); static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie, dma_addr_t addr, int index); static void kvaser_pciefd_write_dma_map_xilinx(struct kvaser_pciefd *pcie, dma_addr_t addr, int index); struct kvaser_pciefd_address_offset { … }; struct kvaser_pciefd_dev_ops { … }; struct kvaser_pciefd_irq_mask { … }; struct kvaser_pciefd_driver_data { … }; static const struct kvaser_pciefd_address_offset kvaser_pciefd_altera_address_offset = …; static const struct kvaser_pciefd_address_offset kvaser_pciefd_sf2_address_offset = …; static const struct kvaser_pciefd_address_offset kvaser_pciefd_xilinx_address_offset = …; static const struct kvaser_pciefd_irq_mask kvaser_pciefd_altera_irq_mask = …; static const struct kvaser_pciefd_irq_mask kvaser_pciefd_sf2_irq_mask = …; static const struct kvaser_pciefd_irq_mask kvaser_pciefd_xilinx_irq_mask = …; static const struct kvaser_pciefd_dev_ops kvaser_pciefd_altera_dev_ops = …; static const struct kvaser_pciefd_dev_ops kvaser_pciefd_sf2_dev_ops = …; static const struct kvaser_pciefd_dev_ops kvaser_pciefd_xilinx_dev_ops = …; static const struct kvaser_pciefd_driver_data kvaser_pciefd_altera_driver_data = …; static const struct kvaser_pciefd_driver_data kvaser_pciefd_sf2_driver_data = …; static const struct kvaser_pciefd_driver_data kvaser_pciefd_xilinx_driver_data = …; struct kvaser_pciefd_can { … }; struct kvaser_pciefd { … }; struct kvaser_pciefd_rx_packet { … }; struct kvaser_pciefd_tx_packet { … }; static const struct can_bittiming_const kvaser_pciefd_bittiming_const = …; static struct pci_device_id kvaser_pciefd_id_table[] = …; MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table); static inline void kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can *can, u32 cmd) { … } static inline void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can) { … } static inline void kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can *can) { … } static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can) { … } static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can) { … } static inline void kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) { … } static inline void kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd *pcie, struct sk_buff *skb, u64 timestamp) { … } static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) { … } static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) { … } static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) { … } static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) { … } static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can) { … } static int kvaser_pciefd_open(struct net_device *netdev) { … } static int kvaser_pciefd_stop(struct net_device *netdev) { … } static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, struct kvaser_pciefd_can *can, struct sk_buff *skb) { … } static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, struct net_device *netdev) { … } static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) { … } static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev) { … } static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev) { … } static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode) { … } static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev, struct can_berr_counter *bec) { … } static void kvaser_pciefd_bec_poll_timer(struct timer_list *data) { … } static const struct net_device_ops kvaser_pciefd_netdev_ops = …; static const struct ethtool_ops kvaser_pciefd_ethtool_ops = …; static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) { … } static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie) { … } static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie, dma_addr_t addr, int index) { … } static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie, dma_addr_t addr, int index) { … } static void kvaser_pciefd_write_dma_map_xilinx(struct kvaser_pciefd *pcie, dma_addr_t addr, int index) { … } static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) { … } static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie) { … } static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie, struct kvaser_pciefd_rx_packet *p, __le32 *data) { … } static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can, struct can_frame *cf, enum can_state new_state, enum can_state tx_state, enum can_state rx_state) { … } static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p, struct can_berr_counter *bec, enum can_state *new_state, enum can_state *tx_state, enum can_state *rx_state) { … } static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, struct kvaser_pciefd_rx_packet *p) { … } static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie, struct kvaser_pciefd_rx_packet *p) { … } static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos, int dma_buf) { … } static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf) { … } static u32 kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie) { … } static void kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) { … } static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) { … } static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie) { … } static int kvaser_pciefd_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie) { … } static void kvaser_pciefd_remove(struct pci_dev *pdev) { … } static struct pci_driver kvaser_pciefd = …; module_pci_driver(…) …
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