/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx Switch Global 2 Registers support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2016-2017 Savoir-faire Linux Inc. * Vivien Didelot <[email protected]> */ #ifndef _MV88E6XXX_GLOBAL2_H #define _MV88E6XXX_GLOBAL2_H #include "chip.h" /* Offset 0x00: Interrupt Source Register */ #define MV88E6XXX_G2_INT_SRC … #define MV88E6XXX_G2_INT_SRC_WDOG … #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT … #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH … #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT … #define MV88E6352_G2_INT_SRC_SERDES … #define MV88E6352_G2_INT_SRC_PHY … #define MV88E6390_G2_INT_SRC_PHY … #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG … /* Offset 0x01: Interrupt Mask Register */ #define MV88E6XXX_G2_INT_MASK … #define MV88E6XXX_G2_INT_MASK_WDOG … #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT … #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH … #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT … #define MV88E6352_G2_INT_MASK_SERDES … #define MV88E6352_G2_INT_MASK_PHY … #define MV88E6390_G2_INT_MASK_PHY … /* Offset 0x02: MGMT Enable Register 2x */ #define MV88E6XXX_G2_MGMT_EN_2X … /* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */ #define MV88E6393X_G2_MACLINK_INT_SRC … /* Offset 0x03: MGMT Enable Register 0x */ #define MV88E6XXX_G2_MGMT_EN_0X … /* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */ #define MV88E6393X_G2_MACLINK_INT_MASK … /* Offset 0x04: Flow Control Delay Register */ #define MV88E6XXX_G2_FLOW_CTL … /* Offset 0x05: Switch Management Register */ #define MV88E6XXX_G2_SWITCH_MGMT … #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA … #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS … #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG … #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI … #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU … #define MV88E6393X_G2_EGRESS_MONITOR_DEST … /* Offset 0x06: Device Mapping Table Register */ #define MV88E6XXX_G2_DEVICE_MAPPING … #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE … #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK … #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK … #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK … /* Offset 0x07: Trunk Mask Table Register */ #define MV88E6XXX_G2_TRUNK_MASK … #define MV88E6XXX_G2_TRUNK_MASK_UPDATE … #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK … #define MV88E6XXX_G2_TRUNK_MASK_HASH … /* Offset 0x08: Trunk Mapping Table Register */ #define MV88E6XXX_G2_TRUNK_MAPPING … #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE … #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK … /* Offset 0x09: Ingress Rate Command Register */ #define MV88E6XXX_G2_IRL_CMD … #define MV88E6XXX_G2_IRL_CMD_BUSY … #define MV88E6352_G2_IRL_CMD_OP_MASK … #define MV88E6352_G2_IRL_CMD_OP_NOOP … #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL … #define MV88E6352_G2_IRL_CMD_OP_INIT_RES … #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG … #define MV88E6352_G2_IRL_CMD_OP_READ_REG … #define MV88E6390_G2_IRL_CMD_OP_MASK … #define MV88E6390_G2_IRL_CMD_OP_READ_REG … #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL … #define MV88E6390_G2_IRL_CMD_OP_INIT_RES … #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG … #define MV88E6352_G2_IRL_CMD_PORT_MASK … #define MV88E6390_G2_IRL_CMD_PORT_MASK … #define MV88E6XXX_G2_IRL_CMD_RES_MASK … #define MV88E6XXX_G2_IRL_CMD_REG_MASK … /* Offset 0x0A: Ingress Rate Data Register */ #define MV88E6XXX_G2_IRL_DATA … #define MV88E6XXX_G2_IRL_DATA_MASK … /* Offset 0x0B: Cross-chip Port VLAN Register */ #define MV88E6XXX_G2_PVT_ADDR … #define MV88E6XXX_G2_PVT_ADDR_BUSY … #define MV88E6XXX_G2_PVT_ADDR_OP_MASK … #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES … #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN … #define MV88E6XXX_G2_PVT_ADDR_OP_READ … #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK … #define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK … /* Offset 0x0C: Cross-chip Port VLAN Data Register */ #define MV88E6XXX_G2_PVT_DATA … #define MV88E6XXX_G2_PVT_DATA_MASK … /* Offset 0x0D: Switch MAC/WoL/WoF Register */ #define MV88E6XXX_G2_SWITCH_MAC … #define MV88E6XXX_G2_SWITCH_MAC_UPDATE … #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK … #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK … /* Offset 0x0E: ATU Stats Register */ #define MV88E6XXX_G2_ATU_STATS … #define MV88E6XXX_G2_ATU_STATS_BIN_0 … #define MV88E6XXX_G2_ATU_STATS_BIN_1 … #define MV88E6XXX_G2_ATU_STATS_BIN_2 … #define MV88E6XXX_G2_ATU_STATS_BIN_3 … #define MV88E6XXX_G2_ATU_STATS_MODE_ALL … #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC … #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL … #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC … #define MV88E6XXX_G2_ATU_STATS_MASK … /* Offset 0x0F: Priority Override Table */ #define MV88E6XXX_G2_PRIO_OVERRIDE … #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE … #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET … #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK … #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN … #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK … #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN … #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK … /* Offset 0x14: EEPROM Command */ #define MV88E6XXX_G2_EEPROM_CMD … #define MV88E6XXX_G2_EEPROM_CMD_BUSY … #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK … #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE … #define MV88E6XXX_G2_EEPROM_CMD_OP_READ … #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD … #define MV88E6XXX_G2_EEPROM_CMD_RUNNING … #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN … #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK … #define MV88E6390_G2_EEPROM_CMD_DATA_MASK … /* Offset 0x15: EEPROM Data */ #define MV88E6352_G2_EEPROM_DATA … #define MV88E6352_G2_EEPROM_DATA_MASK … /* Offset 0x15: EEPROM Addr */ #define MV88E6390_G2_EEPROM_ADDR … #define MV88E6390_G2_EEPROM_ADDR_MASK … /* Offset 0x16: AVB Command Register */ #define MV88E6352_G2_AVB_CMD … #define MV88E6352_G2_AVB_CMD_BUSY … #define MV88E6352_G2_AVB_CMD_OP_READ … #define MV88E6352_G2_AVB_CMD_OP_READ_INCR … #define MV88E6352_G2_AVB_CMD_OP_WRITE … #define MV88E6390_G2_AVB_CMD_OP_READ … #define MV88E6390_G2_AVB_CMD_OP_READ_INCR … #define MV88E6390_G2_AVB_CMD_OP_WRITE … #define MV88E6352_G2_AVB_CMD_PORT_MASK … #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL … #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL … #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL … #define MV88E6390_G2_AVB_CMD_PORT_MASK … #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL … #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL … #define MV88E6352_G2_AVB_CMD_BLOCK_PTP … #define MV88E6352_G2_AVB_CMD_BLOCK_AVB … #define MV88E6352_G2_AVB_CMD_BLOCK_QAV … #define MV88E6352_G2_AVB_CMD_BLOCK_QVB … #define MV88E6352_G2_AVB_CMD_BLOCK_MASK … #define MV88E6352_G2_AVB_CMD_ADDR_MASK … /* Offset 0x17: AVB Data Register */ #define MV88E6352_G2_AVB_DATA … /* Offset 0x18: SMI PHY Command Register */ #define MV88E6XXX_G2_SMI_PHY_CMD … #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY … #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK … #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL … #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL … #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP … #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK … #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 … #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC … #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA … #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK … #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK … #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK … /* Offset 0x19: SMI PHY Data Register */ #define MV88E6XXX_G2_SMI_PHY_DATA … /* Offset 0x1A: Scratch and Misc. Register */ #define MV88E6XXX_G2_SCRATCH_MISC_MISC … #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE … #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK … #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK … /* Offset 0x1B: Watch Dog Control Register */ #define MV88E6250_G2_WDOG_CTL … #define MV88E6250_G2_WDOG_CTL_QC_HISTORY … #define MV88E6250_G2_WDOG_CTL_QC_EVENT … #define MV88E6250_G2_WDOG_CTL_QC_ENABLE … #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY … #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT … #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE … #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ … #define MV88E6250_G2_WDOG_CTL_HISTORY … #define MV88E6250_G2_WDOG_CTL_SWRESET … /* Offset 0x1B: Watch Dog Control Register */ #define MV88E6352_G2_WDOG_CTL … #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT … #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT … #define MV88E6352_G2_WDOG_CTL_QC_ENABLE … #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY … #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE … #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ … #define MV88E6352_G2_WDOG_CTL_HISTORY … #define MV88E6352_G2_WDOG_CTL_SWRESET … /* Offset 0x1B: Watch Dog Control Register */ #define MV88E6390_G2_WDOG_CTL … #define MV88E6390_G2_WDOG_CTL_UPDATE … #define MV88E6390_G2_WDOG_CTL_PTR_MASK … #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE … #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS … #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE … #define MV88E6390_G2_WDOG_CTL_PTR_EVENT … #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY … #define MV88E6390_G2_WDOG_CTL_DATA_MASK … #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH … #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER … #define MV88E6390_G2_WDOG_CTL_EGRESS … #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ … /* Offset 0x1C: QoS Weights Register */ #define MV88E6XXX_G2_QOS_WEIGHTS … #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE … #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK … #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK … #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK … /* Offset 0x1D: Misc Register */ #define MV88E6XXX_G2_MISC … #define MV88E6XXX_G2_MISC_5_BIT_PORT … #define MV88E6352_G2_NOEGR_POLICY … #define MV88E6390_G2_LAG_ID_4 … /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ /* Offset 0x02: Misc Configuration */ #define MV88E6352_G2_SCRATCH_MISC_CFG … #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI … /* Offset 0x60-0x61: GPIO Configuration */ #define MV88E6352_G2_SCRATCH_GPIO_CFG0 … #define MV88E6352_G2_SCRATCH_GPIO_CFG1 … /* Offset 0x62-0x63: GPIO Direction */ #define MV88E6352_G2_SCRATCH_GPIO_DIR0 … #define MV88E6352_G2_SCRATCH_GPIO_DIR1 … #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT … #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN … /* Offset 0x64-0x65: GPIO Data */ #define MV88E6352_G2_SCRATCH_GPIO_DATA0 … #define MV88E6352_G2_SCRATCH_GPIO_DATA1 … /* Offset 0x68-0x6F: GPIO Pin Control */ #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 … #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 … #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 … #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 … #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU … #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 … #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK … #define MV88E6352_G2_SCRATCH_CONFIG_DATA3 … #define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL … #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO … #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG … #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ … int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int bit, int val); int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, struct mii_bus *bus, int addr, int reg, u16 *val); int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, struct mii_bus *bus, int addr, int reg, u16 val); int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, struct mii_bus *bus, int addr, int devad, int reg, u16 *val); int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, struct mii_bus *bus, int addr, int devad, int reg, u16 val); int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, struct ethtool_eeprom *eeprom, u8 *data); int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, struct ethtool_eeprom *eeprom, u8 *data); int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, struct ethtool_eeprom *eeprom, u8 *data); int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, struct ethtool_eeprom *eeprom, u8 *data); int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev, int src_port, u16 *data); int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, int src_port, u16 data); int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, struct mii_bus *bus); void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, struct mii_bus *bus); int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, bool hash, u16 mask); int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, u16 map); int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, int port); int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip); extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops; extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; extern const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops; extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops; extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, bool external); int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, bool external); int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); #endif /* _MV88E6XXX_GLOBAL2_H */
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