linux/drivers/net/dsa/mv88e6xxx/global1.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Marvell 88E6xxx Switch Global (1) Registers support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <[email protected]>
 */

#include <linux/bitfield.h>

#include "chip.h"
#include "global1.h"

int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
{ … }

int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
{ … }

int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
			  bit, int val)
{ … }

int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
			   u16 mask, u16 val)
{ … }

/* Offset 0x00: Switch Global Status Register */

static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
{ … }

static int mv88e6250_g1_eeprom_reload(struct mv88e6xxx_chip *chip)
{ … }

/* Returns 0 when done, -EBUSY when waiting, other negative codes on error */
static int mv88e6xxx_g1_is_eeprom_done(struct mv88e6xxx_chip *chip)
{ … }

/* As the EEInt (EEPROM done) flag clears on read if the status register, this
 * function must be called directly after a hard reset or EEPROM ReLoad request,
 * or the done condition may have been missed
 */
int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
 */
int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
{ … }

/* Offset 0x04: Switch Global Control Register */

int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
{ … }

/* Offset 0x10: IP-PRI Mapping Register 0
 * Offset 0x11: IP-PRI Mapping Register 1
 * Offset 0x12: IP-PRI Mapping Register 2
 * Offset 0x13: IP-PRI Mapping Register 3
 * Offset 0x14: IP-PRI Mapping Register 4
 * Offset 0x15: IP-PRI Mapping Register 5
 * Offset 0x16: IP-PRI Mapping Register 6
 * Offset 0x17: IP-PRI Mapping Register 7
 */

int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x18: IEEE-PRI Register */

int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x1a: Monitor Control */
/* Offset 0x1a: Monitor & MGMT Control on some devices */

int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
				 enum mv88e6xxx_egress_direction direction,
				 int port)
{ … }

/* Older generations also call this the ARP destination. It has been
 * generalized in more modern devices such that more than ARP can
 * egress it
 */
int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
{ … }

static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
				      u16 pointer, u8 data)
{ … }

int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
				 enum mv88e6xxx_egress_direction direction,
				 int port)
{ … }

int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{ … }

/* Offset 0x1c: Global Control 2 */

static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
				  u16 val)
{ … }

int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
{ … }

/* Offset 0x1d: Statistics Operation 2 */

static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
{ … }

int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
{ … }

int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
{ … }

void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
{ … }

int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
{ … }