/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx Switch Port Registers support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2016-2017 Savoir-faire Linux Inc. * Vivien Didelot <[email protected]> */ #ifndef _MV88E6XXX_PORT_H #define _MV88E6XXX_PORT_H #include "chip.h" /* Offset 0x00: Port Status Register */ #define MV88E6XXX_PORT_STS … #define MV88E6XXX_PORT_STS_PAUSE_EN … #define MV88E6XXX_PORT_STS_MY_PAUSE … #define MV88E6XXX_PORT_STS_HD_FLOW … #define MV88E6XXX_PORT_STS_PHY_DETECT … #define MV88E6250_PORT_STS_LINK … #define MV88E6250_PORT_STS_PORTMODE_MASK … #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF … #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF … #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL … #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL … /* - Modes with PHY suffix use output instead of input clock * - Modes without RMII or RGMII use MII * - Modes without speed do not have a fixed speed specified in the manual * ("DC to x MHz" - variable clock support?) */ #define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED … #define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII … #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL … #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL … #define MV88E6250_PORT_STS_PORTMODE_MII_HALF … #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_FULL … #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY … #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY … #define MV88E6XXX_PORT_STS_LINK … #define MV88E6XXX_PORT_STS_DUPLEX … #define MV88E6XXX_PORT_STS_SPEED_MASK … #define MV88E6XXX_PORT_STS_SPEED_10 … #define MV88E6XXX_PORT_STS_SPEED_100 … #define MV88E6XXX_PORT_STS_SPEED_1000 … #define MV88E6XXX_PORT_STS_SPEED_10000 … #define MV88E6352_PORT_STS_EEE … #define MV88E6165_PORT_STS_AM_DIS … #define MV88E6185_PORT_STS_MGMII … #define MV88E6XXX_PORT_STS_TX_PAUSED … #define MV88E6XXX_PORT_STS_FLOW_CTL … #define MV88E6XXX_PORT_STS_CMODE_MASK … #define MV88E6XXX_PORT_STS_CMODE_MII_PHY … #define MV88E6XXX_PORT_STS_CMODE_MII … #define MV88E6XXX_PORT_STS_CMODE_GMII … #define MV88E6XXX_PORT_STS_CMODE_RMII_PHY … #define MV88E6XXX_PORT_STS_CMODE_RMII … #define MV88E6XXX_PORT_STS_CMODE_RGMII … #define MV88E6XXX_PORT_STS_CMODE_100BASEX … #define MV88E6XXX_PORT_STS_CMODE_1000BASEX … #define MV88E6XXX_PORT_STS_CMODE_SGMII … #define MV88E6XXX_PORT_STS_CMODE_2500BASEX … #define MV88E6XXX_PORT_STS_CMODE_XAUI … #define MV88E6XXX_PORT_STS_CMODE_RXAUI … #define MV88E6393X_PORT_STS_CMODE_5GBASER … #define MV88E6393X_PORT_STS_CMODE_10GBASER … #define MV88E6393X_PORT_STS_CMODE_USXGMII … #define MV88E6185_PORT_STS_CDUPLEX … #define MV88E6185_PORT_STS_CMODE_MASK … #define MV88E6185_PORT_STS_CMODE_GMII_FD … #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS … #define MV88E6185_PORT_STS_CMODE_MII_100 … #define MV88E6185_PORT_STS_CMODE_MII_10 … #define MV88E6185_PORT_STS_CMODE_SERDES … #define MV88E6185_PORT_STS_CMODE_1000BASE_X … #define MV88E6185_PORT_STS_CMODE_PHY … #define MV88E6185_PORT_STS_CMODE_DISABLED … /* Offset 0x01: MAC (or PCS or Physical) Control Register */ #define MV88E6XXX_PORT_MAC_CTL … #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK … #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK … #define MV88E6185_PORT_MAC_CTL_SYNC_OK … #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED … #define MV88E6390_PORT_MAC_CTL_ALTSPEED … #define MV88E6352_PORT_MAC_CTL_200BASE … #define MV88E6XXX_PORT_MAC_CTL_EEE … #define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE … #define MV88E6185_PORT_MAC_CTL_AN_EN … #define MV88E6185_PORT_MAC_CTL_AN_RESTART … #define MV88E6185_PORT_MAC_CTL_AN_DONE … #define MV88E6XXX_PORT_MAC_CTL_FC … #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC … #define MV88E6XXX_PORT_MAC_CTL_LINK_UP … #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK … #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL … #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX … #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK … #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 … #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 … #define MV88E6065_PORT_MAC_CTL_SPEED_200 … #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 … #define MV88E6390_PORT_MAC_CTL_SPEED_10000 … #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED … /* Offset 0x02: Jamming Control Register */ #define MV88E6097_PORT_JAM_CTL … #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK … #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK … /* Offset 0x02: Flow Control Register */ #define MV88E6390_PORT_FLOW_CTL … #define MV88E6390_PORT_FLOW_CTL_UPDATE … #define MV88E6390_PORT_FLOW_CTL_PTR_MASK … #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN … #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT … #define MV88E6390_PORT_FLOW_CTL_DATA_MASK … /* Offset 0x03: Switch Identifier Register */ #define MV88E6XXX_PORT_SWITCH_ID … #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 … #define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X … #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK … /* Offset 0x04: Port Control Register */ #define MV88E6XXX_PORT_CTL0 … #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG … #define MV88E6XXX_PORT_CTL0_SA_FILT_MASK … #define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED … #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK … #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK … #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU … #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK … #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED … #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED … #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED … #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA … #define MV88E6XXX_PORT_CTL0_HEADER … #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP … #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG … #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK … #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL … #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA … #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER … #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA … #define MV88E6XXX_PORT_CTL0_DSA_TAG … #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL … #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH … #define MV88E6185_PORT_CTL0_USE_IP … #define MV88E6185_PORT_CTL0_USE_TAG … #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN … #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC … #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC … #define MV88E6XXX_PORT_CTL0_STATE_MASK … #define MV88E6XXX_PORT_CTL0_STATE_DISABLED … #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING … #define MV88E6XXX_PORT_CTL0_STATE_LEARNING … #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING … /* Offset 0x05: Port Control 1 */ #define MV88E6XXX_PORT_CTL1 … #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT … #define MV88E6XXX_PORT_CTL1_TRUNK_PORT … #define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK … #define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT … #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK … /* Offset 0x06: Port Based VLAN Map */ #define MV88E6XXX_PORT_BASE_VLAN … #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK … /* Offset 0x07: Default Port VLAN ID & Priority */ #define MV88E6XXX_PORT_DEFAULT_VLAN … #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK … /* Offset 0x08: Port Control 2 Register */ #define MV88E6XXX_PORT_CTL2 … #define MV88E6XXX_PORT_CTL2_IGNORE_FCS … #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE … #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE … #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE … #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK … #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 … #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 … #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 … #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK … #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED … #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK … #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK … #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE … #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED … #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED … #define MV88E6XXX_PORT_CTL2_MAP_DA … #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD … #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR … #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR … #define MV88E6095_PORT_CTL2_CPU_PORT_MASK … /* Offset 0x09: Egress Rate Control */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 … /* Offset 0x0A: Egress Rate Control 2 */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 … /* Offset 0x0B: Port Association Vector */ #define MV88E6XXX_PORT_ASSOC_VECTOR … #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 … #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT … #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT … #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG … #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED … /* Offset 0x0C: Port ATU Control */ #define MV88E6XXX_PORT_ATU_CTL … /* Offset 0x0D: Priority Override Register */ #define MV88E6XXX_PORT_PRI_OVERRIDE … /* Offset 0x0E: Policy Control Register */ #define MV88E6XXX_PORT_POLICY_CTL … #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK … #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK … #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK … #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK … #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK … #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK … #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK … #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK … #define MV88E6XXX_PORT_POLICY_CTL_NORMAL … #define MV88E6XXX_PORT_POLICY_CTL_MIRROR … #define MV88E6XXX_PORT_POLICY_CTL_TRAP … #define MV88E6XXX_PORT_POLICY_CTL_DISCARD … /* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ #define MV88E6393X_PORT_POLICY_MGMT_CTL … #define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK … #define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST … #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST … #define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI … /* Offset 0x0F: Port Special Ether Type */ #define MV88E6XXX_PORT_ETH_TYPE … #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT … /* Offset 0x10: InDiscards Low Counter */ #define MV88E6XXX_PORT_IN_DISCARD_LO … /* Offset 0x10: Extended Port Control Command */ #define MV88E6393X_PORT_EPC_CMD … #define MV88E6393X_PORT_EPC_CMD_BUSY … #define MV88E6393X_PORT_EPC_CMD_WRITE … #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE … /* Offset 0x11: Extended Port Control Data */ #define MV88E6393X_PORT_EPC_DATA … /* Offset 0x11: InDiscards High Counter */ #define MV88E6XXX_PORT_IN_DISCARD_HI … /* Offset 0x12: InFiltered Counter */ #define MV88E6XXX_PORT_IN_FILTERED … /* Offset 0x13: OutFiltered Counter */ #define MV88E6XXX_PORT_OUT_FILTERED … /* Offset 0x18: IEEE Priority Mapping Table */ #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK … #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK … /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 … /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 … /* Offset 0x1a: Magic undocumented errata register */ #define MV88E6XXX_PORT_RESERVED_1A … #define MV88E6XXX_PORT_RESERVED_1A_BUSY … #define MV88E6XXX_PORT_RESERVED_1A_WRITE … #define MV88E6XXX_PORT_RESERVED_1A_READ … #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT … #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT … #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT … #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT … #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE … #define MV88E6341_PORT_RESERVED_1A_SGMII_AN … int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, u16 *val); int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, u16 val); int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, int bit, int val); int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, int pause); int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, int speed, int duplex); phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port); phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port); phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port); phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, bool locked); int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, u16 mode); int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_egress_mode mode); int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_frame_mode mode); int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_frame_mode mode); int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, int port, bool unicast); int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, int port, bool multicast); int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, bool unicast); int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, bool multicast); int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_policy_mapping mapping, enum mv88e6xxx_policy_action action); int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_policy_mapping mapping, enum mv88e6xxx_policy_action action); int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, u16 etype); int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, enum mv88e6xxx_egress_direction direction, int port); int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, int upstream_port); int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, u16 etype); int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, bool message_port); int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, bool trunk, u8 id); int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, size_t size); int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, u16 pav); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, phy_interface_t mode); int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, bool drop_untagged); int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, int upstream_port); int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, enum mv88e6xxx_egress_direction direction, bool mirror); int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, int port, int reg, u16 val); int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, int reg, u16 *val); #endif /* _MV88E6XXX_PORT_H */
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