/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx Switch hardware timestamping support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2017 National Instruments * Erik Hons <[email protected]> * Brandon Streiff <[email protected]> * Dane Wagner <[email protected]> */ #ifndef _MV88E6XXX_HWTSTAMP_H #define _MV88E6XXX_HWTSTAMP_H #include "chip.h" /* Global 6352 PTP registers */ /* Offset 0x00: PTP EtherType */ #define MV88E6XXX_PTP_ETHERTYPE … /* Offset 0x01: Message Type Timestamp Enables */ #define MV88E6XXX_PTP_MSGTYPE … #define MV88E6XXX_PTP_MSGTYPE_SYNC … #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ … #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ … #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES … #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT … /* Offset 0x02: Timestamp Arrival Capture Pointers */ #define MV88E6XXX_PTP_TS_ARRIVAL_PTR … /* Offset 0x05: PTP Global Configuration */ #define MV88E6165_PTP_CFG … #define MV88E6165_PTP_CFG_TSPEC_MASK … #define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE … #define MV88E6165_PTP_CFG_DISABLE_PTP … /* Offset 0x07: PTP Global Configuration */ #define MV88E6341_PTP_CFG … #define MV88E6341_PTP_CFG_UPDATE … #define MV88E6341_PTP_CFG_IDX_MASK … #define MV88E6341_PTP_CFG_DATA_MASK … #define MV88E6341_PTP_CFG_MODE_IDX … #define MV88E6341_PTP_CFG_MODE_TS_AT_PHY … #define MV88E6341_PTP_CFG_MODE_TS_AT_MAC … /* Offset 0x08: PTP Interrupt Status */ #define MV88E6XXX_PTP_IRQ_STATUS … /* Per-Port 6352 PTP Registers */ /* Offset 0x00: PTP Configuration 0 */ #define MV88E6XXX_PORT_PTP_CFG0 … #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT … #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK … #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 … #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS … #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH … #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE … #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP … /* Offset 0x01: PTP Configuration 1 */ #define MV88E6XXX_PORT_PTP_CFG1 … /* Offset 0x02: PTP Configuration 2 */ #define MV88E6XXX_PORT_PTP_CFG2 … #define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL … #define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN … #define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN … /* Offset 0x03: PTP LED Configuration */ #define MV88E6XXX_PORT_PTP_LED_CFG … /* Offset 0x08: PTP Arrival 0 Status */ #define MV88E6XXX_PORT_PTP_ARR0_STS … /* Offset 0x09/0x0A: PTP Arrival 0 Time */ #define MV88E6XXX_PORT_PTP_ARR0_TIME_LO … #define MV88E6XXX_PORT_PTP_ARR0_TIME_HI … /* Offset 0x0B: PTP Arrival 0 Sequence ID */ #define MV88E6XXX_PORT_PTP_ARR0_SEQID … /* Offset 0x0C: PTP Arrival 1 Status */ #define MV88E6XXX_PORT_PTP_ARR1_STS … /* Offset 0x0D/0x0E: PTP Arrival 1 Time */ #define MV88E6XXX_PORT_PTP_ARR1_TIME_LO … #define MV88E6XXX_PORT_PTP_ARR1_TIME_HI … /* Offset 0x0F: PTP Arrival 1 Sequence ID */ #define MV88E6XXX_PORT_PTP_ARR1_SEQID … /* Offset 0x10: PTP Departure Status */ #define MV88E6XXX_PORT_PTP_DEP_STS … /* Offset 0x11/0x12: PTP Deperture Time */ #define MV88E6XXX_PORT_PTP_DEP_TIME_LO … #define MV88E6XXX_PORT_PTP_DEP_TIME_HI … /* Offset 0x13: PTP Departure Sequence ID */ #define MV88E6XXX_PORT_PTP_DEP_SEQID … /* Status fields for arrival and depature timestamp status registers */ #define MV88E6XXX_PTP_TS_STATUS_MASK … #define MV88E6XXX_PTP_TS_STATUS_NORMAL … #define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN … #define MV88E6XXX_PTP_TS_STATUS_DISCARDED … #define MV88E6XXX_PTP_TS_VALID … #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr); int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr); bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, struct sk_buff *clone, unsigned int type); void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, struct sk_buff *skb); int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, struct kernel_ethtool_ts_info *info); int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip); int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port); int mv88e6352_hwtstamp_port_disable(struct mv88e6xxx_chip *chip, int port); int mv88e6165_global_enable(struct mv88e6xxx_chip *chip); int mv88e6165_global_disable(struct mv88e6xxx_chip *chip); #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port, struct ifreq *ifr) { return -EOPNOTSUPP; } static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port, struct ifreq *ifr) { return -EOPNOTSUPP; } static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, struct sk_buff *clone, unsigned int type) { return false; } static inline void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, struct sk_buff *skb) { } static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, struct kernel_ethtool_ts_info *info) { return -EOPNOTSUPP; } static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip) { return 0; } static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip) { } #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ #endif /* _MV88E6XXX_HWTSTAMP_H */
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