/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Marvell 88E6xxx Switch PTP support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2017 National Instruments * Erik Hons <[email protected]> * Brandon Streiff <[email protected]> * Dane Wagner <[email protected]> */ #ifndef _MV88E6XXX_PTP_H #define _MV88E6XXX_PTP_H #include "chip.h" /* Offset 0x00: TAI Global Config */ #define MV88E6XXX_TAI_CFG … #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE … #define MV88E6XXX_TAI_CFG_CAP_CTR_START … #define MV88E6XXX_TAI_CFG_EVREQ_FALLING … #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO … #define MV88E6XXX_TAI_CFG_IRL_ENABLE … #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN … #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN … #define MV88E6XXX_TAI_CFG_TRIG_LOCK … #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE … #define MV88E6XXX_TAI_CFG_MULTI_PTP … #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT … #define MV88E6XXX_TAI_CFG_TRIG_ENABLE … /* Offset 0x01: Timestamp Clock Period (ps) */ #define MV88E6XXX_TAI_CLOCK_PERIOD … /* Offset 0x02/0x03: Trigger Generation Amount */ #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO … #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI … /* Offset 0x04: Clock Compensation */ #define MV88E6XXX_TAI_TRIG_CLOCK_COMP … /* Offset 0x05: Trigger Configuration */ #define MV88E6XXX_TAI_TRIG_CFG … /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ #define MV88E6XXX_TAI_IRL_AMOUNT … /* Offset 0x07: Ingress Rate Limiter Compensation */ #define MV88E6XXX_TAI_IRL_COMP … /* Offset 0x08: Ingress Rate Limiter Compensation */ #define MV88E6XXX_TAI_IRL_COMP_PS … /* Offset 0x09: Event Status */ #define MV88E6XXX_TAI_EVENT_STATUS … #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG … #define MV88E6XXX_TAI_EVENT_STATUS_ERROR … #define MV88E6XXX_TAI_EVENT_STATUS_VALID … #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK … /* Offset 0x0A/0x0B: Event Time */ #define MV88E6XXX_TAI_EVENT_TIME_LO … #define MV88E6XXX_TAI_EVENT_TYPE_HI … /* Offset 0x0E/0x0F: PTP Global Time */ #define MV88E6XXX_TAI_TIME_LO … #define MV88E6XXX_TAI_TIME_HI … /* Offset 0x10/0x11: Trig Generation Time */ #define MV88E6XXX_TAI_TRIG_TIME_LO … #define MV88E6XXX_TAI_TRIG_TIME_HI … /* Offset 0x12: Lock Status */ #define MV88E6XXX_TAI_LOCK_STATUS … /* Offset 0x00: Ether Type */ #define MV88E6XXX_PTP_GC_ETYPE … /* 6165 Global Control Registers */ /* Offset 0x00: Ether Type */ #define MV88E6XXX_PTP_GC_ETYPE … /* Offset 0x01: Message ID */ #define MV88E6XXX_PTP_GC_MESSAGE_ID … /* Offset 0x02: Time Stamp Arrive Time */ #define MV88E6XXX_PTP_GC_TS_ARR_PTR … /* Offset 0x03: Port Arrival Interrupt Enable */ #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN … /* Offset 0x04: Port Departure Interrupt Enable */ #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN … /* Offset 0x05: Configuration */ #define MV88E6XXX_PTP_GC_CONFIG … #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE … #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS … /* Offset 0x8: Interrupt Status */ #define MV88E6XXX_PTP_GC_INT_STATUS … /* Offset 0x9/0xa: Global Time */ #define MV88E6XXX_PTP_GC_TIME_LO … #define MV88E6XXX_PTP_GC_TIME_HI … /* 6165 Per Port Registers */ /* Offset 0: Arrival Time 0 Status */ #define MV88E6165_PORT_PTP_ARR0_STS … /* Offset 0x01/0x02: PTP Arrival 0 Time */ #define MV88E6165_PORT_PTP_ARR0_TIME_LO … #define MV88E6165_PORT_PTP_ARR0_TIME_HI … /* Offset 0x03: PTP Arrival 0 Sequence ID */ #define MV88E6165_PORT_PTP_ARR0_SEQID … /* Offset 0x04: PTP Arrival 1 Status */ #define MV88E6165_PORT_PTP_ARR1_STS … /* Offset 0x05/0x6E: PTP Arrival 1 Time */ #define MV88E6165_PORT_PTP_ARR1_TIME_LO … #define MV88E6165_PORT_PTP_ARR1_TIME_HI … /* Offset 0x07: PTP Arrival 1 Sequence ID */ #define MV88E6165_PORT_PTP_ARR1_SEQID … /* Offset 0x08: PTP Departure Status */ #define MV88E6165_PORT_PTP_DEP_STS … /* Offset 0x09/0x0a: PTP Deperture Time */ #define MV88E6165_PORT_PTP_DEP_TIME_LO … #define MV88E6165_PORT_PTP_DEP_TIME_HI … /* Offset 0x0b: PTP Departure Sequence ID */ #define MV88E6165_PORT_PTP_DEP_SEQID … /* Offset 0x0d: Port Status */ #define MV88E6164_PORT_STATUS … #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp); int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); #define ptp_to_chip(ptp) … extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops; extern const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops; extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops; extern const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops; #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp) { return -1; } static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) { return 0; } static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) { } static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {}; static const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {}; static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {}; static const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops = {}; #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ #endif /* _MV88E6XXX_PTP_H */
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