/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2009 Felix Fietkau <[email protected]> * Copyright (C) 2011-2012 Gabor Juhos <[email protected]> * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ #ifndef __QCA8K_H #define __QCA8K_H #include <linux/delay.h> #include <linux/regmap.h> #include <linux/gpio.h> #include <linux/leds.h> #include <linux/dsa/tag_qca.h> #define QCA8K_ETHERNET_MDIO_PRIORITY … #define QCA8K_ETHERNET_PHY_PRIORITY … #define QCA8K_ETHERNET_TIMEOUT … #define QCA8K_NUM_PORTS … #define QCA8K_NUM_CPU_PORTS … #define QCA8K_MAX_MTU … #define QCA8K_NUM_LAGS … #define QCA8K_NUM_PORTS_FOR_LAG … #define PHY_ID_QCA8327 … #define QCA8K_ID_QCA8327 … #define PHY_ID_QCA8337 … #define QCA8K_ID_QCA8337 … #define QCA8K_QCA832X_MIB_COUNT … #define QCA8K_QCA833X_MIB_COUNT … #define QCA8K_BUSY_WAIT_TIMEOUT … #define QCA8K_NUM_FDB_RECORDS … #define QCA8K_PORT_VID_DEF … /* Global control registers */ #define QCA8K_REG_MASK_CTRL … #define QCA8K_MASK_CTRL_REV_ID_MASK … #define QCA8K_MASK_CTRL_REV_ID(x) … #define QCA8K_MASK_CTRL_DEVICE_ID_MASK … #define QCA8K_MASK_CTRL_DEVICE_ID(x) … #define QCA8K_REG_PORT0_PAD_CTRL … #define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN … #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE … #define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE … #define QCA8K_REG_PORT5_PAD_CTRL … #define QCA8K_REG_PORT6_PAD_CTRL … #define QCA8K_PORT_PAD_RGMII_EN … #define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK … #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) … #define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK … #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) … #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN … #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN … #define QCA8K_PORT_PAD_SGMII_EN … #define QCA8K_REG_PWS … #define QCA8K_PWS_POWER_ON_SEL … /* This reg is only valid for QCA832x and toggle the package * type from 176 pin (by default) to 148 pin used on QCA8327 */ #define QCA8327_PWS_PACKAGE148_EN … #define QCA8K_PWS_LED_OPEN_EN_CSR … #define QCA8K_PWS_SERDES_AEN_DIS … #define QCA8K_REG_MODULE_EN … #define QCA8K_MODULE_EN_MIB … #define QCA8K_REG_MIB … #define QCA8K_MIB_FUNC … #define QCA8K_MIB_CPU_KEEP … #define QCA8K_MIB_BUSY … #define QCA8K_MDIO_MASTER_CTRL … #define QCA8K_MDIO_MASTER_BUSY … #define QCA8K_MDIO_MASTER_EN … #define QCA8K_MDIO_MASTER_READ … #define QCA8K_MDIO_MASTER_WRITE … #define QCA8K_MDIO_MASTER_SUP_PRE … #define QCA8K_MDIO_MASTER_PHY_ADDR_MASK … #define QCA8K_MDIO_MASTER_PHY_ADDR(x) … #define QCA8K_MDIO_MASTER_REG_ADDR_MASK … #define QCA8K_MDIO_MASTER_REG_ADDR(x) … #define QCA8K_MDIO_MASTER_DATA_MASK … #define QCA8K_MDIO_MASTER_DATA(x) … #define QCA8K_MDIO_MASTER_MAX_PORTS … #define QCA8K_MDIO_MASTER_MAX_REG … /* LED control register */ #define QCA8K_LED_PORT_COUNT … #define QCA8K_LED_COUNT … #define QCA8K_LED_RULE_COUNT … #define QCA8K_LED_RULE_MAX … #define QCA8K_LED_PORT_INDEX(_phy, _led) … #define QCA8K_LED_PHY123_PATTERN_EN_SHIFT(_phy, _led) … #define QCA8K_LED_PHY123_PATTERN_EN_MASK … #define QCA8K_LED_PHY0123_CONTROL_RULE_SHIFT … #define QCA8K_LED_PHY4_CONTROL_RULE_SHIFT … #define QCA8K_LED_CTRL_REG(_i) … #define QCA8K_LED_CTRL0_REG … #define QCA8K_LED_CTRL1_REG … #define QCA8K_LED_CTRL2_REG … #define QCA8K_LED_CTRL3_REG … #define QCA8K_LED_CTRL_SHIFT(_i) … #define QCA8K_LED_CTRL_MASK … #define QCA8K_LED_RULE_MASK … #define QCA8K_LED_BLINK_FREQ_MASK … #define QCA8K_LED_BLINK_FREQ_SHITF … #define QCA8K_LED_BLINK_2HZ … #define QCA8K_LED_BLINK_4HZ … #define QCA8K_LED_BLINK_8HZ … #define QCA8K_LED_BLINK_AUTO … #define QCA8K_LED_LINKUP_OVER_MASK … #define QCA8K_LED_TX_BLINK_MASK … #define QCA8K_LED_RX_BLINK_MASK … #define QCA8K_LED_COL_BLINK_MASK … #define QCA8K_LED_LINK_10M_EN_MASK … #define QCA8K_LED_LINK_100M_EN_MASK … #define QCA8K_LED_LINK_1000M_EN_MASK … #define QCA8K_LED_POWER_ON_LIGHT_MASK … #define QCA8K_LED_HALF_DUPLEX_MASK … #define QCA8K_LED_FULL_DUPLEX_MASK … #define QCA8K_LED_PATTERN_EN_MASK … #define QCA8K_LED_PATTERN_EN_SHIFT … #define QCA8K_LED_ALWAYS_OFF … #define QCA8K_LED_ALWAYS_BLINK_4HZ … #define QCA8K_LED_ALWAYS_ON … #define QCA8K_LED_RULE_CONTROLLED … #define QCA8K_GOL_MAC_ADDR0 … #define QCA8K_GOL_MAC_ADDR1 … #define QCA8K_MAX_FRAME_SIZE … #define QCA8K_REG_PORT_STATUS(_i) … #define QCA8K_PORT_STATUS_SPEED … #define QCA8K_PORT_STATUS_SPEED_10 … #define QCA8K_PORT_STATUS_SPEED_100 … #define QCA8K_PORT_STATUS_SPEED_1000 … #define QCA8K_PORT_STATUS_TXMAC … #define QCA8K_PORT_STATUS_RXMAC … #define QCA8K_PORT_STATUS_TXFLOW … #define QCA8K_PORT_STATUS_RXFLOW … #define QCA8K_PORT_STATUS_DUPLEX … #define QCA8K_PORT_STATUS_LINK_UP … #define QCA8K_PORT_STATUS_LINK_AUTO … #define QCA8K_PORT_STATUS_LINK_PAUSE … #define QCA8K_PORT_STATUS_FLOW_AUTO … #define QCA8K_REG_PORT_HDR_CTRL(_i) … #define QCA8K_PORT_HDR_CTRL_RX_MASK … #define QCA8K_PORT_HDR_CTRL_TX_MASK … #define QCA8K_PORT_HDR_CTRL_ALL … #define QCA8K_PORT_HDR_CTRL_MGMT … #define QCA8K_PORT_HDR_CTRL_NONE … #define QCA8K_REG_SGMII_CTRL … #define QCA8K_SGMII_EN_PLL … #define QCA8K_SGMII_EN_RX … #define QCA8K_SGMII_EN_TX … #define QCA8K_SGMII_EN_SD … #define QCA8K_SGMII_CLK125M_DELAY … #define QCA8K_SGMII_MODE_CTRL_MASK … #define QCA8K_SGMII_MODE_CTRL(x) … #define QCA8K_SGMII_MODE_CTRL_BASEX … #define QCA8K_SGMII_MODE_CTRL_PHY … #define QCA8K_SGMII_MODE_CTRL_MAC … /* MAC_PWR_SEL registers */ #define QCA8K_REG_MAC_PWR_SEL … #define QCA8K_MAC_PWR_RGMII1_1_8V … #define QCA8K_MAC_PWR_RGMII0_1_8V … /* EEE control registers */ #define QCA8K_REG_EEE_CTRL … #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) … /* TRUNK_HASH_EN registers */ #define QCA8K_TRUNK_HASH_EN_CTRL … #define QCA8K_TRUNK_HASH_SIP_EN … #define QCA8K_TRUNK_HASH_DIP_EN … #define QCA8K_TRUNK_HASH_SA_EN … #define QCA8K_TRUNK_HASH_DA_EN … #define QCA8K_TRUNK_HASH_MASK … /* ACL registers */ #define QCA8K_REG_PORT_VLAN_CTRL0(_i) … #define QCA8K_PORT_VLAN_CVID_MASK … #define QCA8K_PORT_VLAN_CVID(x) … #define QCA8K_PORT_VLAN_SVID_MASK … #define QCA8K_PORT_VLAN_SVID(x) … #define QCA8K_REG_PORT_VLAN_CTRL1(_i) … #define QCA8K_REG_IPV4_PRI_BASE_ADDR … #define QCA8K_REG_IPV4_PRI_ADDR_MASK … /* Lookup registers */ #define QCA8K_ATU_TABLE_SIZE … #define QCA8K_REG_ATU_DATA0 … #define QCA8K_ATU_ADDR2_MASK … #define QCA8K_ATU_ADDR3_MASK … #define QCA8K_ATU_ADDR4_MASK … #define QCA8K_ATU_ADDR5_MASK … #define QCA8K_REG_ATU_DATA1 … #define QCA8K_ATU_PORT_MASK … #define QCA8K_ATU_ADDR0_MASK … #define QCA8K_ATU_ADDR1_MASK … #define QCA8K_REG_ATU_DATA2 … #define QCA8K_ATU_VID_MASK … #define QCA8K_ATU_STATUS_MASK … #define QCA8K_ATU_STATUS_STATIC … #define QCA8K_REG_ATU_FUNC … #define QCA8K_ATU_FUNC_BUSY … #define QCA8K_ATU_FUNC_PORT_EN … #define QCA8K_ATU_FUNC_MULTI_EN … #define QCA8K_ATU_FUNC_FULL … #define QCA8K_ATU_FUNC_PORT_MASK … #define QCA8K_REG_VTU_FUNC0 … #define QCA8K_VTU_FUNC0_VALID … #define QCA8K_VTU_FUNC0_IVL_EN … /* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4) * It does contain VLAN_MODE for each port [5:4] for port0, * [7:6] for port1 ... [17:16] for port6. Use virtual port * define to handle this. */ #define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) … #define QCA8K_VTU_FUNC0_EG_MODE_MASK … #define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) … #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD … #define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) … #define QCA8K_VTU_FUNC0_EG_MODE_UNTAG … #define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) … #define QCA8K_VTU_FUNC0_EG_MODE_TAG … #define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) … #define QCA8K_VTU_FUNC0_EG_MODE_NOT … #define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) … #define QCA8K_REG_VTU_FUNC1 … #define QCA8K_VTU_FUNC1_BUSY … #define QCA8K_VTU_FUNC1_VID_MASK … #define QCA8K_VTU_FUNC1_FULL … #define QCA8K_REG_ATU_CTRL … #define QCA8K_ATU_AGE_TIME_MASK … #define QCA8K_ATU_AGE_TIME(x) … #define QCA8K_REG_GLOBAL_FW_CTRL0 … #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN … #define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM … #define QCA8K_REG_GLOBAL_FW_CTRL1 … #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK … #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK … #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK … #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK … #define QCA8K_PORT_LOOKUP_CTRL(_i) … #define QCA8K_PORT_LOOKUP_MEMBER … #define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK … #define QCA8K_PORT_LOOKUP_VLAN_MODE(x) … #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE … #define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK … #define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK … #define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE … #define QCA8K_PORT_LOOKUP_STATE_MASK … #define QCA8K_PORT_LOOKUP_STATE(x) … #define QCA8K_PORT_LOOKUP_STATE_DISABLED … #define QCA8K_PORT_LOOKUP_STATE_BLOCKING … #define QCA8K_PORT_LOOKUP_STATE_LISTENING … #define QCA8K_PORT_LOOKUP_STATE_LEARNING … #define QCA8K_PORT_LOOKUP_STATE_FORWARD … #define QCA8K_PORT_LOOKUP_LEARN … #define QCA8K_PORT_LOOKUP_ING_MIRROR_EN … #define QCA8K_REG_GOL_TRUNK_CTRL0 … /* 4 max trunk first * first 6 bit for member bitmap * 7th bit is to enable trunk port */ #define QCA8K_REG_GOL_TRUNK_SHIFT(_i) … #define QCA8K_REG_GOL_TRUNK_EN_MASK … #define QCA8K_REG_GOL_TRUNK_EN(_i) … #define QCA8K_REG_GOL_TRUNK_MEMBER_MASK … #define QCA8K_REG_GOL_TRUNK_MEMBER(_i) … /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */ #define QCA8K_REG_GOL_TRUNK_CTRL(_i) … #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK … #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK … #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK … #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) … #define QCA8K_REG_GOL_MEM_ID_SHIFT(_i) … /* Complex shift: FIRST shift for port THEN shift for trunk */ #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) … #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j) … #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j) … #define QCA8K_REG_GLOBAL_FC_THRESH … #define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK … #define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) … #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK … #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) … #define QCA8K_REG_PORT_HOL_CTRL0(_i) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) … #define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK … #define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) … #define QCA8K_REG_PORT_HOL_CTRL1(_i) … #define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK … #define QCA8K_PORT_HOL_CTRL1_ING(x) … #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN … #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN … #define QCA8K_PORT_HOL_CTRL1_WRED_EN … #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN … /* Pkt edit registers */ #define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) … #define QCA8K_EGREES_VLAN_PORT_MASK(_i) … #define QCA8K_EGREES_VLAN_PORT(_i, x) … #define QCA8K_EGRESS_VLAN(x) … /* L3 registers */ #define QCA8K_HROUTER_CONTROL … #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M … #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S … #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE … #define QCA8K_HROUTER_PBASED_CONTROL1 … #define QCA8K_HROUTER_PBASED_CONTROL2 … #define QCA8K_HNAT_CONTROL … /* MIB registers */ #define QCA8K_PORT_MIB_COUNTER(_i) … /* QCA specific MII registers */ #define MII_ATH_MMD_ADDR … #define MII_ATH_MMD_DATA … enum { … }; enum qca8k_fdb_cmd { … }; enum qca8k_vlan_cmd { … }; enum qca8k_mid_cmd { … }; struct qca8k_priv; struct qca8k_info_ops { … }; struct qca8k_match_data { … }; enum { … }; struct qca8k_mgmt_eth_data { … }; struct qca8k_mib_eth_data { … }; struct qca8k_ports_config { … }; struct qca8k_mdio_cache { … }; struct qca8k_pcs { … }; struct qca8k_led_pattern_en { … }; struct qca8k_led { … }; struct qca8k_priv { … }; struct qca8k_mib_desc { … }; struct qca8k_fdb { … }; static inline u32 qca8k_port_to_phy(int port) { … } /* Common setup function */ extern const struct qca8k_mib_desc ar8327_mib[]; extern const struct regmap_access_table qca8k_readable_table; int qca8k_mib_init(struct qca8k_priv *priv); void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable); int qca8k_read_switch_id(struct qca8k_priv *priv); /* Common read/write/rmw function */ int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val); int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val); int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val); /* Common ops function */ void qca8k_fdb_flush(struct qca8k_priv *priv); /* Common ethtool stats function */ void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data); void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data); int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset); /* Common eee function */ int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *eee); int qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e); /* Common bridge function */ void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); int qca8k_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack); int qca8k_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack); int qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge, bool *tx_fwd_offload, struct netlink_ext_ack *extack); void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge); /* Common port enable/disable function */ int qca8k_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy); void qca8k_port_disable(struct dsa_switch *ds, int port); /* Common MTU function */ int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu); int qca8k_port_max_mtu(struct dsa_switch *ds, int port); /* Common fast age function */ void qca8k_port_fast_age(struct dsa_switch *ds, int port); int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs); /* Common FDB function */ int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, u16 port_mask, u16 vid); int qca8k_port_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db); int qca8k_port_fdb_del(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db); int qca8k_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, void *data); /* Common MDB function */ int qca8k_port_mdb_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_mdb *mdb, struct dsa_db db); int qca8k_port_mdb_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_mdb *mdb, struct dsa_db db); /* Common port mirror function */ int qca8k_port_mirror_add(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror, bool ingress, struct netlink_ext_ack *extack); void qca8k_port_mirror_del(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror); /* Common port VLAN function */ int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack); int qca8k_port_vlan_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack); int qca8k_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan); /* Common port LAG function */ int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag, struct netdev_lag_upper_info *info, struct netlink_ext_ack *extack); int qca8k_port_lag_leave(struct dsa_switch *ds, int port, struct dsa_lag lag); #endif /* __QCA8K_H */
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