/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022 Renesas Electronics Corporation */ #ifndef __MFD_RZ_MTU3_H__ #define __MFD_RZ_MTU3_H__ #include <linux/clk.h> #include <linux/device.h> #include <linux/mutex.h> /* 8-bit shared register offsets macros */ #define RZ_MTU3_TSTRA … #define RZ_MTU3_TSTRB … /* 16-bit shared register offset macros */ #define RZ_MTU3_TDDRA … #define RZ_MTU3_TDDRB … #define RZ_MTU3_TCDRA … #define RZ_MTU3_TCDRB … #define RZ_MTU3_TCBRA … #define RZ_MTU3_TCBRB … #define RZ_MTU3_TCNTSA … #define RZ_MTU3_TCNTSB … /* * MTU5 contains 3 timer counter registers and is totaly different * from other channels, so we must separate its offset */ /* 8-bit register offset macros of MTU3 channels except MTU5 */ #define RZ_MTU3_TIER … #define RZ_MTU3_NFCR … #define RZ_MTU3_TSR … #define RZ_MTU3_TCR … #define RZ_MTU3_TCR2 … /* Timer mode register 1 */ #define RZ_MTU3_TMDR1 … #define RZ_MTU3_TMDR1_MD … #define RZ_MTU3_TMDR1_MD_NORMAL … #define RZ_MTU3_TMDR1_MD_PWMMODE1 … #define RZ_MTU3_TIOR … #define RZ_MTU3_TIORH … #define RZ_MTU3_TIORL … /* Only MTU3/4/6/7 have TBTM registers */ #define RZ_MTU3_TBTM … /* 8-bit MTU5 register offset macros */ #define RZ_MTU3_TSTR … #define RZ_MTU3_TCNTCMPCLR … #define RZ_MTU3_TCRU … #define RZ_MTU3_TCR2U … #define RZ_MTU3_TIORU … #define RZ_MTU3_TCRV … #define RZ_MTU3_TCR2V … #define RZ_MTU3_TIORV … #define RZ_MTU3_TCRW … #define RZ_MTU3_TCR2W … #define RZ_MTU3_TIORW … /* 16-bit register offset macros of MTU3 channels except MTU5 */ #define RZ_MTU3_TCNT … #define RZ_MTU3_TGRA … #define RZ_MTU3_TGRB … #define RZ_MTU3_TGRC … #define RZ_MTU3_TGRD … #define RZ_MTU3_TGRE … #define RZ_MTU3_TGRF … /* Timer A/D converter start request registers */ #define RZ_MTU3_TADCR … #define RZ_MTU3_TADCORA … #define RZ_MTU3_TADCORB … #define RZ_MTU3_TADCOBRA … #define RZ_MTU3_TADCOBRB … /* 16-bit MTU5 register offset macros */ #define RZ_MTU3_TCNTU … #define RZ_MTU3_TGRU … #define RZ_MTU3_TCNTV … #define RZ_MTU3_TGRV … #define RZ_MTU3_TCNTW … #define RZ_MTU3_TGRW … /* 32-bit register offset */ #define RZ_MTU3_TCNTLW … #define RZ_MTU3_TGRALW … #define RZ_MTU3_TGRBLW … #define RZ_MTU3_TMDR3 … /* Macros for setting registers */ #define RZ_MTU3_TCR_CCLR … #define RZ_MTU3_TCR_CKEG … #define RZ_MTU3_TCR_TPCS … #define RZ_MTU3_TCR_CCLR_TGRA … #define RZ_MTU3_TCR_CCLR_TGRC … #define RZ_MTU3_TCR_CKEG_RISING … #define RZ_MTU3_TIOR_IOB … #define RZ_MTU3_TIOR_IOA … #define RZ_MTU3_TIOR_OC_RETAIN … #define RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT … #define RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT … #define RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH … #define RZ_MTU3_TIOR_OC_IOB_TOGGLE … enum rz_mtu3_channels { … }; /** * struct rz_mtu3_channel - MTU3 channel private data * * @dev: device handle * @channel_number: channel number * @lock: Lock to protect channel state * @is_busy: channel state */ struct rz_mtu3_channel { … }; /** * struct rz_mtu3 - MTU3 core private data * * @clk: MTU3 module clock * @rz_mtu3_channel: HW channels * @priv_data: MTU3 core driver private data */ struct rz_mtu3 { … }; static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch) { … } static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch) { … } bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch); void rz_mtu3_disable(struct rz_mtu3_channel *ch); int rz_mtu3_enable(struct rz_mtu3_channel *ch); u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off); u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off); u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off); u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off); void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val); void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val); void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val); void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val); void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off, u16 pos, u8 val); #endif /* __MFD_RZ_MTU3_H__ */
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