/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2017 Sean Wang <[email protected]> */ #ifndef __MT7530_H #define __MT7530_H #define MT7530_NUM_PORTS … #define MT7530_NUM_PHYS … #define MT7530_NUM_FDB_RECORDS … #define MT7530_ALL_MEMBERS … #define MTK_HDR_LEN … #define MT7530_MAX_MTU … enum mt753x_id { … }; #define NUM_TRGMII_CTRL … #define TRGMII_BASE(x) … /* Registers to ethsys access */ #define ETHSYS_CLKCFG0 … #define ETHSYS_TRGMII_CLK_SEL362_5 … #define SYSC_REG_RSTCTRL … #define RESET_MCM … /* Register for ARL global control */ #define MT753X_AGC … #define LOCAL_EN … /* Register for MAC forward control */ #define MT753X_MFC … #define BC_FFP_MASK … #define BC_FFP(x) … #define UNM_FFP_MASK … #define UNM_FFP(x) … #define UNU_FFP_MASK … #define UNU_FFP(x) … #define MT7530_CPU_EN … #define MT7530_CPU_PORT_MASK … #define MT7530_CPU_PORT(x) … #define MT7530_MIRROR_EN … #define MT7530_MIRROR_PORT_MASK … #define MT7530_MIRROR_PORT_GET(x) … #define MT7530_MIRROR_PORT_SET(x) … #define MT7531_QRY_FFP_MASK … #define MT7531_QRY_FFP(x) … /* Register for CPU forward control */ #define MT7531_CFC … #define MT7531_MIRROR_EN … #define MT7531_MIRROR_PORT_MASK … #define MT7531_MIRROR_PORT_GET(x) … #define MT7531_MIRROR_PORT_SET(x) … #define MT7531_CPU_PMAP_MASK … #define MT7531_CPU_PMAP(x) … #define MT753X_MIRROR_REG(id) … #define MT753X_MIRROR_EN(id) … #define MT753X_MIRROR_PORT_MASK(id) … #define MT753X_MIRROR_PORT_GET(id, val) … #define MT753X_MIRROR_PORT_SET(id, val) … /* Register for BPDU and PAE frame control */ #define MT753X_BPC … #define PAE_BPDU_FR … #define PAE_EG_TAG_MASK … #define PAE_EG_TAG(x) … #define PAE_PORT_FW_MASK … #define PAE_PORT_FW(x) … #define BPDU_EG_TAG_MASK … #define BPDU_EG_TAG(x) … #define BPDU_PORT_FW_MASK … /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ #define MT753X_RGAC1 … #define R02_BPDU_FR … #define R02_EG_TAG_MASK … #define R02_EG_TAG(x) … #define R02_PORT_FW_MASK … #define R02_PORT_FW(x) … #define R01_BPDU_FR … #define R01_EG_TAG_MASK … #define R01_EG_TAG(x) … #define R01_PORT_FW_MASK … /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ #define MT753X_RGAC2 … #define R0E_BPDU_FR … #define R0E_EG_TAG_MASK … #define R0E_EG_TAG(x) … #define R0E_PORT_FW_MASK … #define R0E_PORT_FW(x) … #define R03_BPDU_FR … #define R03_EG_TAG_MASK … #define R03_EG_TAG(x) … #define R03_PORT_FW_MASK … enum mt753x_to_cpu_fw { … }; /* Registers for address table access */ #define MT7530_ATA1 … #define STATIC_EMP … #define STATIC_ENT … #define MT7530_ATA2 … #define ATA2_IVL … #define ATA2_FID(x) … /* Register for address table write data */ #define MT7530_ATWD … /* Register for address table control */ #define MT7530_ATC … #define ATC_HASH … #define ATC_BUSY … #define ATC_SRCH_END … #define ATC_SRCH_HIT … #define ATC_INVALID … #define ATC_MAT(x) … #define ATC_MAT_MACTAB … enum mt7530_fdb_cmd { … }; /* Registers for table search read address */ #define MT7530_TSRA1 … #define MAC_BYTE_0 … #define MAC_BYTE_1 … #define MAC_BYTE_2 … #define MAC_BYTE_3 … #define MAC_BYTE_MASK … #define MT7530_TSRA2 … #define MAC_BYTE_4 … #define MAC_BYTE_5 … #define CVID … #define CVID_MASK … #define MT7530_ATRD … #define AGE_TIMER … #define AGE_TIMER_MASK … #define PORT_MAP … #define PORT_MAP_MASK … #define ENT_STATUS … #define ENT_STATUS_MASK … /* Register for vlan table control */ #define MT7530_VTCR … #define VTCR_BUSY … #define VTCR_INVALID … #define VTCR_FUNC(x) … #define VTCR_VID … enum mt7530_vlan_cmd { … }; /* Register for setup vlan and acl write data */ #define MT7530_VAWD1 … #define PORT_STAG … /* Independent VLAN Learning */ #define IVL_MAC … /* Egress Tag Consistent */ #define EG_CON … /* Per VLAN Egress Tag Control */ #define VTAG_EN … /* VLAN Member Control */ #define PORT_MEM(x) … /* Filter ID */ #define FID(x) … /* VLAN Entry Valid */ #define VLAN_VALID … #define PORT_MEM_SHFT … #define PORT_MEM_MASK … enum mt7530_fid { … }; #define MT7530_VAWD2 … /* Egress Tag Control */ #define ETAG_CTRL_P(p, x) … #define ETAG_CTRL_P_MASK(p) … enum mt7530_vlan_egress_attr { … }; /* Register for address age control */ #define MT7530_AAC … /* Disable ageing */ #define AGE_DIS … /* Age count */ #define AGE_CNT_MASK … #define AGE_CNT_MAX … #define AGE_CNT(x) … /* Age unit */ #define AGE_UNIT_MASK … #define AGE_UNIT_MAX … #define AGE_UNIT(x) … /* Register for port STP state control */ #define MT7530_SSP_P(x) … #define FID_PST(fid, state) … #define FID_PST_MASK(fid) … enum mt7530_stp_state { … }; /* Register for port control */ #define MT7530_PCR_P(x) … #define PORT_TX_MIR … #define PORT_RX_MIR … #define PORT_VLAN(x) … enum mt7530_port_mode { … }; #define PCR_MATRIX(x) … #define PORT_PRI(x) … #define EG_TAG(x) … #define PCR_MATRIX_MASK … #define PCR_MATRIX_CLR … #define PCR_PORT_VLAN_MASK … /* Register for port security control */ #define MT7530_PSC_P(x) … #define SA_DIS … /* Register for port vlan control */ #define MT7530_PVC_P(x) … #define PORT_SPEC_TAG … #define PVC_EG_TAG(x) … #define PVC_EG_TAG_MASK … #define VLAN_ATTR(x) … #define VLAN_ATTR_MASK … #define ACC_FRM_MASK … enum mt7530_vlan_port_eg_tag { … }; enum mt7530_vlan_port_attr { … }; enum mt7530_vlan_port_acc_frm { … }; #define STAG_VPID … /* Register for port port-and-protocol based vlan 1 control */ #define MT7530_PPBV1_P(x) … #define G0_PORT_VID(x) … #define G0_PORT_VID_MASK … #define G0_PORT_VID_DEF … /* Register for port MAC control register */ #define MT753X_PMCR_P(x) … #define PMCR_IFG_XMIT_MASK … #define PMCR_IFG_XMIT(x) … #define PMCR_EXT_PHY … #define PMCR_MAC_MODE … #define MT7530_FORCE_MODE … #define PMCR_MAC_TX_EN … #define PMCR_MAC_RX_EN … #define PMCR_BACKOFF_EN … #define PMCR_BACKPR_EN … #define PMCR_FORCE_EEE1G … #define PMCR_FORCE_EEE100 … #define PMCR_FORCE_RX_FC_EN … #define PMCR_FORCE_TX_FC_EN … #define PMCR_FORCE_SPEED_1000 … #define PMCR_FORCE_SPEED_100 … #define PMCR_FORCE_FDX … #define PMCR_FORCE_LNK … #define MT7531_FORCE_MODE_LNK … #define MT7531_FORCE_MODE_SPD … #define MT7531_FORCE_MODE_DPX … #define MT7531_FORCE_MODE_RX_FC … #define MT7531_FORCE_MODE_TX_FC … #define MT7531_FORCE_MODE_EEE100 … #define MT7531_FORCE_MODE_EEE1G … #define MT7531_FORCE_MODE_MASK … #define MT753X_FORCE_MODE(id) … #define PMCR_LINK_SETTINGS_MASK … #define MT753X_PMEEECR_P(x) … #define WAKEUP_TIME_1000_MASK … #define WAKEUP_TIME_1000(x) … #define WAKEUP_TIME_100_MASK … #define WAKEUP_TIME_100(x) … #define LPI_THRESH_MASK … #define LPI_THRESH_GET(x) … #define LPI_THRESH_SET(x) … #define LPI_MODE_EN … #define MT7530_PMSR_P(x) … #define PMSR_EEE1G … #define PMSR_EEE100M … #define PMSR_RX_FC … #define PMSR_TX_FC … #define PMSR_SPEED_1000 … #define PMSR_SPEED_100 … #define PMSR_SPEED_10 … #define PMSR_SPEED_MASK … #define PMSR_DPX … #define PMSR_LINK … /* Register for port debug count */ #define MT7531_DBG_CNT(x) … #define MT7531_DIS_CLR … #define MT7530_GMACCR … #define MAX_RX_JUMBO(x) … #define MAX_RX_JUMBO_MASK … #define MAX_RX_PKT_LEN_MASK … #define MAX_RX_PKT_LEN_1522 … #define MAX_RX_PKT_LEN_1536 … #define MAX_RX_PKT_LEN_1552 … #define MAX_RX_PKT_LEN_JUMBO … /* Register for MIB */ #define MT7530_PORT_MIB_COUNTER(x) … #define MT7530_MIB_CCR … #define CCR_MIB_ENABLE … #define CCR_RX_OCT_CNT_GOOD … #define CCR_RX_OCT_CNT_BAD … #define CCR_TX_OCT_CNT_GOOD … #define CCR_TX_OCT_CNT_BAD … #define CCR_MIB_FLUSH … #define CCR_MIB_ACTIVATE … /* MT7531 SGMII register group */ #define MT7531_SGMII_REG_BASE(p) … #define MT7531_PHYA_CTRL_SIGNAL3 … /* Register for system reset */ #define MT7530_SYS_CTRL … #define SYS_CTRL_PHY_RST … #define SYS_CTRL_SW_RST … #define SYS_CTRL_REG_RST … /* Register for system interrupt */ #define MT7530_SYS_INT_EN … /* Register for system interrupt status */ #define MT7530_SYS_INT_STS … /* Register for PHY Indirect Access Control */ #define MT7531_PHY_IAC … #define MT7531_PHY_ACS_ST … #define MT7531_MDIO_REG_ADDR_MASK … #define MT7531_MDIO_PHY_ADDR_MASK … #define MT7531_MDIO_CMD_MASK … #define MT7531_MDIO_ST_MASK … #define MT7531_MDIO_RW_DATA_MASK … #define MT7531_MDIO_REG_ADDR(x) … #define MT7531_MDIO_DEV_ADDR(x) … #define MT7531_MDIO_PHY_ADDR(x) … #define MT7531_MDIO_CMD(x) … #define MT7531_MDIO_ST(x) … enum mt7531_phy_iac_cmd { … }; /* MDIO_ST: MDIO start field */ enum mt7531_mdio_st { … }; #define MT7531_MDIO_CL22_READ … #define MT7531_MDIO_CL22_WRITE … #define MT7531_MDIO_CL45_ADDR … #define MT7531_MDIO_CL45_READ … #define MT7531_MDIO_CL45_WRITE … /* Register for RGMII clock phase */ #define MT7531_CLKGEN_CTRL … #define CLK_SKEW_OUT(x) … #define CLK_SKEW_OUT_MASK … #define CLK_SKEW_IN(x) … #define CLK_SKEW_IN_MASK … #define RXCLK_NO_DELAY … #define TXCLK_NO_REVERSE … #define GP_MODE(x) … #define GP_MODE_MASK … #define GP_CLK_EN … enum mt7531_gp_mode { … }; enum mt7531_clk_skew { … }; /* Register for trap status */ #define MT753X_TRAP … #define MT7530_XTAL_MASK … #define MT7530_XTAL_25MHZ … #define MT7530_XTAL_40MHZ … #define MT7530_XTAL_20MHZ … #define MT7531_XTAL25 … /* Register for trap modification */ #define MT753X_MTRAP … #define MT7530_P5_PHY0_SEL … #define MT7530_CHG_TRAP … #define MT7530_P5_MAC_SEL … #define MT7530_P6_DIS … #define MT7530_P5_RGMII_MODE … #define MT7530_P5_DIS … #define MT7530_PHY_INDIRECT_ACCESS … #define MT7531_CHG_STRAP … #define MT7531_PHY_EN … enum mt7531_xtal_fsel { … }; /* Register for TOP signal control */ #define MT7530_TOP_SIG_CTRL … #define TOP_SIG_CTRL_NORMAL … #define MT7531_TOP_SIG_SR … #define PAD_DUAL_SGMII_EN … #define PAD_MCM_SMI_EN … #define MT7530_IO_DRV_CR … #define P5_IO_CLK_DRV(x) … #define P5_IO_DATA_DRV(x) … #define MT7531_CHIP_REV … #define MT7531_PLLGP_EN … #define EN_COREPLL … #define SW_CLKSW … #define SW_PLLGP … #define MT7530_P6ECR … #define P6_INTF_MODE_MASK … #define P6_INTF_MODE(x) … #define MT7531_PLLGP_CR0 … #define RG_COREPLL_EN … #define RG_COREPLL_POSDIV_S … #define RG_COREPLL_POSDIV_M … #define RG_COREPLL_SDM_PCW_S … #define RG_COREPLL_SDM_PCW_M … #define RG_COREPLL_SDM_PCW_CHG … /* Registers for RGMII and SGMII PLL clock */ #define MT7531_ANA_PLLGP_CR2 … #define MT7531_ANA_PLLGP_CR5 … /* Registers for TRGMII on the both side */ #define MT7530_TRGMII_RCK_CTRL … #define RX_RST … #define RXC_DQSISEL … #define DQSI1_TAP_MASK … #define DQSI0_TAP_MASK … #define DQSI1_TAP(x) … #define DQSI0_TAP(x) … #define MT7530_TRGMII_RCK_RTT … #define DQS1_GATE … #define DQS0_GATE … #define MT7530_TRGMII_RD(x) … #define BSLIP_EN … #define EDGE_CHK … #define RD_TAP_MASK … #define RD_TAP(x) … #define MT7530_TRGMII_TXCTRL … #define TRAIN_TXEN … #define TXC_INV … #define TX_RST … #define MT7530_TRGMII_TD_ODT(i) … #define TD_DM_DRVP(x) … #define TD_DM_DRVN(x) … #define MT7530_TRGMII_TCK_CTRL … #define TCK_TAP(x) … #define MT7530_P5RGMIIRXCR … #define CSR_RGMII_EDGE_ALIGN … #define CSR_RGMII_RXC_0DEG_CFG(x) … #define MT7530_P5RGMIITXCR … #define CSR_RGMII_TXC_CFG(x) … /* Registers for GPIO mode */ #define MT7531_GPIO_MODE0 … #define MT7531_GPIO0_MASK … #define MT7531_GPIO0_INTERRUPT … #define MT7531_GPIO_MODE1 … #define MT7531_GPIO11_RG_RXD2_MASK … #define MT7531_EXT_P_MDC_11 … #define MT7531_GPIO12_RG_RXD3_MASK … #define MT7531_EXT_P_MDIO_12 … /* Registers for LED GPIO control (MT7530 only) * All registers follow this pattern: * [ 2: 0] port 0 * [ 6: 4] port 1 * [10: 8] port 2 * [14:12] port 3 * [18:16] port 4 */ /* LED enable, 0: Disable, 1: Enable (Default) */ #define MT7530_LED_EN … /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ #define MT7530_LED_IO_MODE … /* GPIO direction, 0: Input, 1: Output */ #define MT7530_LED_GPIO_DIR … /* GPIO output enable, 0: Disable, 1: Enable */ #define MT7530_LED_GPIO_OE … /* GPIO value, 0: Low, 1: High */ #define MT7530_LED_GPIO_DATA … #define MT7530_CREV … #define CHIP_NAME_SHIFT … #define MT7530_ID … #define MT7531_CREV … #define CHIP_REV_M … #define MT7531_ID … /* Registers for core PLL access through mmd indirect */ #define CORE_PLL_GROUP2 … #define RG_SYSPLL_EN_NORMAL … #define RG_SYSPLL_VODEN … #define RG_SYSPLL_LF … #define RG_SYSPLL_RST_DLY(x) … #define RG_SYSPLL_LVROD_EN … #define RG_SYSPLL_PREDIV(x) … #define RG_SYSPLL_POSDIV(x) … #define RG_SYSPLL_FBKSEL … #define RT_SYSPLL_EN_AFE_OLT … #define CORE_PLL_GROUP4 … #define RG_SYSPLL_DDSFBK_EN … #define RG_SYSPLL_BIAS_EN … #define RG_SYSPLL_BIAS_LPF_EN … #define MT7531_RG_SYSPLL_DMY2 … #define MT7531_PHY_PLL_OFF … #define MT7531_PHY_PLL_BYPASS_MODE … #define MT753X_CTRL_PHY_ADDR(addr) … #define CORE_PLL_GROUP5 … #define RG_LCDDS_PCW_NCPO1(x) … #define CORE_PLL_GROUP6 … #define RG_LCDDS_PCW_NCPO0(x) … #define CORE_PLL_GROUP7 … #define RG_LCDDS_PWDB … #define RG_LCDDS_ISO_EN … #define RG_LCCDS_C(x) … #define RG_LCDDS_PCW_NCPO_CHG … #define CORE_PLL_GROUP10 … #define RG_LCDDS_SSC_DELTA(x) … #define CORE_PLL_GROUP11 … #define RG_LCDDS_SSC_DELTA1(x) … #define CORE_GSWPLL_GRP1 … #define RG_GSWPLL_PREDIV(x) … #define RG_GSWPLL_POSDIV_200M(x) … #define RG_GSWPLL_EN_PRE … #define RG_GSWPLL_FBKSEL … #define RG_GSWPLL_BP … #define RG_GSWPLL_BR … #define RG_GSWPLL_FBKDIV_200M(x) … #define CORE_GSWPLL_GRP2 … #define RG_GSWPLL_POSDIV_500M(x) … #define RG_GSWPLL_FBKDIV_500M(x) … #define CORE_TRGMII_GSW_CLK_CG … #define REG_GSWCK_EN … #define REG_TRGMIICK_EN … #define MIB_DESC(_s, _o, _n) … struct mt7530_mib_desc { … }; struct mt7530_fdb { … }; /* struct mt7530_port - This is the main data structure for holding the state * of the port. * @enable: The status used for show port is enabled or not. * @pm: The matrix used to show all connections with the port. * @pvid: The VLAN specified is to be considered a PVID at ingress. Any * untagged frames will be assigned to the related VLAN. * @sgmii_pcs: Pointer to PCS instance for SerDes ports */ struct mt7530_port { … }; /* Port 5 mode definitions of the MT7530 switch */ enum mt7530_p5_mode { … }; struct mt7530_priv; struct mt753x_pcs { … }; /* struct mt753x_info - This is the main data structure for holding the specific * part for each supported device * @id: Holding the identifier to a switch model * @pcs_ops: Holding the pointer to the MAC PCS operations structure * @sw_setup: Holding the handler to a device initialization * @phy_read_c22: Holding the way reading PHY port using C22 * @phy_write_c22: Holding the way writing PHY port using C22 * @phy_read_c45: Holding the way reading PHY port using C45 * @phy_write_c45: Holding the way writing PHY port using C45 * @mac_port_get_caps: Holding the handler that provides MAC capabilities * @mac_port_config: Holding the way setting up the PHY attribute to a * certain MAC port */ struct mt753x_info { … }; /* struct mt7530_priv - This is the main data structure for holding the state * of the driver * @dev: The device pointer * @ds: The pointer to the dsa core structure * @bus: The bus used for the device and built-in PHY * @regmap: The regmap instance representing all switch registers * @rstc: The pointer to reset control used by MCM * @core_pwr: The power supplied into the core * @io_pwr: The power supplied into the I/O * @reset: The descriptor for GPIO line tied to its reset pin * @mcm: Flag for distinguishing if standalone IC or module * coupling * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers * @p5_mode: Holding the current mode of port 5 of the MT7530 switch * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) * @active_cpu_ports: Holding the active CPU ports * @mdiodev: The pointer to the MDIO device structure */ struct mt7530_priv { … }; struct mt7530_hw_vlan_entry { … }; static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, int port, bool untagged) { … } mt7530_vlan_op; struct mt7530_hw_stats { … }; struct mt7530_dummy_poll { … }; static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, struct mt7530_priv *priv, u32 reg) { … } int mt7530_probe_common(struct mt7530_priv *priv); void mt7530_remove_common(struct mt7530_priv *priv); extern const struct dsa_switch_ops mt7530_switch_ops; extern const struct mt753x_info mt753x_table[]; #endif /* __MT7530_H */
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