// SPDX-License-Identifier: GPL-2.0 /* DSA driver for: * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch * * These switches have a built-in 8051 CPU and can download and execute a * firmware in this CPU. They can also be configured to use an external CPU * handling the switch in a memory-mapped manner by connecting to that external * CPU's memory bus. * * Copyright (C) 2018 Linus Wallej <[email protected]> * Includes portions of code from the firmware uploader by: * Copyright (C) 2009 Gabor Juhos <[email protected]> */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/device.h> #include <linux/iopoll.h> #include <linux/of.h> #include <linux/of_mdio.h> #include <linux/bitops.h> #include <linux/bitfield.h> #include <linux/if_bridge.h> #include <linux/if_vlan.h> #include <linux/etherdevice.h> #include <linux/gpio/consumer.h> #include <linux/gpio/driver.h> #include <linux/dsa/8021q.h> #include <linux/random.h> #include <net/dsa.h> #include "vitesse-vsc73xx.h" #define VSC73XX_BLOCK_MAC … #define VSC73XX_BLOCK_ANALYZER … #define VSC73XX_BLOCK_MII … #define VSC73XX_BLOCK_MEMINIT … #define VSC73XX_BLOCK_CAPTURE … #define VSC73XX_BLOCK_ARBITER … #define VSC73XX_BLOCK_SYSTEM … /* MII Block subblock */ #define VSC73XX_BLOCK_MII_INTERNAL … #define VSC73XX_BLOCK_MII_EXTERNAL … #define CPU_PORT … #define VSC73XX_NUM_FDB_ROWS … #define VSC73XX_NUM_BUCKETS … /* MAC Block registers */ #define VSC73XX_MAC_CFG … #define VSC73XX_MACHDXGAP … #define VSC73XX_FCCONF … #define VSC73XX_FCMACHI … #define VSC73XX_FCMACLO … #define VSC73XX_MAXLEN … #define VSC73XX_ADVPORTM … #define VSC73XX_TXUPDCFG … #define VSC73XX_TXQ_SELECT_CFG … #define VSC73XX_RXOCT … #define VSC73XX_TXOCT … #define VSC73XX_C_RX0 … #define VSC73XX_C_RX1 … #define VSC73XX_C_RX2 … #define VSC73XX_C_TX0 … #define VSC73XX_C_TX1 … #define VSC73XX_C_TX2 … #define VSC73XX_C_CFG … #define VSC73XX_CAT_DROP … #define VSC73XX_CAT_PR_MISC_L2 … #define VSC73XX_CAT_PR_USR_PRIO … #define VSC73XX_CAT_VLAN_MISC … #define VSC73XX_CAT_PORT_VLAN … #define VSC73XX_Q_MISC_CONF … /* MAC_CFG register bits */ #define VSC73XX_MAC_CFG_WEXC_DIS … #define VSC73XX_MAC_CFG_PORT_RST … #define VSC73XX_MAC_CFG_TX_EN … #define VSC73XX_MAC_CFG_SEED_LOAD … #define VSC73XX_MAC_CFG_SEED_MASK … #define VSC73XX_MAC_CFG_SEED_OFFSET … #define VSC73XX_MAC_CFG_FDX … #define VSC73XX_MAC_CFG_GIGA_MODE … #define VSC73XX_MAC_CFG_RX_EN … #define VSC73XX_MAC_CFG_VLAN_DBLAWR … #define VSC73XX_MAC_CFG_VLAN_AWR … #define VSC73XX_MAC_CFG_100_BASE_T … #define VSC73XX_MAC_CFG_TX_IPG_MASK … #define VSC73XX_MAC_CFG_TX_IPG_OFFSET … #define VSC73XX_MAC_CFG_TX_IPG_1000M … #define VSC73XX_MAC_CFG_TX_IPG_100_10M … #define VSC73XX_MAC_CFG_MAC_RX_RST … #define VSC73XX_MAC_CFG_MAC_TX_RST … #define VSC73XX_MAC_CFG_CLK_SEL_MASK … #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET … #define VSC73XX_MAC_CFG_CLK_SEL_1000M … #define VSC73XX_MAC_CFG_CLK_SEL_100M … #define VSC73XX_MAC_CFG_CLK_SEL_10M … #define VSC73XX_MAC_CFG_CLK_SEL_EXT … #define VSC73XX_MAC_CFG_1000M_F_PHY … #define VSC73XX_MAC_CFG_100_10M_F_PHY … #define VSC73XX_MAC_CFG_100_10M_H_PHY … #define VSC73XX_MAC_CFG_1000M_F_RGMII … #define VSC73XX_MAC_CFG_RESET … /* Flow control register bits */ #define VSC73XX_FCCONF_ZERO_PAUSE_EN … #define VSC73XX_FCCONF_FLOW_CTRL_OBEY … #define VSC73XX_FCCONF_PAUSE_VAL_MASK … /* ADVPORTM advanced port setup register bits */ #define VSC73XX_ADVPORTM_IFG_PPM … #define VSC73XX_ADVPORTM_EXC_COL_CONT … #define VSC73XX_ADVPORTM_EXT_PORT … #define VSC73XX_ADVPORTM_INV_GTX … #define VSC73XX_ADVPORTM_ENA_GTX … #define VSC73XX_ADVPORTM_DDR_MODE … #define VSC73XX_ADVPORTM_IO_LOOPBACK … #define VSC73XX_ADVPORTM_HOST_LOOPBACK … /* TXUPDCFG transmit modify setup bits */ #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE … #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA … #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA … #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID … #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA … #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA … #define VSC73XX_TXUPDCFG_TX_INSERT_TAG … #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT … /* CAT_DROP categorizer frame dropping register bits */ #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA … #define VSC73XX_CAT_DROP_FWD_CTRL_ENA … #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA … #define VSC73XX_CAT_DROP_UNTAGGED_ENA … #define VSC73XX_CAT_DROP_TAGGED_ENA … #define VSC73XX_CAT_DROP_NULL_MAC_ENA … #define VSC73XX_Q_MISC_CONF_EXTENT_MEM … #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK … #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 … #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE … /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA … #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA … /* CAT_PORT_VLAN categorizer port VLAN */ #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI … #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO … #define VSC73XX_CAT_PORT_VLAN_VLAN_VID … /* Frame analyzer block 2 registers */ #define VSC73XX_STORMLIMIT … #define VSC73XX_ADVLEARN … #define VSC73XX_IFLODMSK … #define VSC73XX_VLANMASK … #define VSC73XX_MACHDATA … #define VSC73XX_MACLDATA … #define VSC73XX_ANMOVED … #define VSC73XX_ANAGEFIL … #define VSC73XX_ANEVENTS … #define VSC73XX_ANCNTMASK … #define VSC73XX_ANCNTVAL … #define VSC73XX_LEARNMASK … #define VSC73XX_UFLODMASK … #define VSC73XX_MFLODMASK … #define VSC73XX_RECVMASK … #define VSC73XX_AGGRCTRL … #define VSC73XX_AGGRMSKS … #define VSC73XX_DSTMASKS … #define VSC73XX_SRCMASKS … #define VSC73XX_CAPENAB … #define VSC73XX_MACACCESS … #define VSC73XX_IPMCACCESS … #define VSC73XX_MACTINDX … #define VSC73XX_VLANACCESS … #define VSC73XX_VLANTIDX … #define VSC73XX_AGENCTRL … #define VSC73XX_CAPRST … #define VSC73XX_SRCMASKS_CPU_COPY … #define VSC73XX_SRCMASKS_MIRROR … #define VSC73XX_SRCMASKS_PORTS_MASK … #define VSC73XX_MACHDATA_VID … #define VSC73XX_MACHDATA_MAC0 … #define VSC73XX_MACHDATA_MAC1 … #define VSC73XX_MACLDATA_MAC2 … #define VSC73XX_MACLDATA_MAC3 … #define VSC73XX_MACLDATA_MAC4 … #define VSC73XX_MACLDATA_MAC5 … #define VSC73XX_HASH0_VID_FROM_MASK … #define VSC73XX_HASH0_MAC0_FROM_MASK … #define VSC73XX_HASH1_MAC0_FROM_MASK … #define VSC73XX_HASH1_MAC1_FROM_MASK … #define VSC73XX_HASH2_MAC1_FROM_MASK … #define VSC73XX_HASH2_MAC2_FROM_MASK … #define VSC73XX_HASH2_MAC3_FROM_MASK … #define VSC73XX_HASH3_MAC3_FROM_MASK … #define VSC73XX_HASH3_MAC4_FROM_MASK … #define VSC73XX_HASH4_MAC4_FROM_MASK … #define VSC73XX_HASH0_VID_TO_MASK … #define VSC73XX_HASH0_MAC0_TO_MASK … #define VSC73XX_HASH1_MAC0_TO_MASK … #define VSC73XX_HASH1_MAC1_TO_MASK … #define VSC73XX_HASH2_MAC1_TO_MASK … #define VSC73XX_HASH2_MAC2_TO_MASK … #define VSC73XX_HASH2_MAC3_TO_MASK … #define VSC73XX_HASH3_MAC3_TO_MASK … #define VSC73XX_HASH3_MAC4_TO_MASK … #define VSC73XX_HASH4_MAC4_TO_MASK … #define VSC73XX_MACTINDX_SHADOW … #define VSC73XX_MACTINDX_BUCKET_MSK … #define VSC73XX_MACTINDX_INDEX_MSK … #define VSC73XX_MACACCESS_CPU_COPY … #define VSC73XX_MACACCESS_FWD_KILL … #define VSC73XX_MACACCESS_IGNORE_VLAN … #define VSC73XX_MACACCESS_AGED_FLAG … #define VSC73XX_MACACCESS_VALID … #define VSC73XX_MACACCESS_LOCKED … #define VSC73XX_MACACCESS_DEST_IDX_MASK … #define VSC73XX_MACACCESS_CMD_MASK … #define VSC73XX_MACACCESS_CMD_IDLE … #define VSC73XX_MACACCESS_CMD_LEARN … #define VSC73XX_MACACCESS_CMD_FORGET … #define VSC73XX_MACACCESS_CMD_AGE_TABLE … #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE … #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE … #define VSC73XX_MACACCESS_CMD_READ_ENTRY … #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY … #define VSC73XX_VLANACCESS_LEARN_DISABLED … #define VSC73XX_VLANACCESS_VLAN_MIRROR … #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK … #define VSC73XX_VLANACCESS_VLAN_PORT_MASK … #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT … #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK … #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE … #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY … #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY … #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE … /* MII block 3 registers */ #define VSC73XX_MII_STAT … #define VSC73XX_MII_CMD … #define VSC73XX_MII_DATA … #define VSC73XX_MII_MPRES … #define VSC73XX_MII_STAT_BUSY … #define VSC73XX_MII_STAT_READ … #define VSC73XX_MII_STAT_WRITE … #define VSC73XX_MII_CMD_SCAN … #define VSC73XX_MII_CMD_OPERATION … #define VSC73XX_MII_CMD_PHY_ADDR … #define VSC73XX_MII_CMD_PHY_REG … #define VSC73XX_MII_CMD_WRITE_DATA … #define VSC73XX_MII_DATA_FAILURE … #define VSC73XX_MII_DATA_READ_DATA … #define VSC73XX_MII_MPRES_NOPREAMBLE … #define VSC73XX_MII_MPRES_PRESCALEVAL … #define VSC73XX_MII_PRESCALEVAL_MIN … #define VSC73XX_MII_STAT_BUSY … /* Arbiter block 5 registers */ #define VSC73XX_ARBEMPTY … #define VSC73XX_ARBDISC … #define VSC73XX_SBACKWDROP … #define VSC73XX_DBACKWDROP … #define VSC73XX_ARBBURSTPROB … /* System block 7 registers */ #define VSC73XX_ICPU_SIPAD … #define VSC73XX_GMIIDELAY … #define VSC73XX_ICPU_CTRL … #define VSC73XX_ICPU_ADDR … #define VSC73XX_ICPU_SRAM … #define VSC73XX_HWSEM … #define VSC73XX_GLORESET … #define VSC73XX_ICPU_MBOX_VAL … #define VSC73XX_ICPU_MBOX_SET … #define VSC73XX_ICPU_MBOX_CLR … #define VSC73XX_CHIPID … #define VSC73XX_GPIO … #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE … #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS … #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS … #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS … #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE … #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS … #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS … #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS … #define VSC73XX_ICPU_CTRL_WATCHDOG_RST … #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK … #define VSC73XX_ICPU_CTRL_SRST_HOLD … #define VSC73XX_ICPU_CTRL_ICPU_PI_EN … #define VSC73XX_ICPU_CTRL_BOOT_EN … #define VSC73XX_ICPU_CTRL_EXT_ACC_EN … #define VSC73XX_ICPU_CTRL_CLK_EN … #define VSC73XX_ICPU_CTRL_SRST … #define VSC73XX_CHIPID_ID_SHIFT … #define VSC73XX_CHIPID_ID_MASK … #define VSC73XX_CHIPID_REV_SHIFT … #define VSC73XX_CHIPID_REV_MASK … #define VSC73XX_CHIPID_ID_7385 … #define VSC73XX_CHIPID_ID_7388 … #define VSC73XX_CHIPID_ID_7395 … #define VSC73XX_CHIPID_ID_7398 … #define VSC73XX_GLORESET_STROBE … #define VSC73XX_GLORESET_ICPU_LOCK … #define VSC73XX_GLORESET_MEM_LOCK … #define VSC73XX_GLORESET_PHY_RESET … #define VSC73XX_GLORESET_MASTER_RESET … #define VSC7385_CLOCK_DELAY … #define VSC7385_CLOCK_DELAY_MASK … #define VSC73XX_ICPU_CTRL_STOP … #define VSC73XX_ICPU_CTRL_START … #define IS_7385(a) … #define IS_7388(a) … #define IS_7395(a) … #define IS_7398(a) … #define IS_739X(a) … #define VSC73XX_POLL_SLEEP_US … #define VSC73XX_MDIO_POLL_SLEEP_US … #define VSC73XX_POLL_TIMEOUT_US … struct vsc73xx_counter { … }; struct vsc73xx_fdb { … }; /* Counters are named according to the MIB standards where applicable. * Some counters are custom, non-standard. The standard counters are * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex * 30A Counters. */ static const struct vsc73xx_counter vsc73xx_rx_counters[] = …; static const struct vsc73xx_counter vsc73xx_tx_counters[] = …; struct vsc73xx_vlan_summary { … }; enum vsc73xx_port_vlan_conf { … }; int vsc73xx_is_addr_valid(u8 block, u8 subblock) { … } EXPORT_SYMBOL(…); static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, u32 *val) { … } static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, u32 val) { … } static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, u32 mask, u32 val) { … } static int vsc73xx_detect(struct vsc73xx *vsc) { … } static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) { … } static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) { … } static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val) { … } static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { … } static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) { … } static int vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) { … } static int vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) { … } static int vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) { … } static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds) { … } static int vsc73xx_setup(struct dsa_switch *ds) { … } static void vsc73xx_teardown(struct dsa_switch *ds) { … } static void vsc73xx_init_port(struct vsc73xx *vsc, int port) { … } static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) { … } static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, const struct phylink_link_state *state) { … } static void vsc73xx_mac_link_down(struct phylink_config *config, unsigned int mode, phy_interface_t interface) { … } static void vsc73xx_mac_link_up(struct phylink_config *config, struct phy_device *phy, unsigned int mode, phy_interface_t interface, int speed, int duplex, bool tx_pause, bool rx_pause) { … } static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) { … } static struct vsc73xx_bridge_vlan * vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) { … } static void vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, int port) { … } static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, struct vsc73xx_vlan_summary *summary, u16 ignored_vid) { … } static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) { … } static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, enum vsc73xx_port_vlan_conf port_vlan_conf) { … } /** * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port * @vsc: Switch private data structure * @port: Port index on which to operate * * Update the VLAN behavior of a port to make sure that when it is under * a VLAN filtering bridge, the port is either filtering with tag * preservation, or filtering with all VLANs egress-untagged. Otherwise, * the port ignores VLAN tags from packets and applies the port-based * VID. * * Must be called when changes are made to: * - the bridge VLAN filtering state of the port * - the number or attributes of VLANs from the bridge VLAN table, * while the port is currently VLAN-aware * * Return: 0 on success, or negative errno on error. */ static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) { … } static int vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) { … } /** * vsc73xx_vlan_commit_untagged - Update native VLAN of a port * @vsc: Switch private data structure * @port: Port index on which to operate * * Update the native VLAN of a port (the one VLAN which is transmitted * as egress-tagged on a trunk port) when port is in VLAN filtering mode and * only one untagged vid is configured. * In other cases no need to configure it because switch can untag all vlans on * the port. * * Return: 0 on success, or negative errno on error. */ static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) { … } static int vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) { … } /** * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port * @vsc: Switch private data structure * @port: Port index on which to operate * * Update the PVID of a port so that it follows either the bridge PVID * configuration, when the bridge is currently VLAN-aware, or the PVID * from tag_8021q, when the port is standalone or under a VLAN-unaware * bridge. A port with no PVID drops all untagged and VID 0 tagged * traffic. * * Must be called when changes are made to: * - the bridge VLAN filtering state of the port * - the number or attributes of VLANs from the bridge VLAN table, * while the port is currently VLAN-aware * * Return: 0 on success, or negative errno on error. */ static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) { … } static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) { … } static int vsc73xx_port_enable(struct dsa_switch *ds, int port, struct phy_device *phy) { … } static void vsc73xx_port_disable(struct dsa_switch *ds, int port) { … } static const struct vsc73xx_counter * vsc73xx_find_counter(struct vsc73xx *vsc, u8 counter, bool tx) { … } static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) { … } static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) { … } static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) { … } static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { … } /* According to application not "VSC7398 Jumbo Frames" setting * up the frame size to 9.6 KB does not affect the performance on standard * frames. It is clear from the application note that * "9.6 kilobytes" == 9600 bytes. */ static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) { … } static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, struct phylink_config *config) { … } static int vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, struct netlink_ext_ack *extack) { … } static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, struct netlink_ext_ack *extack) { … } static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { … } static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, u16 flags) { … } static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) { … } static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack) { … } static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack) { … } static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) { … } /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are * forwarded only from and to PI/SI interface. For more info see chapter * 2.7.1 (CPU Forwarding) in datasheet. * This function is required for tag_8021q operations. */ static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) { … } static u16 vsc73xx_calc_hash(const unsigned char *addr, u16 vid) { … } static int vsc73xx_port_wait_for_mac_table_cmd(struct vsc73xx *vsc) { … } static int vsc73xx_port_read_mac_table_row(struct vsc73xx *vsc, u16 index, struct vsc73xx_fdb *fdb) { … } static int vsc73xx_fdb_operation(struct vsc73xx *vsc, const unsigned char *addr, u16 vid, u16 hash, u16 cmd_mask, u16 cmd_val) { … } static int vsc73xx_fdb_del_entry(struct vsc73xx *vsc, int port, const unsigned char *addr, u16 vid) { … } static int vsc73xx_fdb_add_entry(struct vsc73xx *vsc, int port, const unsigned char *addr, u16 vid) { … } static int vsc73xx_fdb_add(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db) { … } static int vsc73xx_fdb_del(struct dsa_switch *ds, int port, const unsigned char *addr, u16 vid, struct dsa_db db) { … } static int vsc73xx_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, void *data) { … } static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = …; static const struct dsa_switch_ops vsc73xx_ds_ops = …; static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) { … } static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) { … } static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) { … } static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { … } static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { … } static int vsc73xx_gpio_probe(struct vsc73xx *vsc) { … } int vsc73xx_probe(struct vsc73xx *vsc) { … } EXPORT_SYMBOL(…); void vsc73xx_remove(struct vsc73xx *vsc) { … } EXPORT_SYMBOL(…); void vsc73xx_shutdown(struct vsc73xx *vsc) { … } EXPORT_SYMBOL(…); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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