/* * AMD 10Gb Ethernet driver * * This file is available to you under your choice of the following two * licenses: * * License 1: GPLv2 * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * * This file is free software; you may copy, redistribute and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, either version 2 of the License, or (at * your option) any later version. * * This file is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * * License 2: Modified BSD * * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This file incorporates work covered by the following copyright and * permission notice: * The Synopsys DWC ETHER XGMAC Software Driver and documentation * (hereinafter "Software") is an unsupported proprietary work of Synopsys, * Inc. unless otherwise expressly agreed to in writing between Synopsys * and you. * * The Software IS NOT an item of Licensed Software or Licensed Product * under any End User Software License Agreement or Agreement for Licensed * Product with Synopsys or any supplement thereto. Permission is hereby * granted, free of charge, to any person obtaining a copy of this software * annotated with this license and the Software, to deal in the Software * without restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __XGBE_COMMON_H__ #define __XGBE_COMMON_H__ /* DMA register offsets */ #define DMA_MR … #define DMA_SBMR … #define DMA_ISR … #define DMA_AXIARCR … #define DMA_AXIAWCR … #define DMA_AXIAWARCR … #define DMA_DSR0 … #define DMA_DSR1 … #define DMA_TXEDMACR … #define DMA_RXEDMACR … /* DMA register entry bit positions and sizes */ #define DMA_ISR_MACIS_INDEX … #define DMA_ISR_MACIS_WIDTH … #define DMA_ISR_MTLIS_INDEX … #define DMA_ISR_MTLIS_WIDTH … #define DMA_MR_INTM_INDEX … #define DMA_MR_INTM_WIDTH … #define DMA_MR_SWR_INDEX … #define DMA_MR_SWR_WIDTH … #define DMA_RXEDMACR_RDPS_INDEX … #define DMA_RXEDMACR_RDPS_WIDTH … #define DMA_SBMR_AAL_INDEX … #define DMA_SBMR_AAL_WIDTH … #define DMA_SBMR_EAME_INDEX … #define DMA_SBMR_EAME_WIDTH … #define DMA_SBMR_BLEN_INDEX … #define DMA_SBMR_BLEN_WIDTH … #define DMA_SBMR_RD_OSR_LMT_INDEX … #define DMA_SBMR_RD_OSR_LMT_WIDTH … #define DMA_SBMR_UNDEF_INDEX … #define DMA_SBMR_UNDEF_WIDTH … #define DMA_SBMR_WR_OSR_LMT_INDEX … #define DMA_SBMR_WR_OSR_LMT_WIDTH … #define DMA_TXEDMACR_TDPS_INDEX … #define DMA_TXEDMACR_TDPS_WIDTH … /* DMA register values */ #define DMA_SBMR_BLEN_256 … #define DMA_SBMR_BLEN_128 … #define DMA_SBMR_BLEN_64 … #define DMA_SBMR_BLEN_32 … #define DMA_SBMR_BLEN_16 … #define DMA_SBMR_BLEN_8 … #define DMA_SBMR_BLEN_4 … #define DMA_DSR_RPS_WIDTH … #define DMA_DSR_TPS_WIDTH … #define DMA_DSR_Q_WIDTH … #define DMA_DSR0_RPS_START … #define DMA_DSR0_TPS_START … #define DMA_DSRX_FIRST_QUEUE … #define DMA_DSRX_INC … #define DMA_DSRX_QPR … #define DMA_DSRX_RPS_START … #define DMA_DSRX_TPS_START … #define DMA_TPS_STOPPED … #define DMA_TPS_SUSPENDED … /* DMA channel register offsets * Multiple channels can be active. The first channel has registers * that begin at 0x3100. Each subsequent channel has registers that * are accessed using an offset of 0x80 from the previous channel. */ #define DMA_CH_BASE … #define DMA_CH_INC … #define DMA_CH_CR … #define DMA_CH_TCR … #define DMA_CH_RCR … #define DMA_CH_TDLR_HI … #define DMA_CH_TDLR_LO … #define DMA_CH_RDLR_HI … #define DMA_CH_RDLR_LO … #define DMA_CH_TDTR_LO … #define DMA_CH_RDTR_LO … #define DMA_CH_TDRLR … #define DMA_CH_RDRLR … #define DMA_CH_IER … #define DMA_CH_RIWT … #define DMA_CH_CATDR_LO … #define DMA_CH_CARDR_LO … #define DMA_CH_CATBR_HI … #define DMA_CH_CATBR_LO … #define DMA_CH_CARBR_HI … #define DMA_CH_CARBR_LO … #define DMA_CH_SR … /* DMA channel register entry bit positions and sizes */ #define DMA_CH_CR_PBLX8_INDEX … #define DMA_CH_CR_PBLX8_WIDTH … #define DMA_CH_CR_SPH_INDEX … #define DMA_CH_CR_SPH_WIDTH … #define DMA_CH_IER_AIE20_INDEX … #define DMA_CH_IER_AIE20_WIDTH … #define DMA_CH_IER_AIE_INDEX … #define DMA_CH_IER_AIE_WIDTH … #define DMA_CH_IER_FBEE_INDEX … #define DMA_CH_IER_FBEE_WIDTH … #define DMA_CH_IER_NIE20_INDEX … #define DMA_CH_IER_NIE20_WIDTH … #define DMA_CH_IER_NIE_INDEX … #define DMA_CH_IER_NIE_WIDTH … #define DMA_CH_IER_RBUE_INDEX … #define DMA_CH_IER_RBUE_WIDTH … #define DMA_CH_IER_RIE_INDEX … #define DMA_CH_IER_RIE_WIDTH … #define DMA_CH_IER_RSE_INDEX … #define DMA_CH_IER_RSE_WIDTH … #define DMA_CH_IER_TBUE_INDEX … #define DMA_CH_IER_TBUE_WIDTH … #define DMA_CH_IER_TIE_INDEX … #define DMA_CH_IER_TIE_WIDTH … #define DMA_CH_IER_TXSE_INDEX … #define DMA_CH_IER_TXSE_WIDTH … #define DMA_CH_RCR_PBL_INDEX … #define DMA_CH_RCR_PBL_WIDTH … #define DMA_CH_RCR_RBSZ_INDEX … #define DMA_CH_RCR_RBSZ_WIDTH … #define DMA_CH_RCR_SR_INDEX … #define DMA_CH_RCR_SR_WIDTH … #define DMA_CH_RIWT_RWT_INDEX … #define DMA_CH_RIWT_RWT_WIDTH … #define DMA_CH_SR_FBE_INDEX … #define DMA_CH_SR_FBE_WIDTH … #define DMA_CH_SR_RBU_INDEX … #define DMA_CH_SR_RBU_WIDTH … #define DMA_CH_SR_RI_INDEX … #define DMA_CH_SR_RI_WIDTH … #define DMA_CH_SR_RPS_INDEX … #define DMA_CH_SR_RPS_WIDTH … #define DMA_CH_SR_TBU_INDEX … #define DMA_CH_SR_TBU_WIDTH … #define DMA_CH_SR_TI_INDEX … #define DMA_CH_SR_TI_WIDTH … #define DMA_CH_SR_TPS_INDEX … #define DMA_CH_SR_TPS_WIDTH … #define DMA_CH_TCR_OSP_INDEX … #define DMA_CH_TCR_OSP_WIDTH … #define DMA_CH_TCR_PBL_INDEX … #define DMA_CH_TCR_PBL_WIDTH … #define DMA_CH_TCR_ST_INDEX … #define DMA_CH_TCR_ST_WIDTH … #define DMA_CH_TCR_TSE_INDEX … #define DMA_CH_TCR_TSE_WIDTH … /* DMA channel register values */ #define DMA_OSP_DISABLE … #define DMA_OSP_ENABLE … #define DMA_PBL_1 … #define DMA_PBL_2 … #define DMA_PBL_4 … #define DMA_PBL_8 … #define DMA_PBL_16 … #define DMA_PBL_32 … #define DMA_PBL_64 … #define DMA_PBL_128 … #define DMA_PBL_256 … #define DMA_PBL_X8_DISABLE … #define DMA_PBL_X8_ENABLE … /* MAC register offsets */ #define MAC_TCR … #define MAC_RCR … #define MAC_PFR … #define MAC_WTR … #define MAC_HTR0 … #define MAC_VLANTR … #define MAC_VLANHTR … #define MAC_VLANIR … #define MAC_IVLANIR … #define MAC_RETMR … #define MAC_Q0TFCR … #define MAC_RFCR … #define MAC_RQC0R … #define MAC_RQC1R … #define MAC_RQC2R … #define MAC_RQC3R … #define MAC_ISR … #define MAC_IER … #define MAC_RTSR … #define MAC_PMTCSR … #define MAC_RWKPFR … #define MAC_LPICSR … #define MAC_LPITCR … #define MAC_TIR … #define MAC_VR … #define MAC_DR … #define MAC_HWF0R … #define MAC_HWF1R … #define MAC_HWF2R … #define MAC_MDIOSCAR … #define MAC_MDIOSCCDR … #define MAC_MDIOISR … #define MAC_MDIOIER … #define MAC_MDIOCL22R … #define MAC_GPIOCR … #define MAC_GPIOSR … #define MAC_MACA0HR … #define MAC_MACA0LR … #define MAC_MACA1HR … #define MAC_MACA1LR … #define MAC_RSSCR … #define MAC_RSSAR … #define MAC_RSSDR … #define MAC_TSCR … #define MAC_SSIR … #define MAC_STSR … #define MAC_STNR … #define MAC_STSUR … #define MAC_STNUR … #define MAC_TSAR … #define MAC_TSSR … #define MAC_TXSNR … #define MAC_TXSSR … #define MAC_QTFCR_INC … #define MAC_MACA_INC … #define MAC_HTR_INC … #define MAC_RQC2_INC … #define MAC_RQC2_Q_PER_REG … /* MAC register entry bit positions and sizes */ #define MAC_HWF0R_ADDMACADRSEL_INDEX … #define MAC_HWF0R_ADDMACADRSEL_WIDTH … #define MAC_HWF0R_ARPOFFSEL_INDEX … #define MAC_HWF0R_ARPOFFSEL_WIDTH … #define MAC_HWF0R_EEESEL_INDEX … #define MAC_HWF0R_EEESEL_WIDTH … #define MAC_HWF0R_GMIISEL_INDEX … #define MAC_HWF0R_GMIISEL_WIDTH … #define MAC_HWF0R_MGKSEL_INDEX … #define MAC_HWF0R_MGKSEL_WIDTH … #define MAC_HWF0R_MMCSEL_INDEX … #define MAC_HWF0R_MMCSEL_WIDTH … #define MAC_HWF0R_RWKSEL_INDEX … #define MAC_HWF0R_RWKSEL_WIDTH … #define MAC_HWF0R_RXCOESEL_INDEX … #define MAC_HWF0R_RXCOESEL_WIDTH … #define MAC_HWF0R_SAVLANINS_INDEX … #define MAC_HWF0R_SAVLANINS_WIDTH … #define MAC_HWF0R_SMASEL_INDEX … #define MAC_HWF0R_SMASEL_WIDTH … #define MAC_HWF0R_TSSEL_INDEX … #define MAC_HWF0R_TSSEL_WIDTH … #define MAC_HWF0R_TSSTSSEL_INDEX … #define MAC_HWF0R_TSSTSSEL_WIDTH … #define MAC_HWF0R_TXCOESEL_INDEX … #define MAC_HWF0R_TXCOESEL_WIDTH … #define MAC_HWF0R_VLHASH_INDEX … #define MAC_HWF0R_VLHASH_WIDTH … #define MAC_HWF0R_VXN_INDEX … #define MAC_HWF0R_VXN_WIDTH … #define MAC_HWF1R_ADDR64_INDEX … #define MAC_HWF1R_ADDR64_WIDTH … #define MAC_HWF1R_ADVTHWORD_INDEX … #define MAC_HWF1R_ADVTHWORD_WIDTH … #define MAC_HWF1R_DBGMEMA_INDEX … #define MAC_HWF1R_DBGMEMA_WIDTH … #define MAC_HWF1R_DCBEN_INDEX … #define MAC_HWF1R_DCBEN_WIDTH … #define MAC_HWF1R_HASHTBLSZ_INDEX … #define MAC_HWF1R_HASHTBLSZ_WIDTH … #define MAC_HWF1R_L3L4FNUM_INDEX … #define MAC_HWF1R_L3L4FNUM_WIDTH … #define MAC_HWF1R_NUMTC_INDEX … #define MAC_HWF1R_NUMTC_WIDTH … #define MAC_HWF1R_RSSEN_INDEX … #define MAC_HWF1R_RSSEN_WIDTH … #define MAC_HWF1R_RXFIFOSIZE_INDEX … #define MAC_HWF1R_RXFIFOSIZE_WIDTH … #define MAC_HWF1R_SPHEN_INDEX … #define MAC_HWF1R_SPHEN_WIDTH … #define MAC_HWF1R_TSOEN_INDEX … #define MAC_HWF1R_TSOEN_WIDTH … #define MAC_HWF1R_TXFIFOSIZE_INDEX … #define MAC_HWF1R_TXFIFOSIZE_WIDTH … #define MAC_HWF2R_AUXSNAPNUM_INDEX … #define MAC_HWF2R_AUXSNAPNUM_WIDTH … #define MAC_HWF2R_PPSOUTNUM_INDEX … #define MAC_HWF2R_PPSOUTNUM_WIDTH … #define MAC_HWF2R_RXCHCNT_INDEX … #define MAC_HWF2R_RXCHCNT_WIDTH … #define MAC_HWF2R_RXQCNT_INDEX … #define MAC_HWF2R_RXQCNT_WIDTH … #define MAC_HWF2R_TXCHCNT_INDEX … #define MAC_HWF2R_TXCHCNT_WIDTH … #define MAC_HWF2R_TXQCNT_INDEX … #define MAC_HWF2R_TXQCNT_WIDTH … #define MAC_IER_TSIE_INDEX … #define MAC_IER_TSIE_WIDTH … #define MAC_ISR_MMCRXIS_INDEX … #define MAC_ISR_MMCRXIS_WIDTH … #define MAC_ISR_MMCTXIS_INDEX … #define MAC_ISR_MMCTXIS_WIDTH … #define MAC_ISR_PMTIS_INDEX … #define MAC_ISR_PMTIS_WIDTH … #define MAC_ISR_SMI_INDEX … #define MAC_ISR_SMI_WIDTH … #define MAC_ISR_TSIS_INDEX … #define MAC_ISR_TSIS_WIDTH … #define MAC_MACA1HR_AE_INDEX … #define MAC_MACA1HR_AE_WIDTH … #define MAC_MDIOIER_SNGLCOMPIE_INDEX … #define MAC_MDIOIER_SNGLCOMPIE_WIDTH … #define MAC_MDIOISR_SNGLCOMPINT_INDEX … #define MAC_MDIOISR_SNGLCOMPINT_WIDTH … #define MAC_MDIOSCAR_DA_INDEX … #define MAC_MDIOSCAR_DA_WIDTH … #define MAC_MDIOSCAR_PA_INDEX … #define MAC_MDIOSCAR_PA_WIDTH … #define MAC_MDIOSCAR_RA_INDEX … #define MAC_MDIOSCAR_RA_WIDTH … #define MAC_MDIOSCCDR_BUSY_INDEX … #define MAC_MDIOSCCDR_BUSY_WIDTH … #define MAC_MDIOSCCDR_CMD_INDEX … #define MAC_MDIOSCCDR_CMD_WIDTH … #define MAC_MDIOSCCDR_CR_INDEX … #define MAC_MDIOSCCDR_CR_WIDTH … #define MAC_MDIOSCCDR_DATA_INDEX … #define MAC_MDIOSCCDR_DATA_WIDTH … #define MAC_MDIOSCCDR_SADDR_INDEX … #define MAC_MDIOSCCDR_SADDR_WIDTH … #define MAC_PFR_HMC_INDEX … #define MAC_PFR_HMC_WIDTH … #define MAC_PFR_HPF_INDEX … #define MAC_PFR_HPF_WIDTH … #define MAC_PFR_HUC_INDEX … #define MAC_PFR_HUC_WIDTH … #define MAC_PFR_PM_INDEX … #define MAC_PFR_PM_WIDTH … #define MAC_PFR_PR_INDEX … #define MAC_PFR_PR_WIDTH … #define MAC_PFR_VTFE_INDEX … #define MAC_PFR_VTFE_WIDTH … #define MAC_PFR_VUCC_INDEX … #define MAC_PFR_VUCC_WIDTH … #define MAC_PMTCSR_MGKPKTEN_INDEX … #define MAC_PMTCSR_MGKPKTEN_WIDTH … #define MAC_PMTCSR_PWRDWN_INDEX … #define MAC_PMTCSR_PWRDWN_WIDTH … #define MAC_PMTCSR_RWKFILTRST_INDEX … #define MAC_PMTCSR_RWKFILTRST_WIDTH … #define MAC_PMTCSR_RWKPKTEN_INDEX … #define MAC_PMTCSR_RWKPKTEN_WIDTH … #define MAC_Q0TFCR_PT_INDEX … #define MAC_Q0TFCR_PT_WIDTH … #define MAC_Q0TFCR_TFE_INDEX … #define MAC_Q0TFCR_TFE_WIDTH … #define MAC_RCR_ACS_INDEX … #define MAC_RCR_ACS_WIDTH … #define MAC_RCR_CST_INDEX … #define MAC_RCR_CST_WIDTH … #define MAC_RCR_DCRCC_INDEX … #define MAC_RCR_DCRCC_WIDTH … #define MAC_RCR_HDSMS_INDEX … #define MAC_RCR_HDSMS_WIDTH … #define MAC_RCR_IPC_INDEX … #define MAC_RCR_IPC_WIDTH … #define MAC_RCR_JE_INDEX … #define MAC_RCR_JE_WIDTH … #define MAC_RCR_LM_INDEX … #define MAC_RCR_LM_WIDTH … #define MAC_RCR_RE_INDEX … #define MAC_RCR_RE_WIDTH … #define MAC_RFCR_PFCE_INDEX … #define MAC_RFCR_PFCE_WIDTH … #define MAC_RFCR_RFE_INDEX … #define MAC_RFCR_RFE_WIDTH … #define MAC_RFCR_UP_INDEX … #define MAC_RFCR_UP_WIDTH … #define MAC_RQC0R_RXQ0EN_INDEX … #define MAC_RQC0R_RXQ0EN_WIDTH … #define MAC_RSSAR_ADDRT_INDEX … #define MAC_RSSAR_ADDRT_WIDTH … #define MAC_RSSAR_CT_INDEX … #define MAC_RSSAR_CT_WIDTH … #define MAC_RSSAR_OB_INDEX … #define MAC_RSSAR_OB_WIDTH … #define MAC_RSSAR_RSSIA_INDEX … #define MAC_RSSAR_RSSIA_WIDTH … #define MAC_RSSCR_IP2TE_INDEX … #define MAC_RSSCR_IP2TE_WIDTH … #define MAC_RSSCR_RSSE_INDEX … #define MAC_RSSCR_RSSE_WIDTH … #define MAC_RSSCR_TCP4TE_INDEX … #define MAC_RSSCR_TCP4TE_WIDTH … #define MAC_RSSCR_UDP4TE_INDEX … #define MAC_RSSCR_UDP4TE_WIDTH … #define MAC_RSSDR_DMCH_INDEX … #define MAC_RSSDR_DMCH_WIDTH … #define MAC_SSIR_SNSINC_INDEX … #define MAC_SSIR_SNSINC_WIDTH … #define MAC_SSIR_SSINC_INDEX … #define MAC_SSIR_SSINC_WIDTH … #define MAC_TCR_SS_INDEX … #define MAC_TCR_SS_WIDTH … #define MAC_TCR_TE_INDEX … #define MAC_TCR_TE_WIDTH … #define MAC_TCR_VNE_INDEX … #define MAC_TCR_VNE_WIDTH … #define MAC_TCR_VNM_INDEX … #define MAC_TCR_VNM_WIDTH … #define MAC_TIR_TNID_INDEX … #define MAC_TIR_TNID_WIDTH … #define MAC_TSCR_AV8021ASMEN_INDEX … #define MAC_TSCR_AV8021ASMEN_WIDTH … #define MAC_TSCR_SNAPTYPSEL_INDEX … #define MAC_TSCR_SNAPTYPSEL_WIDTH … #define MAC_TSCR_TSADDREG_INDEX … #define MAC_TSCR_TSADDREG_WIDTH … #define MAC_TSCR_TSCFUPDT_INDEX … #define MAC_TSCR_TSCFUPDT_WIDTH … #define MAC_TSCR_TSCTRLSSR_INDEX … #define MAC_TSCR_TSCTRLSSR_WIDTH … #define MAC_TSCR_TSENA_INDEX … #define MAC_TSCR_TSENA_WIDTH … #define MAC_TSCR_TSENALL_INDEX … #define MAC_TSCR_TSENALL_WIDTH … #define MAC_TSCR_TSEVNTENA_INDEX … #define MAC_TSCR_TSEVNTENA_WIDTH … #define MAC_TSCR_TSINIT_INDEX … #define MAC_TSCR_TSINIT_WIDTH … #define MAC_TSCR_TSIPENA_INDEX … #define MAC_TSCR_TSIPENA_WIDTH … #define MAC_TSCR_TSIPV4ENA_INDEX … #define MAC_TSCR_TSIPV4ENA_WIDTH … #define MAC_TSCR_TSIPV6ENA_INDEX … #define MAC_TSCR_TSIPV6ENA_WIDTH … #define MAC_TSCR_TSMSTRENA_INDEX … #define MAC_TSCR_TSMSTRENA_WIDTH … #define MAC_TSCR_TSVER2ENA_INDEX … #define MAC_TSCR_TSVER2ENA_WIDTH … #define MAC_TSCR_TXTSSTSM_INDEX … #define MAC_TSCR_TXTSSTSM_WIDTH … #define MAC_TSSR_TXTSC_INDEX … #define MAC_TSSR_TXTSC_WIDTH … #define MAC_TXSNR_TXTSSTSMIS_INDEX … #define MAC_TXSNR_TXTSSTSMIS_WIDTH … #define MAC_VLANHTR_VLHT_INDEX … #define MAC_VLANHTR_VLHT_WIDTH … #define MAC_VLANIR_VLTI_INDEX … #define MAC_VLANIR_VLTI_WIDTH … #define MAC_VLANIR_CSVL_INDEX … #define MAC_VLANIR_CSVL_WIDTH … #define MAC_VLANTR_DOVLTC_INDEX … #define MAC_VLANTR_DOVLTC_WIDTH … #define MAC_VLANTR_ERSVLM_INDEX … #define MAC_VLANTR_ERSVLM_WIDTH … #define MAC_VLANTR_ESVL_INDEX … #define MAC_VLANTR_ESVL_WIDTH … #define MAC_VLANTR_ETV_INDEX … #define MAC_VLANTR_ETV_WIDTH … #define MAC_VLANTR_EVLS_INDEX … #define MAC_VLANTR_EVLS_WIDTH … #define MAC_VLANTR_EVLRXS_INDEX … #define MAC_VLANTR_EVLRXS_WIDTH … #define MAC_VLANTR_VL_INDEX … #define MAC_VLANTR_VL_WIDTH … #define MAC_VLANTR_VTHM_INDEX … #define MAC_VLANTR_VTHM_WIDTH … #define MAC_VLANTR_VTIM_INDEX … #define MAC_VLANTR_VTIM_WIDTH … #define MAC_VR_DEVID_INDEX … #define MAC_VR_DEVID_WIDTH … #define MAC_VR_SNPSVER_INDEX … #define MAC_VR_SNPSVER_WIDTH … #define MAC_VR_USERVER_INDEX … #define MAC_VR_USERVER_WIDTH … /* MMC register offsets */ #define MMC_CR … #define MMC_RISR … #define MMC_TISR … #define MMC_RIER … #define MMC_TIER … #define MMC_TXOCTETCOUNT_GB_LO … #define MMC_TXOCTETCOUNT_GB_HI … #define MMC_TXFRAMECOUNT_GB_LO … #define MMC_TXFRAMECOUNT_GB_HI … #define MMC_TXBROADCASTFRAMES_G_LO … #define MMC_TXBROADCASTFRAMES_G_HI … #define MMC_TXMULTICASTFRAMES_G_LO … #define MMC_TXMULTICASTFRAMES_G_HI … #define MMC_TX64OCTETS_GB_LO … #define MMC_TX64OCTETS_GB_HI … #define MMC_TX65TO127OCTETS_GB_LO … #define MMC_TX65TO127OCTETS_GB_HI … #define MMC_TX128TO255OCTETS_GB_LO … #define MMC_TX128TO255OCTETS_GB_HI … #define MMC_TX256TO511OCTETS_GB_LO … #define MMC_TX256TO511OCTETS_GB_HI … #define MMC_TX512TO1023OCTETS_GB_LO … #define MMC_TX512TO1023OCTETS_GB_HI … #define MMC_TX1024TOMAXOCTETS_GB_LO … #define MMC_TX1024TOMAXOCTETS_GB_HI … #define MMC_TXUNICASTFRAMES_GB_LO … #define MMC_TXUNICASTFRAMES_GB_HI … #define MMC_TXMULTICASTFRAMES_GB_LO … #define MMC_TXMULTICASTFRAMES_GB_HI … #define MMC_TXBROADCASTFRAMES_GB_LO … #define MMC_TXBROADCASTFRAMES_GB_HI … #define MMC_TXUNDERFLOWERROR_LO … #define MMC_TXUNDERFLOWERROR_HI … #define MMC_TXOCTETCOUNT_G_LO … #define MMC_TXOCTETCOUNT_G_HI … #define MMC_TXFRAMECOUNT_G_LO … #define MMC_TXFRAMECOUNT_G_HI … #define MMC_TXPAUSEFRAMES_LO … #define MMC_TXPAUSEFRAMES_HI … #define MMC_TXVLANFRAMES_G_LO … #define MMC_TXVLANFRAMES_G_HI … #define MMC_RXFRAMECOUNT_GB_LO … #define MMC_RXFRAMECOUNT_GB_HI … #define MMC_RXOCTETCOUNT_GB_LO … #define MMC_RXOCTETCOUNT_GB_HI … #define MMC_RXOCTETCOUNT_G_LO … #define MMC_RXOCTETCOUNT_G_HI … #define MMC_RXBROADCASTFRAMES_G_LO … #define MMC_RXBROADCASTFRAMES_G_HI … #define MMC_RXMULTICASTFRAMES_G_LO … #define MMC_RXMULTICASTFRAMES_G_HI … #define MMC_RXCRCERROR_LO … #define MMC_RXCRCERROR_HI … #define MMC_RXRUNTERROR … #define MMC_RXJABBERERROR … #define MMC_RXUNDERSIZE_G … #define MMC_RXOVERSIZE_G … #define MMC_RX64OCTETS_GB_LO … #define MMC_RX64OCTETS_GB_HI … #define MMC_RX65TO127OCTETS_GB_LO … #define MMC_RX65TO127OCTETS_GB_HI … #define MMC_RX128TO255OCTETS_GB_LO … #define MMC_RX128TO255OCTETS_GB_HI … #define MMC_RX256TO511OCTETS_GB_LO … #define MMC_RX256TO511OCTETS_GB_HI … #define MMC_RX512TO1023OCTETS_GB_LO … #define MMC_RX512TO1023OCTETS_GB_HI … #define MMC_RX1024TOMAXOCTETS_GB_LO … #define MMC_RX1024TOMAXOCTETS_GB_HI … #define MMC_RXUNICASTFRAMES_G_LO … #define MMC_RXUNICASTFRAMES_G_HI … #define MMC_RXLENGTHERROR_LO … #define MMC_RXLENGTHERROR_HI … #define MMC_RXOUTOFRANGETYPE_LO … #define MMC_RXOUTOFRANGETYPE_HI … #define MMC_RXPAUSEFRAMES_LO … #define MMC_RXPAUSEFRAMES_HI … #define MMC_RXFIFOOVERFLOW_LO … #define MMC_RXFIFOOVERFLOW_HI … #define MMC_RXVLANFRAMES_GB_LO … #define MMC_RXVLANFRAMES_GB_HI … #define MMC_RXWATCHDOGERROR … /* MMC register entry bit positions and sizes */ #define MMC_CR_CR_INDEX … #define MMC_CR_CR_WIDTH … #define MMC_CR_CSR_INDEX … #define MMC_CR_CSR_WIDTH … #define MMC_CR_ROR_INDEX … #define MMC_CR_ROR_WIDTH … #define MMC_CR_MCF_INDEX … #define MMC_CR_MCF_WIDTH … #define MMC_CR_MCT_INDEX … #define MMC_CR_MCT_WIDTH … #define MMC_RIER_ALL_INTERRUPTS_INDEX … #define MMC_RIER_ALL_INTERRUPTS_WIDTH … #define MMC_RISR_RXFRAMECOUNT_GB_INDEX … #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH … #define MMC_RISR_RXOCTETCOUNT_GB_INDEX … #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH … #define MMC_RISR_RXOCTETCOUNT_G_INDEX … #define MMC_RISR_RXOCTETCOUNT_G_WIDTH … #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX … #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH … #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX … #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH … #define MMC_RISR_RXCRCERROR_INDEX … #define MMC_RISR_RXCRCERROR_WIDTH … #define MMC_RISR_RXRUNTERROR_INDEX … #define MMC_RISR_RXRUNTERROR_WIDTH … #define MMC_RISR_RXJABBERERROR_INDEX … #define MMC_RISR_RXJABBERERROR_WIDTH … #define MMC_RISR_RXUNDERSIZE_G_INDEX … #define MMC_RISR_RXUNDERSIZE_G_WIDTH … #define MMC_RISR_RXOVERSIZE_G_INDEX … #define MMC_RISR_RXOVERSIZE_G_WIDTH … #define MMC_RISR_RX64OCTETS_GB_INDEX … #define MMC_RISR_RX64OCTETS_GB_WIDTH … #define MMC_RISR_RX65TO127OCTETS_GB_INDEX … #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH … #define MMC_RISR_RX128TO255OCTETS_GB_INDEX … #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH … #define MMC_RISR_RX256TO511OCTETS_GB_INDEX … #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH … #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX … #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH … #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX … #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH … #define MMC_RISR_RXUNICASTFRAMES_G_INDEX … #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH … #define MMC_RISR_RXLENGTHERROR_INDEX … #define MMC_RISR_RXLENGTHERROR_WIDTH … #define MMC_RISR_RXOUTOFRANGETYPE_INDEX … #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH … #define MMC_RISR_RXPAUSEFRAMES_INDEX … #define MMC_RISR_RXPAUSEFRAMES_WIDTH … #define MMC_RISR_RXFIFOOVERFLOW_INDEX … #define MMC_RISR_RXFIFOOVERFLOW_WIDTH … #define MMC_RISR_RXVLANFRAMES_GB_INDEX … #define MMC_RISR_RXVLANFRAMES_GB_WIDTH … #define MMC_RISR_RXWATCHDOGERROR_INDEX … #define MMC_RISR_RXWATCHDOGERROR_WIDTH … #define MMC_TIER_ALL_INTERRUPTS_INDEX … #define MMC_TIER_ALL_INTERRUPTS_WIDTH … #define MMC_TISR_TXOCTETCOUNT_GB_INDEX … #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH … #define MMC_TISR_TXFRAMECOUNT_GB_INDEX … #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH … #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX … #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH … #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX … #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH … #define MMC_TISR_TX64OCTETS_GB_INDEX … #define MMC_TISR_TX64OCTETS_GB_WIDTH … #define MMC_TISR_TX65TO127OCTETS_GB_INDEX … #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH … #define MMC_TISR_TX128TO255OCTETS_GB_INDEX … #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH … #define MMC_TISR_TX256TO511OCTETS_GB_INDEX … #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH … #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX … #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH … #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX … #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH … #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX … #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH … #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX … #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH … #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX … #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH … #define MMC_TISR_TXUNDERFLOWERROR_INDEX … #define MMC_TISR_TXUNDERFLOWERROR_WIDTH … #define MMC_TISR_TXOCTETCOUNT_G_INDEX … #define MMC_TISR_TXOCTETCOUNT_G_WIDTH … #define MMC_TISR_TXFRAMECOUNT_G_INDEX … #define MMC_TISR_TXFRAMECOUNT_G_WIDTH … #define MMC_TISR_TXPAUSEFRAMES_INDEX … #define MMC_TISR_TXPAUSEFRAMES_WIDTH … #define MMC_TISR_TXVLANFRAMES_G_INDEX … #define MMC_TISR_TXVLANFRAMES_G_WIDTH … /* MTL register offsets */ #define MTL_OMR … #define MTL_FDCR … #define MTL_FDSR … #define MTL_FDDR … #define MTL_ISR … #define MTL_RQDCM0R … #define MTL_TCPM0R … #define MTL_TCPM1R … #define MTL_RQDCM_INC … #define MTL_RQDCM_Q_PER_REG … #define MTL_TCPM_INC … #define MTL_TCPM_TC_PER_REG … /* MTL register entry bit positions and sizes */ #define MTL_OMR_ETSALG_INDEX … #define MTL_OMR_ETSALG_WIDTH … #define MTL_OMR_RAA_INDEX … #define MTL_OMR_RAA_WIDTH … /* MTL queue register offsets * Multiple queues can be active. The first queue has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_Q_BASE … #define MTL_Q_INC … #define MTL_Q_TQOMR … #define MTL_Q_TQUR … #define MTL_Q_TQDR … #define MTL_Q_RQOMR … #define MTL_Q_RQMPOCR … #define MTL_Q_RQDR … #define MTL_Q_RQFCR … #define MTL_Q_IER … #define MTL_Q_ISR … /* MTL queue register entry bit positions and sizes */ #define MTL_Q_RQDR_PRXQ_INDEX … #define MTL_Q_RQDR_PRXQ_WIDTH … #define MTL_Q_RQDR_RXQSTS_INDEX … #define MTL_Q_RQDR_RXQSTS_WIDTH … #define MTL_Q_RQFCR_RFA_INDEX … #define MTL_Q_RQFCR_RFA_WIDTH … #define MTL_Q_RQFCR_RFD_INDEX … #define MTL_Q_RQFCR_RFD_WIDTH … #define MTL_Q_RQOMR_EHFC_INDEX … #define MTL_Q_RQOMR_EHFC_WIDTH … #define MTL_Q_RQOMR_RQS_INDEX … #define MTL_Q_RQOMR_RQS_WIDTH … #define MTL_Q_RQOMR_RSF_INDEX … #define MTL_Q_RQOMR_RSF_WIDTH … #define MTL_Q_RQOMR_RTC_INDEX … #define MTL_Q_RQOMR_RTC_WIDTH … #define MTL_Q_TQDR_TRCSTS_INDEX … #define MTL_Q_TQDR_TRCSTS_WIDTH … #define MTL_Q_TQDR_TXQSTS_INDEX … #define MTL_Q_TQDR_TXQSTS_WIDTH … #define MTL_Q_TQOMR_FTQ_INDEX … #define MTL_Q_TQOMR_FTQ_WIDTH … #define MTL_Q_TQOMR_Q2TCMAP_INDEX … #define MTL_Q_TQOMR_Q2TCMAP_WIDTH … #define MTL_Q_TQOMR_TQS_INDEX … #define MTL_Q_TQOMR_TQS_WIDTH … #define MTL_Q_TQOMR_TSF_INDEX … #define MTL_Q_TQOMR_TSF_WIDTH … #define MTL_Q_TQOMR_TTC_INDEX … #define MTL_Q_TQOMR_TTC_WIDTH … #define MTL_Q_TQOMR_TXQEN_INDEX … #define MTL_Q_TQOMR_TXQEN_WIDTH … /* MTL queue register value */ #define MTL_RSF_DISABLE … #define MTL_RSF_ENABLE … #define MTL_TSF_DISABLE … #define MTL_TSF_ENABLE … #define MTL_RX_THRESHOLD_64 … #define MTL_RX_THRESHOLD_96 … #define MTL_RX_THRESHOLD_128 … #define MTL_TX_THRESHOLD_32 … #define MTL_TX_THRESHOLD_64 … #define MTL_TX_THRESHOLD_96 … #define MTL_TX_THRESHOLD_128 … #define MTL_TX_THRESHOLD_192 … #define MTL_TX_THRESHOLD_256 … #define MTL_TX_THRESHOLD_384 … #define MTL_TX_THRESHOLD_512 … #define MTL_ETSALG_WRR … #define MTL_ETSALG_WFQ … #define MTL_ETSALG_DWRR … #define MTL_RAA_SP … #define MTL_RAA_WSP … #define MTL_Q_DISABLED … #define MTL_Q_ENABLED … /* MTL traffic class register offsets * Multiple traffic classes can be active. The first class has registers * that begin at 0x1100. Each subsequent queue has registers that * are accessed using an offset of 0x80 from the previous queue. */ #define MTL_TC_BASE … #define MTL_TC_INC … #define MTL_TC_ETSCR … #define MTL_TC_ETSSR … #define MTL_TC_QWR … /* MTL traffic class register entry bit positions and sizes */ #define MTL_TC_ETSCR_TSA_INDEX … #define MTL_TC_ETSCR_TSA_WIDTH … #define MTL_TC_QWR_QW_INDEX … #define MTL_TC_QWR_QW_WIDTH … /* MTL traffic class register value */ #define MTL_TSA_SP … #define MTL_TSA_ETS … /* PCS register offsets */ #define PCS_V1_WINDOW_SELECT … #define PCS_V2_WINDOW_DEF … #define PCS_V2_WINDOW_SELECT … #define PCS_V2_RV_WINDOW_DEF … #define PCS_V2_RV_WINDOW_SELECT … #define PCS_V2_YC_WINDOW_DEF … #define PCS_V2_YC_WINDOW_SELECT … /* PCS register entry bit positions and sizes */ #define PCS_V2_WINDOW_DEF_OFFSET_INDEX … #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH … #define PCS_V2_WINDOW_DEF_SIZE_INDEX … #define PCS_V2_WINDOW_DEF_SIZE_WIDTH … /* SerDes integration register offsets */ #define SIR0_KR_RT_1 … #define SIR0_STATUS … #define SIR1_SPEED … /* SerDes integration register entry bit positions and sizes */ #define SIR0_KR_RT_1_RESET_INDEX … #define SIR0_KR_RT_1_RESET_WIDTH … #define SIR0_STATUS_RX_READY_INDEX … #define SIR0_STATUS_RX_READY_WIDTH … #define SIR0_STATUS_TX_READY_INDEX … #define SIR0_STATUS_TX_READY_WIDTH … #define SIR1_SPEED_CDR_RATE_INDEX … #define SIR1_SPEED_CDR_RATE_WIDTH … #define SIR1_SPEED_DATARATE_INDEX … #define SIR1_SPEED_DATARATE_WIDTH … #define SIR1_SPEED_PLLSEL_INDEX … #define SIR1_SPEED_PLLSEL_WIDTH … #define SIR1_SPEED_RATECHANGE_INDEX … #define SIR1_SPEED_RATECHANGE_WIDTH … #define SIR1_SPEED_TXAMP_INDEX … #define SIR1_SPEED_TXAMP_WIDTH … #define SIR1_SPEED_WORDMODE_INDEX … #define SIR1_SPEED_WORDMODE_WIDTH … /* SerDes RxTx register offsets */ #define RXTX_REG6 … #define RXTX_REG20 … #define RXTX_REG22 … #define RXTX_REG114 … #define RXTX_REG129 … /* SerDes RxTx register entry bit positions and sizes */ #define RXTX_REG6_RESETB_RXD_INDEX … #define RXTX_REG6_RESETB_RXD_WIDTH … #define RXTX_REG20_BLWC_ENA_INDEX … #define RXTX_REG20_BLWC_ENA_WIDTH … #define RXTX_REG114_PQ_REG_INDEX … #define RXTX_REG114_PQ_REG_WIDTH … #define RXTX_REG129_RXDFE_CONFIG_INDEX … #define RXTX_REG129_RXDFE_CONFIG_WIDTH … /* MAC Control register offsets */ #define XP_PROP_0 … #define XP_PROP_1 … #define XP_PROP_2 … #define XP_PROP_3 … #define XP_PROP_4 … #define XP_PROP_5 … #define XP_MAC_ADDR_LO … #define XP_MAC_ADDR_HI … #define XP_ECC_ISR … #define XP_ECC_IER … #define XP_ECC_CNT0 … #define XP_ECC_CNT1 … #define XP_DRIVER_INT_REQ … #define XP_DRIVER_INT_RO … #define XP_DRIVER_SCRATCH_0 … #define XP_DRIVER_SCRATCH_1 … #define XP_INT_REISSUE_EN … #define XP_INT_EN … #define XP_I2C_MUTEX … #define XP_MDIO_MUTEX … /* MAC Control register entry bit positions and sizes */ #define XP_DRIVER_INT_REQ_REQUEST_INDEX … #define XP_DRIVER_INT_REQ_REQUEST_WIDTH … #define XP_DRIVER_INT_RO_STATUS_INDEX … #define XP_DRIVER_INT_RO_STATUS_WIDTH … #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX … #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH … #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX … #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH … #define XP_ECC_CNT0_RX_DED_INDEX … #define XP_ECC_CNT0_RX_DED_WIDTH … #define XP_ECC_CNT0_RX_SEC_INDEX … #define XP_ECC_CNT0_RX_SEC_WIDTH … #define XP_ECC_CNT0_TX_DED_INDEX … #define XP_ECC_CNT0_TX_DED_WIDTH … #define XP_ECC_CNT0_TX_SEC_INDEX … #define XP_ECC_CNT0_TX_SEC_WIDTH … #define XP_ECC_CNT1_DESC_DED_INDEX … #define XP_ECC_CNT1_DESC_DED_WIDTH … #define XP_ECC_CNT1_DESC_SEC_INDEX … #define XP_ECC_CNT1_DESC_SEC_WIDTH … #define XP_ECC_IER_DESC_DED_INDEX … #define XP_ECC_IER_DESC_DED_WIDTH … #define XP_ECC_IER_DESC_SEC_INDEX … #define XP_ECC_IER_DESC_SEC_WIDTH … #define XP_ECC_IER_RX_DED_INDEX … #define XP_ECC_IER_RX_DED_WIDTH … #define XP_ECC_IER_RX_SEC_INDEX … #define XP_ECC_IER_RX_SEC_WIDTH … #define XP_ECC_IER_TX_DED_INDEX … #define XP_ECC_IER_TX_DED_WIDTH … #define XP_ECC_IER_TX_SEC_INDEX … #define XP_ECC_IER_TX_SEC_WIDTH … #define XP_ECC_ISR_DESC_DED_INDEX … #define XP_ECC_ISR_DESC_DED_WIDTH … #define XP_ECC_ISR_DESC_SEC_INDEX … #define XP_ECC_ISR_DESC_SEC_WIDTH … #define XP_ECC_ISR_RX_DED_INDEX … #define XP_ECC_ISR_RX_DED_WIDTH … #define XP_ECC_ISR_RX_SEC_INDEX … #define XP_ECC_ISR_RX_SEC_WIDTH … #define XP_ECC_ISR_TX_DED_INDEX … #define XP_ECC_ISR_TX_DED_WIDTH … #define XP_ECC_ISR_TX_SEC_INDEX … #define XP_ECC_ISR_TX_SEC_WIDTH … #define XP_I2C_MUTEX_BUSY_INDEX … #define XP_I2C_MUTEX_BUSY_WIDTH … #define XP_I2C_MUTEX_ID_INDEX … #define XP_I2C_MUTEX_ID_WIDTH … #define XP_I2C_MUTEX_ACTIVE_INDEX … #define XP_I2C_MUTEX_ACTIVE_WIDTH … #define XP_MAC_ADDR_HI_VALID_INDEX … #define XP_MAC_ADDR_HI_VALID_WIDTH … #define XP_PROP_0_CONN_TYPE_INDEX … #define XP_PROP_0_CONN_TYPE_WIDTH … #define XP_PROP_0_MDIO_ADDR_INDEX … #define XP_PROP_0_MDIO_ADDR_WIDTH … #define XP_PROP_0_PORT_ID_INDEX … #define XP_PROP_0_PORT_ID_WIDTH … #define XP_PROP_0_PORT_MODE_INDEX … #define XP_PROP_0_PORT_MODE_WIDTH … #define XP_PROP_0_PORT_SPEEDS_INDEX … #define XP_PROP_0_PORT_SPEEDS_WIDTH … #define XP_PROP_1_MAX_RX_DMA_INDEX … #define XP_PROP_1_MAX_RX_DMA_WIDTH … #define XP_PROP_1_MAX_RX_QUEUES_INDEX … #define XP_PROP_1_MAX_RX_QUEUES_WIDTH … #define XP_PROP_1_MAX_TX_DMA_INDEX … #define XP_PROP_1_MAX_TX_DMA_WIDTH … #define XP_PROP_1_MAX_TX_QUEUES_INDEX … #define XP_PROP_1_MAX_TX_QUEUES_WIDTH … #define XP_PROP_2_RX_FIFO_SIZE_INDEX … #define XP_PROP_2_RX_FIFO_SIZE_WIDTH … #define XP_PROP_2_TX_FIFO_SIZE_INDEX … #define XP_PROP_2_TX_FIFO_SIZE_WIDTH … #define XP_PROP_3_GPIO_MASK_INDEX … #define XP_PROP_3_GPIO_MASK_WIDTH … #define XP_PROP_3_GPIO_MOD_ABS_INDEX … #define XP_PROP_3_GPIO_MOD_ABS_WIDTH … #define XP_PROP_3_GPIO_RATE_SELECT_INDEX … #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH … #define XP_PROP_3_GPIO_RX_LOS_INDEX … #define XP_PROP_3_GPIO_RX_LOS_WIDTH … #define XP_PROP_3_GPIO_TX_FAULT_INDEX … #define XP_PROP_3_GPIO_TX_FAULT_WIDTH … #define XP_PROP_3_GPIO_ADDR_INDEX … #define XP_PROP_3_GPIO_ADDR_WIDTH … #define XP_PROP_3_MDIO_RESET_INDEX … #define XP_PROP_3_MDIO_RESET_WIDTH … #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX … #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH … #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX … #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH … #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX … #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH … #define XP_PROP_4_MUX_ADDR_HI_INDEX … #define XP_PROP_4_MUX_ADDR_HI_WIDTH … #define XP_PROP_4_MUX_ADDR_LO_INDEX … #define XP_PROP_4_MUX_ADDR_LO_WIDTH … #define XP_PROP_4_MUX_CHAN_INDEX … #define XP_PROP_4_MUX_CHAN_WIDTH … #define XP_PROP_4_REDRV_ADDR_INDEX … #define XP_PROP_4_REDRV_ADDR_WIDTH … #define XP_PROP_4_REDRV_IF_INDEX … #define XP_PROP_4_REDRV_IF_WIDTH … #define XP_PROP_4_REDRV_LANE_INDEX … #define XP_PROP_4_REDRV_LANE_WIDTH … #define XP_PROP_4_REDRV_MODEL_INDEX … #define XP_PROP_4_REDRV_MODEL_WIDTH … #define XP_PROP_4_REDRV_PRESENT_INDEX … #define XP_PROP_4_REDRV_PRESENT_WIDTH … /* I2C Control register offsets */ #define IC_CON … #define IC_TAR … #define IC_DATA_CMD … #define IC_INTR_STAT … #define IC_INTR_MASK … #define IC_RAW_INTR_STAT … #define IC_CLR_INTR … #define IC_CLR_TX_ABRT … #define IC_CLR_STOP_DET … #define IC_ENABLE … #define IC_TXFLR … #define IC_RXFLR … #define IC_TX_ABRT_SOURCE … #define IC_ENABLE_STATUS … #define IC_COMP_PARAM_1 … /* I2C Control register entry bit positions and sizes */ #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX … #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH … #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX … #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH … #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX … #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH … #define IC_CON_MASTER_MODE_INDEX … #define IC_CON_MASTER_MODE_WIDTH … #define IC_CON_RESTART_EN_INDEX … #define IC_CON_RESTART_EN_WIDTH … #define IC_CON_RX_FIFO_FULL_HOLD_INDEX … #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH … #define IC_CON_SLAVE_DISABLE_INDEX … #define IC_CON_SLAVE_DISABLE_WIDTH … #define IC_CON_SPEED_INDEX … #define IC_CON_SPEED_WIDTH … #define IC_DATA_CMD_CMD_INDEX … #define IC_DATA_CMD_CMD_WIDTH … #define IC_DATA_CMD_STOP_INDEX … #define IC_DATA_CMD_STOP_WIDTH … #define IC_ENABLE_ABORT_INDEX … #define IC_ENABLE_ABORT_WIDTH … #define IC_ENABLE_EN_INDEX … #define IC_ENABLE_EN_WIDTH … #define IC_ENABLE_STATUS_EN_INDEX … #define IC_ENABLE_STATUS_EN_WIDTH … #define IC_INTR_MASK_TX_EMPTY_INDEX … #define IC_INTR_MASK_TX_EMPTY_WIDTH … #define IC_RAW_INTR_STAT_RX_FULL_INDEX … #define IC_RAW_INTR_STAT_RX_FULL_WIDTH … #define IC_RAW_INTR_STAT_STOP_DET_INDEX … #define IC_RAW_INTR_STAT_STOP_DET_WIDTH … #define IC_RAW_INTR_STAT_TX_ABRT_INDEX … #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH … #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX … #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH … /* I2C Control register value */ #define IC_TX_ABRT_7B_ADDR_NOACK … #define IC_TX_ABRT_ARB_LOST … /* Descriptor/Packet entry bit positions and sizes */ #define RX_PACKET_ERRORS_CRC_INDEX … #define RX_PACKET_ERRORS_CRC_WIDTH … #define RX_PACKET_ERRORS_FRAME_INDEX … #define RX_PACKET_ERRORS_FRAME_WIDTH … #define RX_PACKET_ERRORS_LENGTH_INDEX … #define RX_PACKET_ERRORS_LENGTH_WIDTH … #define RX_PACKET_ERRORS_OVERRUN_INDEX … #define RX_PACKET_ERRORS_OVERRUN_WIDTH … #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX … #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH … #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX … #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH … #define RX_PACKET_ATTRIBUTES_LAST_INDEX … #define RX_PACKET_ATTRIBUTES_LAST_WIDTH … #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX … #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH … #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX … #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH … #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX … #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH … #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX … #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH … #define RX_PACKET_ATTRIBUTES_FIRST_INDEX … #define RX_PACKET_ATTRIBUTES_FIRST_WIDTH … #define RX_PACKET_ATTRIBUTES_TNP_INDEX … #define RX_PACKET_ATTRIBUTES_TNP_WIDTH … #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX … #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH … #define RX_NORMAL_DESC0_OVT_INDEX … #define RX_NORMAL_DESC0_OVT_WIDTH … #define RX_NORMAL_DESC2_HL_INDEX … #define RX_NORMAL_DESC2_HL_WIDTH … #define RX_NORMAL_DESC2_TNP_INDEX … #define RX_NORMAL_DESC2_TNP_WIDTH … #define RX_NORMAL_DESC3_CDA_INDEX … #define RX_NORMAL_DESC3_CDA_WIDTH … #define RX_NORMAL_DESC3_CTXT_INDEX … #define RX_NORMAL_DESC3_CTXT_WIDTH … #define RX_NORMAL_DESC3_ES_INDEX … #define RX_NORMAL_DESC3_ES_WIDTH … #define RX_NORMAL_DESC3_ETLT_INDEX … #define RX_NORMAL_DESC3_ETLT_WIDTH … #define RX_NORMAL_DESC3_FD_INDEX … #define RX_NORMAL_DESC3_FD_WIDTH … #define RX_NORMAL_DESC3_INTE_INDEX … #define RX_NORMAL_DESC3_INTE_WIDTH … #define RX_NORMAL_DESC3_L34T_INDEX … #define RX_NORMAL_DESC3_L34T_WIDTH … #define RX_NORMAL_DESC3_LD_INDEX … #define RX_NORMAL_DESC3_LD_WIDTH … #define RX_NORMAL_DESC3_OWN_INDEX … #define RX_NORMAL_DESC3_OWN_WIDTH … #define RX_NORMAL_DESC3_PL_INDEX … #define RX_NORMAL_DESC3_PL_WIDTH … #define RX_NORMAL_DESC3_RSV_INDEX … #define RX_NORMAL_DESC3_RSV_WIDTH … #define RX_DESC3_L34T_IPV4_TCP … #define RX_DESC3_L34T_IPV4_UDP … #define RX_DESC3_L34T_IPV4_ICMP … #define RX_DESC3_L34T_IPV4_UNKNOWN … #define RX_DESC3_L34T_IPV6_TCP … #define RX_DESC3_L34T_IPV6_UDP … #define RX_DESC3_L34T_IPV6_ICMP … #define RX_DESC3_L34T_IPV6_UNKNOWN … #define RX_CONTEXT_DESC3_TSA_INDEX … #define RX_CONTEXT_DESC3_TSA_WIDTH … #define RX_CONTEXT_DESC3_TSD_INDEX … #define RX_CONTEXT_DESC3_TSD_WIDTH … #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX … #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH … #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX … #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH … #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX … #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH … #define TX_PACKET_ATTRIBUTES_PTP_INDEX … #define TX_PACKET_ATTRIBUTES_PTP_WIDTH … #define TX_PACKET_ATTRIBUTES_VXLAN_INDEX … #define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH … #define TX_CONTEXT_DESC2_MSS_INDEX … #define TX_CONTEXT_DESC2_MSS_WIDTH … #define TX_CONTEXT_DESC3_CTXT_INDEX … #define TX_CONTEXT_DESC3_CTXT_WIDTH … #define TX_CONTEXT_DESC3_TCMSSV_INDEX … #define TX_CONTEXT_DESC3_TCMSSV_WIDTH … #define TX_CONTEXT_DESC3_VLTV_INDEX … #define TX_CONTEXT_DESC3_VLTV_WIDTH … #define TX_CONTEXT_DESC3_VT_INDEX … #define TX_CONTEXT_DESC3_VT_WIDTH … #define TX_NORMAL_DESC2_HL_B1L_INDEX … #define TX_NORMAL_DESC2_HL_B1L_WIDTH … #define TX_NORMAL_DESC2_IC_INDEX … #define TX_NORMAL_DESC2_IC_WIDTH … #define TX_NORMAL_DESC2_TTSE_INDEX … #define TX_NORMAL_DESC2_TTSE_WIDTH … #define TX_NORMAL_DESC2_VTIR_INDEX … #define TX_NORMAL_DESC2_VTIR_WIDTH … #define TX_NORMAL_DESC3_CIC_INDEX … #define TX_NORMAL_DESC3_CIC_WIDTH … #define TX_NORMAL_DESC3_CPC_INDEX … #define TX_NORMAL_DESC3_CPC_WIDTH … #define TX_NORMAL_DESC3_CTXT_INDEX … #define TX_NORMAL_DESC3_CTXT_WIDTH … #define TX_NORMAL_DESC3_FD_INDEX … #define TX_NORMAL_DESC3_FD_WIDTH … #define TX_NORMAL_DESC3_FL_INDEX … #define TX_NORMAL_DESC3_FL_WIDTH … #define TX_NORMAL_DESC3_LD_INDEX … #define TX_NORMAL_DESC3_LD_WIDTH … #define TX_NORMAL_DESC3_OWN_INDEX … #define TX_NORMAL_DESC3_OWN_WIDTH … #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX … #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH … #define TX_NORMAL_DESC3_TCPPL_INDEX … #define TX_NORMAL_DESC3_TCPPL_WIDTH … #define TX_NORMAL_DESC3_TSE_INDEX … #define TX_NORMAL_DESC3_TSE_WIDTH … #define TX_NORMAL_DESC3_VNP_INDEX … #define TX_NORMAL_DESC3_VNP_WIDTH … #define TX_NORMAL_DESC2_VLAN_INSERT … #define TX_NORMAL_DESC3_VXLAN_PACKET … /* MDIO undefined or vendor specific registers */ #ifndef MDIO_PMA_10GBR_PMD_CTRL #define MDIO_PMA_10GBR_PMD_CTRL … #endif #ifndef MDIO_PMA_10GBR_FECCTRL #define MDIO_PMA_10GBR_FECCTRL … #endif #ifndef MDIO_PMA_RX_CTRL1 #define MDIO_PMA_RX_CTRL1 … #endif #ifndef MDIO_PMA_RX_LSTS #define MDIO_PMA_RX_LSTS … #endif #ifndef MDIO_PMA_RX_EQ_CTRL4 #define MDIO_PMA_RX_EQ_CTRL4 … #endif #ifndef MDIO_PMA_MP_MISC_STS #define MDIO_PMA_MP_MISC_STS … #endif #ifndef MDIO_PMA_PHY_RX_EQ_CEU #define MDIO_PMA_PHY_RX_EQ_CEU … #endif #ifndef MDIO_PCS_DIG_CTRL #define MDIO_PCS_DIG_CTRL … #endif #ifndef MDIO_PCS_DIGITAL_STAT #define MDIO_PCS_DIGITAL_STAT … #endif #ifndef MDIO_AN_XNP #define MDIO_AN_XNP … #endif #ifndef MDIO_AN_LPX #define MDIO_AN_LPX … #endif #ifndef MDIO_AN_COMP_STAT #define MDIO_AN_COMP_STAT … #endif #ifndef MDIO_AN_INTMASK #define MDIO_AN_INTMASK … #endif #ifndef MDIO_AN_INT #define MDIO_AN_INT … #endif #ifndef MDIO_VEND2_AN_ADVERTISE #define MDIO_VEND2_AN_ADVERTISE … #endif #ifndef MDIO_VEND2_AN_LP_ABILITY #define MDIO_VEND2_AN_LP_ABILITY … #endif #ifndef MDIO_VEND2_AN_CTRL #define MDIO_VEND2_AN_CTRL … #endif #ifndef MDIO_VEND2_AN_STAT #define MDIO_VEND2_AN_STAT … #endif #ifndef MDIO_VEND2_PMA_CDR_CONTROL #define MDIO_VEND2_PMA_CDR_CONTROL … #endif #ifndef MDIO_VEND2_PMA_MISC_CTRL0 #define MDIO_VEND2_PMA_MISC_CTRL0 … #endif #ifndef MDIO_CTRL1_SPEED1G #define MDIO_CTRL1_SPEED1G … #endif #ifndef MDIO_VEND2_CTRL1_AN_ENABLE #define MDIO_VEND2_CTRL1_AN_ENABLE … #endif #ifndef MDIO_VEND2_CTRL1_AN_RESTART #define MDIO_VEND2_CTRL1_AN_RESTART … #endif #ifndef MDIO_VEND2_CTRL1_SS6 #define MDIO_VEND2_CTRL1_SS6 … #endif #ifndef MDIO_VEND2_CTRL1_SS13 #define MDIO_VEND2_CTRL1_SS13 … #endif /* MDIO mask values */ #define XGBE_AN_CL73_INT_CMPLT … #define XGBE_AN_CL73_INC_LINK … #define XGBE_AN_CL73_PG_RCV … #define XGBE_AN_CL73_INT_MASK … #define XGBE_XNP_MCF_NULL_MESSAGE … #define XGBE_XNP_ACK_PROCESSED … #define XGBE_XNP_MP_FORMATTED … #define XGBE_XNP_NP_EXCHANGE … #define XGBE_KR_TRAINING_START … #define XGBE_KR_TRAINING_ENABLE … #define XGBE_PCS_CL37_BP … #define XGBE_PCS_PSEQ_STATE_MASK … #define XGBE_PCS_PSEQ_STATE_POWER_GOOD … #define XGBE_AN_CL37_INT_CMPLT … #define XGBE_AN_CL37_INT_MASK … #define XGBE_AN_CL37_HD_MASK … #define XGBE_AN_CL37_FD_MASK … #define XGBE_AN_CL37_PCS_MODE_MASK … #define XGBE_AN_CL37_PCS_MODE_BASEX … #define XGBE_AN_CL37_PCS_MODE_SGMII … #define XGBE_AN_CL37_TX_CONFIG_MASK … #define XGBE_AN_CL37_MII_CTRL_8BIT … #define XGBE_PMA_CDR_TRACK_EN_MASK … #define XGBE_PMA_CDR_TRACK_EN_OFF … #define XGBE_PMA_CDR_TRACK_EN_ON … #define XGBE_PMA_RX_RST_0_MASK … #define XGBE_PMA_RX_RST_0_RESET_ON … #define XGBE_PMA_RX_RST_0_RESET_OFF … #define XGBE_PMA_RX_SIG_DET_0_MASK … #define XGBE_PMA_RX_SIG_DET_0_ENABLE … #define XGBE_PMA_RX_SIG_DET_0_DISABLE … #define XGBE_PMA_RX_VALID_0_MASK … #define XGBE_PMA_RX_VALID_0_ENABLE … #define XGBE_PMA_RX_VALID_0_DISABLE … #define XGBE_PMA_RX_AD_REQ_MASK … #define XGBE_PMA_RX_AD_REQ_ENABLE … #define XGBE_PMA_RX_AD_REQ_DISABLE … #define XGBE_PMA_RX_ADPT_ACK_MASK … #define XGBE_PMA_RX_ADPT_ACK … #define XGBE_PMA_CFF_UPDTM1_VLD … #define XGBE_PMA_CFF_UPDT0_VLD … #define XGBE_PMA_CFF_UPDT1_VLD … #define XGBE_PMA_CFF_UPDT_MASK … #define XGBE_PMA_PLL_CTRL_MASK … #define XGBE_PMA_PLL_CTRL_ENABLE … #define XGBE_PMA_PLL_CTRL_DISABLE … /* Bit setting and getting macros * The get macro will extract the current bit field value from within * the variable * * The set macro will clear the current bit field value within the * variable and then set the bit field of the variable to the * specified value */ #define GET_BITS(_var, _index, _width) … #define SET_BITS(_var, _index, _width, _val) … #define GET_BITS_LE(_var, _index, _width) … #define SET_BITS_LE(_var, _index, _width, _val) … /* Bit setting and getting macros based on register fields * The get macro uses the bit field definitions formed using the input * names to extract the current bit field value from within the * variable * * The set macro uses the bit field definitions formed using the input * names to set the bit field of the variable to the specified value */ #define XGMAC_GET_BITS(_var, _prefix, _field) … #define XGMAC_SET_BITS(_var, _prefix, _field, _val) … #define XGMAC_GET_BITS_LE(_var, _prefix, _field) … #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) … /* Macros for reading or writing registers * The ioread macros will get bit fields or full values using the * register definitions formed using the input names * * The iowrite macros will set bit fields or full values using the * register definitions formed using the input names */ #define XGMAC_IOREAD(_pdata, _reg) … #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) … #define XGMAC_IOWRITE(_pdata, _reg, _val) … #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) … /* Macros for reading or writing MTL queue or traffic class registers * Similar to the standard read and write macros except that the * base register value is calculated by the queue or traffic class number */ #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) … #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) … #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) … #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) … /* Macros for reading or writing DMA channel registers * Similar to the standard read and write macros except that the * base register value is obtained from the ring */ #define XGMAC_DMA_IOREAD(_channel, _reg) … #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) … #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) … #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) … /* Macros for building, reading or writing register values or bits * within the register values of XPCS registers. */ #define XPCS_GET_BITS(_var, _prefix, _field) … #define XPCS_SET_BITS(_var, _prefix, _field, _val) … #define XPCS32_IOWRITE(_pdata, _off, _val) … #define XPCS32_IOREAD(_pdata, _off) … #define XPCS16_IOWRITE(_pdata, _off, _val) … #define XPCS16_IOREAD(_pdata, _off) … /* Macros for building, reading or writing register values or bits * within the register values of SerDes integration registers. */ #define XSIR_GET_BITS(_var, _prefix, _field) … #define XSIR_SET_BITS(_var, _prefix, _field, _val) … #define XSIR0_IOREAD(_pdata, _reg) … #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) … #define XSIR0_IOWRITE(_pdata, _reg, _val) … #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) … #define XSIR1_IOREAD(_pdata, _reg) … #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) … #define XSIR1_IOWRITE(_pdata, _reg, _val) … #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) … /* Macros for building, reading or writing register values or bits * within the register values of SerDes RxTx registers. */ #define XRXTX_IOREAD(_pdata, _reg) … #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) … #define XRXTX_IOWRITE(_pdata, _reg, _val) … #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) … /* Macros for building, reading or writing register values or bits * within the register values of MAC Control registers. */ #define XP_GET_BITS(_var, _prefix, _field) … #define XP_SET_BITS(_var, _prefix, _field, _val) … #define XP_IOREAD(_pdata, _reg) … #define XP_IOREAD_BITS(_pdata, _reg, _field) … #define XP_IOWRITE(_pdata, _reg, _val) … #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) … /* Macros for building, reading or writing register values or bits * within the register values of I2C Control registers. */ #define XI2C_GET_BITS(_var, _prefix, _field) … #define XI2C_SET_BITS(_var, _prefix, _field, _val) … #define XI2C_IOREAD(_pdata, _reg) … #define XI2C_IOREAD_BITS(_pdata, _reg, _field) … #define XI2C_IOWRITE(_pdata, _reg, _val) … #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) … /* Macros for building, reading or writing register values or bits * using MDIO. */ #define XGBE_ADDR_C45 … #define XMDIO_READ(_pdata, _mmd, _reg) … #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) … #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) … #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) … #endif
Codebase Browser
linux