/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Advanced Micro Devices Inc. AMD8111E Linux Network Driver * Copyright (C) 2003 Advanced Micro Devices * Module Name: amd8111e.h Abstract: AMD8111 based 10/100 Ethernet Controller driver definitions. Environment: Kernel Mode Revision History: 3.0.0 Initial Revision. 3.0.1 */ #ifndef _AMD811E_H #define _AMD811E_H /* Command style register access Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register. eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered. */ /* Offset for Memory Mapped Registers. */ /* 32 bit registers */ #define ASF_STAT … #define CHIPID … #define MIB_DATA … #define MIB_ADDR … #define STAT0 … #define INT0 … #define INTEN0 … #define CMD0 … #define CMD2 … #define CMD3 … #define CMD7 … #define CTRL1 … #define CTRL2 … #define XMT_RING_LIMIT … #define AUTOPOLL0 … #define AUTOPOLL1 … #define AUTOPOLL2 … #define AUTOPOLL3 … #define AUTOPOLL4 … #define AUTOPOLL5 … #define AP_VALUE … #define DLY_INT_A … #define DLY_INT_B … #define FLOW_CONTROL … #define PHY_ACCESS … #define STVAL … #define XMT_RING_BASE_ADDR0 … #define XMT_RING_BASE_ADDR1 … #define XMT_RING_BASE_ADDR2 … #define XMT_RING_BASE_ADDR3 … #define RCV_RING_BASE_ADDR0 … #define PMAT0 … #define PMAT1 … /* 16bit registers */ #define XMT_RING_LEN0 … #define XMT_RING_LEN1 … #define XMT_RING_LEN2 … #define XMT_RING_LEN3 … #define RCV_RING_LEN0 … #define SRAM_SIZE … #define SRAM_BOUNDARY … /* 48bit register */ #define PADR … #define IFS1 … #define IFS … #define IPG … /* 64bit register */ #define LADRF … /* Register Bit Definitions */ STAT_ASF_BITS; MIB_ADDR_BITS; STAT0_BITS; #define PHY_SPEED_10 … #define PHY_SPEED_100 … /* INT0 0x38, 32bit register */ INT0_BITS; VAL_BITS; INTEN0_BITS; CMD0_BITS; CMD2_BITS; CMD3_BITS; CMD7_BITS; CTRL1_BITS; CTRL2_BITS; /* XMT_RING_LIMIT 0x7C, 32bit register */ XMT_RING_LIMIT_BITS; AUTOPOLL0_BITS; /* AUTOPOLL1 0x8A, 16bit register */ AUTOPOLL1_BITS; AUTOPOLL2_BITS; AUTOPOLL3_BITS; AUTOPOLL4_BITS; AUTOPOLL5_BITS; /* AP_VALUE 0x98, 32bit ragister */ AP_VALUE_BITS; DLY_INT_A_BITS; DLY_INT_B_BITS; /* FLOW_CONTROL 0xC8, 32bit register */ FLOW_CONTROL_BITS; /* PHY_ ACCESS 0xD0, 32bit register */ PHY_ACCESS_BITS; /* PMAT0 0x190, 32bit register */ PMAT0_BITS; /* PMAT1 0x194, 32bit register */ PMAT1_BITS; /************************************************************************/ /* */ /* MIB counter definitions */ /* */ /************************************************************************/ #define rcv_miss_pkts … #define rcv_octets … #define rcv_broadcast_pkts … #define rcv_multicast_pkts … #define rcv_undersize_pkts … #define rcv_oversize_pkts … #define rcv_fragments … #define rcv_jabbers … #define rcv_unicast_pkts … #define rcv_alignment_errors … #define rcv_fcs_errors … #define rcv_good_octets … #define rcv_mac_ctrl … #define rcv_flow_ctrl … #define rcv_pkts_64_octets … #define rcv_pkts_65to127_octets … #define rcv_pkts_128to255_octets … #define rcv_pkts_256to511_octets … #define rcv_pkts_512to1023_octets … #define rcv_pkts_1024to1518_octets … #define rcv_unsupported_opcode … #define rcv_symbol_errors … #define rcv_drop_pkts_ring1 … #define rcv_drop_pkts_ring2 … #define rcv_drop_pkts_ring3 … #define rcv_drop_pkts_ring4 … #define rcv_jumbo_pkts … #define xmt_underrun_pkts … #define xmt_octets … #define xmt_packets … #define xmt_broadcast_pkts … #define xmt_multicast_pkts … #define xmt_collisions … #define xmt_unicast_pkts … #define xmt_one_collision … #define xmt_multiple_collision … #define xmt_deferred_transmit … #define xmt_late_collision … #define xmt_excessive_defer … #define xmt_loss_carrier … #define xmt_excessive_collision … #define xmt_back_pressure … #define xmt_flow_ctrl … #define xmt_pkts_64_octets … #define xmt_pkts_65to127_octets … #define xmt_pkts_128to255_octets … #define xmt_pkts_256to511_octets … #define xmt_pkts_512to1023_octets … #define xmt_pkts_1024to1518_octet … #define xmt_oversize_pkts … #define xmt_jumbo_pkts … /* Driver definitions */ #define PCI_VENDOR_ID_AMD … #define PCI_DEVICE_ID_AMD8111E_7462 … #define MAX_UNITS … #define NUM_TX_BUFFERS … #define NUM_RX_BUFFERS … #define TX_BUFF_MOD_MASK … #define RX_BUFF_MOD_MASK … #define NUM_TX_RING_DR … #define NUM_RX_RING_DR … #define TX_RING_DR_MOD_MASK … #define RX_RING_DR_MOD_MASK … #define MAX_FILTER_SIZE … #define AMD8111E_MIN_MTU … #define AMD8111E_MAX_MTU … #define PKT_BUFF_SZ … #define MIN_PKT_LEN … #define AMD8111E_TX_TIMEOUT … #define SOFT_TIMER_FREQ … #define DELAY_TIMER_CONV … #define OPTION_VLAN_ENABLE … #define OPTION_JUMBO_ENABLE … #define OPTION_MULTICAST_ENABLE … #define OPTION_WOL_ENABLE … #define OPTION_WAKE_MAGIC_ENABLE … #define OPTION_WAKE_PHY_ENABLE … #define OPTION_INTR_COAL_ENABLE … #define OPTION_DYN_IPG_ENABLE … #define PHY_REG_ADDR_MASK … /* ipg parameters */ #define DEFAULT_IPG … #define IFS1_DELTA … #define IPG_CONVERGE_JIFFIES … #define IPG_STABLE_TIME … #define MIN_IPG … #define MAX_IPG … #define IPG_STEP … #define CSTATE … #define SSTATE … /* Assume controller gets data 10 times the maximum processing time */ #define REPEAT_CNT … /* amd8111e descriptor flag definitions */ TX_FLAG_BITS; RX_FLAG_BITS; #define RESET_RX_FLAGS … #define TT_MASK … #define TCC_MASK … /* driver ioctl parameters */ #define AMD8111E_REG_DUMP_LEN … /* amd8111e descriptor format */ struct amd8111e_tx_dr{ … }; struct amd8111e_rx_dr{ … }; struct amd8111e_link_config{ … }; enum coal_type{ … }; enum coal_mode{ … }; #define MAX_TIMEOUT … #define MAX_EVENT_COUNT … struct amd8111e_coalesce_conf{ … }; struct ipg_info{ … }; struct amd8111e_priv{ … }; /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register. BUG? */ #define amd8111e_writeq(_UlData,_memMap) … /* maps the external speed options to internal value */ EXT_PHY_OPTION; static int card_idx; static int speed_duplex[MAX_UNITS] = …; static bool coalesce[MAX_UNITS] = …; static bool dynamic_ipg[MAX_UNITS] = …; static unsigned int chip_version; #endif /* _AMD8111E_H */
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