/* SPDX-License-Identifier: GPL-2.0-only */ /* Atlantic Network Driver * * Copyright (C) 2014-2019 aQuantia Corporation * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware * abstraction layer. */ #ifndef HW_ATL_UTILS_H #define HW_ATL_UTILS_H #define HW_ATL_FLUSH() … /* Hardware tx descriptor */ struct __packed hw_atl_txd_s { … }; /* Hardware tx context descriptor */ struct __packed hw_atl_txc_s { … }; /* Hardware rx descriptor */ struct __packed hw_atl_rxd_s { … }; /* Hardware rx descriptor writeback */ struct __packed hw_atl_rxd_wb_s { … }; /* Hardware rx HW TIMESTAMP writeback */ struct __packed hw_atl_rxd_hwts_wb_s { … }; struct __packed hw_atl_stats_s { … }; struct __packed drv_msg_enable_wakeup { … }; struct __packed magic_packet_pattern_s { … }; struct __packed drv_msg_wol_add { … }; struct __packed drv_msg_wol_remove { … }; struct __packed hw_atl_utils_mbox_header { … }; struct __packed hw_atl_ptp_offset { … }; struct __packed hw_atl_cable_diag { … }; enum gpio_pin_function { … }; struct __packed hw_atl_info { … }; struct __packed hw_atl_utils_mbox { … }; struct __packed offload_ip_info { … }; struct __packed offload_port_info { … }; struct __packed offload_ka_info { … }; struct __packed offload_rr_info { … }; struct __packed offload_info { … }; struct __packed hw_atl_utils_fw_rpc { … }; /* Mailbox FW Request interface */ struct __packed hw_fw_request_ptp_gpio_ctrl { … }; struct __packed hw_fw_request_ptp_adj_freq { … }; struct __packed hw_fw_request_ptp_adj_clock { … }; #define HW_AQ_FW_REQUEST_PTP_GPIO_CTRL … #define HW_AQ_FW_REQUEST_PTP_ADJ_FREQ … #define HW_AQ_FW_REQUEST_PTP_ADJ_CLOCK … struct __packed hw_fw_request_iface { … }; struct __packed hw_atl_utils_settings { … }; enum macsec_msg_type { … }; struct __packed macsec_cfg_request { … }; struct __packed macsec_msg_fw_request { … }; struct __packed macsec_msg_fw_response { … }; enum hw_atl_rx_action_with_traffic { … }; struct aq_rx_filter_vlan { … }; #define HW_ATL_VLAN_MAX_FILTERS … struct aq_rx_filter_l2 { … }; struct aq_rx_filter_l3l4 { … }; enum hw_atl_rx_protocol_value_l3l4 { … }; enum hw_atl_rx_ctrl_registers_l3l4 { … }; #define HW_ATL_RX_QUEUE_FL3L4_SHIFT … #define HW_ATL_RX_ACTION_FL3F4_SHIFT … #define HW_ATL_RX_CNT_REG_ADDR_IPV6 … #define HW_ATL_GET_REG_LOCATION_FL3L4(location) … enum hal_atl_utils_fw_state_e { … }; #define HAL_ATLANTIC_RATE_10G … #define HAL_ATLANTIC_RATE_5G … #define HAL_ATLANTIC_RATE_5GSR … #define HAL_ATLANTIC_RATE_2G5 … #define HAL_ATLANTIC_RATE_1G … #define HAL_ATLANTIC_RATE_100M … #define HAL_ATLANTIC_RATE_INVALID … #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD … #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR … #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN … #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT … #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL … #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP … enum hw_atl_fw2x_rate { … }; /* 0x370 * Link capabilities resolution register */ enum hw_atl_fw2x_caps_lo { … }; /* 0x374 * Status register */ enum hw_atl_fw2x_caps_hi { … }; /* 0x36C * Control register */ enum hw_atl_fw2x_ctrl { … }; enum hw_atl_caps_ex { … }; struct aq_hw_s; struct aq_fw_ops; struct aq_hw_caps_s; struct aq_hw_link_status_s; int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); int hw_atl_utils_soft_reset(struct aq_hw_s *self); void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, struct hw_atl_utils_mbox_header *pmbox); void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, struct hw_atl_utils_mbox *pmbox); void hw_atl_utils_mpi_set(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state, u32 speed); int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, u8 *mac); unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps); int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, const struct aq_hw_caps_s *aq_hw_caps, u32 *regs_buff); int hw_atl_utils_hw_set_power(struct aq_hw_s *self, unsigned int power_state); int hw_atl_utils_hw_deinit(struct aq_hw_s *self); u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self); int hw_atl_utils_update_stats(struct aq_hw_s *self); struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, u32 *p, u32 cnt); int hw_atl_write_fwcfg_dwords(struct aq_hw_s *self, u32 *p, u32 cnt); int hw_atl_write_fwsettings_dwords(struct aq_hw_s *self, u32 offset, u32 *p, u32 cnt); int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac); int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, struct hw_atl_utils_fw_rpc **rpc); bool hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); extern const struct aq_fw_ops aq_fw_1x_ops; extern const struct aq_fw_ops aq_fw_2x_ops; #endif /* HW_ATL_UTILS_H */
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