/* SPDX-License-Identifier: GPL-2.0-only */ /* Atlantic Network Driver * * Copyright (C) 2014-2019 aQuantia Corporation * Copyright (C) 2019-2020 Marvell International Ltd. */ /* File hw_atl_llh_internal.h: Preprocessor definitions * for Atlantic registers. */ #ifndef HW_ATL_LLH_INTERNAL_H #define HW_ATL_LLH_INTERNAL_H /* COM Temperature Sense Reset Bitfield Definitions */ #define HW_ATL_TS_RESET_ADR … #define HW_ATL_TS_RESET_MSK … #define HW_ATL_TS_RESET_SHIFT … #define HW_ATL_TS_RESET_WIDTH … /* COM Temperature Sense Power Down Bitfield Definitions */ #define HW_ATL_TS_POWER_DOWN_ADR … #define HW_ATL_TS_POWER_DOWN_MSK … #define HW_ATL_TS_POWER_DOWN_SHIFT … #define HW_ATL_TS_POWER_DOWN_WIDTH … /* COM Temperature Sense Ready Bitfield Definitions */ #define HW_ATL_TS_READY_ADR … #define HW_ATL_TS_READY_MSK … #define HW_ATL_TS_READY_SHIFT … #define HW_ATL_TS_READY_WIDTH … /* COM Temperature Sense Ready Latch High Bitfield Definitions */ #define HW_ATL_TS_READY_LATCH_HIGH_ADR … #define HW_ATL_TS_READY_LATCH_HIGH_MSK … #define HW_ATL_TS_READY_LATCH_HIGH_SHIFT … #define HW_ATL_TS_READY_LATCH_HIGH_WIDTH … /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */ #define HW_ATL_TS_DATA_OUT_ADR … #define HW_ATL_TS_DATA_OUT_MSK … #define HW_ATL_TS_DATA_OUT_SHIFT … #define HW_ATL_TS_DATA_OUT_WIDTH … /* global microprocessor semaphore definitions * base address: 0x000003a0 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] */ #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) … /* register address for bitfield rx dma good octet counter lsw [1f:0] */ #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW … /* register address for bitfield rx dma good packet counter lsw [1f:0] */ #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW … /* register address for bitfield tx dma good octet counter lsw [1f:0] */ #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW … /* register address for bitfield tx dma good packet counter lsw [1f:0] */ #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW … /* register address for bitfield rx dma good octet counter msw [3f:20] */ #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW … /* register address for bitfield rx dma good packet counter msw [3f:20] */ #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW … /* register address for bitfield tx dma good octet counter msw [3f:20] */ #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW … /* register address for bitfield tx dma good packet counter msw [3f:20] */ #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW … /* preprocessor definitions for msm rx errors counter register */ #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR … /* preprocessor definitions for msm rx unicast frames counter register */ #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR … /* preprocessor definitions for msm rx multicast frames counter register */ #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR … /* preprocessor definitions for msm rx broadcast frames counter register */ #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR … /* preprocessor definitions for msm rx broadcast octets counter register 1 */ #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR … /* preprocessor definitions for msm rx broadcast octets counter register 2 */ #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR … /* preprocessor definitions for msm rx unicast octets counter register 0 */ #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR … /* preprocessor definitions for msm tx unicast frames counter register */ #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR … /* preprocessor definitions for msm tx multicast frames counter register */ #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR … /* preprocessor definitions for global mif identification */ #define HW_ATL_GLB_MIF_ID_ADR … /* register address for bitfield iamr_lsw[1f:0] */ #define HW_ATL_ITR_IAMRLSW_ADR … /* register address for bitfield rx dma drop packet counter [1f:0] */ #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR … /* register address for bitfield imcr_lsw[1f:0] */ #define HW_ATL_ITR_IMCRLSW_ADR … /* register address for bitfield imsr_lsw[1f:0] */ #define HW_ATL_ITR_IMSRLSW_ADR … /* register address for bitfield itr_reg_res_dsbl */ #define HW_ATL_ITR_REG_RES_DSBL_ADR … /* bitmask for bitfield itr_reg_res_dsbl */ #define HW_ATL_ITR_REG_RES_DSBL_MSK … /* lower bit position of bitfield itr_reg_res_dsbl */ #define HW_ATL_ITR_REG_RES_DSBL_SHIFT … /* register address for bitfield iscr_lsw[1f:0] */ #define HW_ATL_ITR_ISCRLSW_ADR … /* register address for bitfield isr_lsw[1f:0] */ #define HW_ATL_ITR_ISRLSW_ADR … /* register address for bitfield itr_reset */ #define HW_ATL_ITR_RES_ADR … /* bitmask for bitfield itr_reset */ #define HW_ATL_ITR_RES_MSK … /* lower bit position of bitfield itr_reset */ #define HW_ATL_ITR_RES_SHIFT … /* register address for bitfield rsc_en */ #define HW_ATL_ITR_RSC_EN_ADR … /* register address for bitfield rsc_delay */ #define HW_ATL_ITR_RSC_DELAY_ADR … /* bitmask for bitfield rsc_delay */ #define HW_ATL_ITR_RSC_DELAY_MSK … /* width of bitfield rsc_delay */ #define HW_ATL_ITR_RSC_DELAY_WIDTH … /* lower bit position of bitfield rsc_delay */ #define HW_ATL_ITR_RSC_DELAY_SHIFT … /* register address for bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_RDM_DCADCPUID_ADR(dca) … /* bitmask for bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_RDM_DCADCPUID_MSK … /* lower bit position of bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_RDM_DCADCPUID_SHIFT … /* register address for bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_ADR … /* rx dca_en bitfield definitions * preprocessor definitions for the bitfield "dca_en". * port="pif_rdm_dca_en_i" */ /* register address for bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_ADR … /* bitmask for bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_MSK … /* inverted bitmask for bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_MSKN … /* lower bit position of bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_SHIFT … /* width of bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_WIDTH … /* default value of bitfield dca_en */ #define HW_ATL_RDM_DCA_EN_DEFAULT … /* rx dca_mode[3:0] bitfield definitions * preprocessor definitions for the bitfield "dca_mode[3:0]". * port="pif_rdm_dca_mode_i[3:0]" */ /* register address for bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_ADR … /* bitmask for bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_MSK … /* inverted bitmask for bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_MSKN … /* lower bit position of bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_SHIFT … /* width of bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_WIDTH … /* default value of bitfield dca_mode[3:0] */ #define HW_ATL_RDM_DCA_MODE_DEFAULT … /* rx desc{d}_data_size[4:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_desc0_data_size_i[4:0]" */ /* register address for bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) … /* bitmask for bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_MSK … /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN … /* lower bit position of bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT … /* width of bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH … /* default value of bitfield desc{d}_data_size[4:0] */ #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT … /* rx dca{d}_desc_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_desc_en". * parameter: dca {d} | stride size 0x4 | range [0, 31] * port="pif_rdm_dca_desc_en_i[0]" */ /* register address for bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) … /* bitmask for bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_MSK … /* inverted bitmask for bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_MSKN … /* lower bit position of bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_SHIFT … /* width of bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_WIDTH … /* default value of bitfield dca{d}_desc_en */ #define HW_ATL_RDM_DCADDESC_EN_DEFAULT … /* rx desc{d}_en bitfield definitions * preprocessor definitions for the bitfield "desc{d}_en". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_desc_en_i[0]" */ /* register address for bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_ADR(descriptor) … /* bitmask for bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_MSK … /* inverted bitmask for bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_MSKN … /* lower bit position of bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_SHIFT … /* width of bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_WIDTH … /* default value of bitfield desc{d}_en */ #define HW_ATL_RDM_DESCDEN_DEFAULT … /* rx desc{d}_hdr_size[4:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_desc0_hdr_size_i[4:0]" */ /* register address for bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) … /* bitmask for bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_MSK … /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN … /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT … /* width of bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH … /* default value of bitfield desc{d}_hdr_size[4:0] */ #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT … /* rx desc{d}_hdr_split bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hdr_split". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_desc_hdr_split_i[0]" */ /* register address for bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) … /* bitmask for bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK … /* inverted bitmask for bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN … /* lower bit position of bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT … /* width of bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH … /* default value of bitfield desc{d}_hdr_split */ #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT … /* rx desc{d}_hd[c:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="rdm_pif_desc0_hd_o[12:0]" */ /* register address for bitfield desc{d}_hd[c:0] */ #define HW_ATL_RDM_DESCDHD_ADR(descriptor) … /* bitmask for bitfield desc{d}_hd[c:0] */ #define HW_ATL_RDM_DESCDHD_MSK … /* inverted bitmask for bitfield desc{d}_hd[c:0] */ #define HW_ATL_RDM_DESCDHD_MSKN … /* lower bit position of bitfield desc{d}_hd[c:0] */ #define HW_ATL_RDM_DESCDHD_SHIFT … /* width of bitfield desc{d}_hd[c:0] */ #define HW_ATL_RDM_DESCDHD_WIDTH … /* rx desc{d}_len[9:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_len[9:0]". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_desc0_len_i[9:0]" */ /* register address for bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) … /* bitmask for bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_MSK … /* inverted bitmask for bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_MSKN … /* lower bit position of bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_SHIFT … /* width of bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_WIDTH … /* default value of bitfield desc{d}_len[9:0] */ #define HW_ATL_RDM_DESCDLEN_DEFAULT … /* rx desc{d}_reset bitfield definitions * preprocessor definitions for the bitfield "desc{d}_reset". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rdm_q_pf_res_i[0]" */ /* register address for bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) … /* bitmask for bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_MSK … /* inverted bitmask for bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_MSKN … /* lower bit position of bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_SHIFT … /* width of bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_WIDTH … /* default value of bitfield desc{d}_reset */ #define HW_ATL_RDM_DESCDRESET_DEFAULT … /* rdm_desc_init_i bitfield definitions * preprocessor definitions for the bitfield rdm_desc_init_i. * port="pif_rdm_desc_init_i" */ /* register address for bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR … /* bitmask for bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK … /* inverted bitmask for bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN … /* lower bit position of bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT … /* width of bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH … /* default value of bitfield rdm_desc_init_i */ #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT … /* rdm_desc_init_done_i bitfield definitions * preprocessor definitions for the bitfield rdm_desc_init_done_i. * port="pif_rdm_desc_init_done_i" */ /* register address for bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR … /* bitmask for bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK … /* inverted bitmask for bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN … /* lower bit position of bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT … /* width of bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH … /* default value of bitfield rdm_desc_init_done_i */ #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT … /* rx int_desc_wrb_en bitfield definitions * preprocessor definitions for the bitfield "int_desc_wrb_en". * port="pif_rdm_int_desc_wrb_en_i" */ /* register address for bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR … /* bitmask for bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK … /* inverted bitmask for bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN … /* lower bit position of bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT … /* width of bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH … /* default value of bitfield int_desc_wrb_en */ #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT … /* rx dca{d}_hdr_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_hdr_en". * parameter: dca {d} | stride size 0x4 | range [0, 31] * port="pif_rdm_dca_hdr_en_i[0]" */ /* register address for bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) … /* bitmask for bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_MSK … /* inverted bitmask for bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_MSKN … /* lower bit position of bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_SHIFT … /* width of bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_WIDTH … /* default value of bitfield dca{d}_hdr_en */ #define HW_ATL_RDM_DCADHDR_EN_DEFAULT … /* rx dca{d}_pay_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_pay_en". * parameter: dca {d} | stride size 0x4 | range [0, 31] * port="pif_rdm_dca_pay_en_i[0]" */ /* register address for bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) … /* bitmask for bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_MSK … /* inverted bitmask for bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_MSKN … /* lower bit position of bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_SHIFT … /* width of bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_WIDTH … /* default value of bitfield dca{d}_pay_en */ #define HW_ATL_RDM_DCADPAY_EN_DEFAULT … /* RX rdm_int_rim_en Bitfield Definitions * Preprocessor definitions for the bitfield "rdm_int_rim_en". * PORT="pif_rdm_int_rim_en_i" */ /* Register address for bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_ADR … /* Bitmask for bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_MSK … /* Inverted bitmask for bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_MSKN … /* Lower bit position of bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_SHIFT … /* Width of bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_WIDTH … /* Default value of bitfield rdm_int_rim_en */ #define HW_ATL_RDM_INT_RIM_EN_DEFAULT … /* general interrupt mapping register definitions * preprocessor definitions for general interrupt mapping register * base address: 0x00002180 * parameter: regidx {f} | stride size 0x4 | range [0, 3] */ #define HW_ATL_GEN_INTR_MAP_ADR(regidx) … /* general interrupt status register definitions * preprocessor definitions for general interrupt status register * address: 0x000021A0 */ #define HW_ATL_GEN_INTR_STAT_ADR … /* interrupt global control register definitions * preprocessor definitions for interrupt global control register * address: 0x00002300 */ #define HW_ATL_INTR_GLB_CTL_ADR … /* interrupt throttle register definitions * preprocessor definitions for interrupt throttle register * base address: 0x00002800 * parameter: throttle {t} | stride size 0x4 | range [0, 31] */ #define HW_ATL_INTR_THR_ADR(throttle) … /* rx dma descriptor base address lsw definitions * preprocessor definitions for rx dma descriptor base address lsw * base address: 0x00005b00 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) … /* rx dma descriptor base address msw definitions * preprocessor definitions for rx dma descriptor base address msw * base address: 0x00005b04 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) … /* rx dma descriptor status register definitions * preprocessor definitions for rx dma descriptor status register * base address: 0x00005b14 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) … /* rx dma descriptor tail pointer register definitions * preprocessor definitions for rx dma descriptor tail pointer register * base address: 0x00005b10 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] */ #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) … /* rx interrupt moderation control register definitions * Preprocessor definitions for RX Interrupt Moderation Control Register * Base Address: 0x00005A40 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] */ #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) … /* rx filter multicast filter mask register definitions * preprocessor definitions for rx filter multicast filter mask register * address: 0x00005270 */ #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR … /* rx filter multicast filter register definitions * preprocessor definitions for rx filter multicast filter register * base address: 0x00005250 * parameter: filter {f} | stride size 0x4 | range [0, 7] */ #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) … /* RX Filter RSS Control Register 1 Definitions * Preprocessor definitions for RX Filter RSS Control Register 1 * Address: 0x000054C0 */ #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR … /* RX Filter Control Register 2 Definitions * Preprocessor definitions for RX Filter Control Register 2 * Address: 0x00005104 */ #define HW_ATL_RX_FLR_CONTROL2_ADR … /* tx tx dma debug control [1f:0] bitfield definitions * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". * port="pif_tdm_debug_cntl_i[31:0]" */ /* register address for bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR … /* bitmask for bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK … /* inverted bitmask for bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN … /* lower bit position of bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT … /* width of bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH … /* default value of bitfield tx dma debug control [1f:0] */ #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT … /* tx dma descriptor base address lsw definitions * preprocessor definitions for tx dma descriptor base address lsw * base address: 0x00007c00 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] */ #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) … /* tx dma descriptor tail pointer register definitions * preprocessor definitions for tx dma descriptor tail pointer register * base address: 0x00007c10 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] */ #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) … /* rx dma_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_sys_loopback". * port="pif_rpb_dma_sys_lbk_i" */ /* register address for bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_ADR … /* bitmask for bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_MSK … /* inverted bitmask for bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_MSKN … /* lower bit position of bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT … /* width of bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH … /* default value of bitfield dma_sys_loopback */ #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT … /* rx dma_net_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_net_loopback". * port="pif_rpb_dma_net_lbk_i" */ /* register address for bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_ADR … /* bitmask for bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_MSK … /* inverted bitmask for bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_MSKN … /* lower bit position of bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_SHIFT … /* width of bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_WIDTH … /* default value of bitfield dma_net_loopback */ #define HW_ATL_RPB_DMA_NET_LBK_DEFAULT … /* rx rx_tc_mode bitfield definitions * preprocessor definitions for the bitfield "rx_tc_mode". * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" */ /* register address for bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR … /* bitmask for bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK … /* inverted bitmask for bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN … /* lower bit position of bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT … /* width of bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH … /* default value of bitfield rx_tc_mode */ #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT … /* rx rx_buf_en bitfield definitions * preprocessor definitions for the bitfield "rx_buf_en". * port="pif_rpb_rx_buf_en_i" */ /* register address for bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_ADR … /* bitmask for bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_MSK … /* inverted bitmask for bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_MSKN … /* lower bit position of bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_SHIFT … /* width of bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_WIDTH … /* default value of bitfield rx_buf_en */ #define HW_ATL_RPB_RX_BUF_EN_DEFAULT … /* rx rx{b}_hi_thresh[d:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_rpb_rx0_hi_thresh_i[13:0]" */ /* register address for bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) … /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_MSK … /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_MSKN … /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_SHIFT … /* width of bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_WIDTH … /* default value of bitfield rx{b}_hi_thresh[d:0] */ #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT … /* rx rx{b}_lo_thresh[d:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_rpb_rx0_lo_thresh_i[13:0]" */ /* register address for bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) … /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_MSK … /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_MSKN … /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_SHIFT … /* width of bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_WIDTH … /* default value of bitfield rx{b}_lo_thresh[d:0] */ #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT … /* rx rx_fc_mode[1:0] bitfield definitions * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". * port="pif_rpb_rx_fc_mode_i[1:0]" */ /* register address for bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_ADR … /* bitmask for bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_MSK … /* inverted bitmask for bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_MSKN … /* lower bit position of bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_SHIFT … /* width of bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_WIDTH … /* default value of bitfield rx_fc_mode[1:0] */ #define HW_ATL_RPB_RX_FC_MODE_DEFAULT … /* rx rx{b}_buf_size[8:0] bitfield definitions * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_rpb_rx0_buf_size_i[8:0]" */ /* register address for bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) … /* bitmask for bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_MSK … /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_MSKN … /* lower bit position of bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT … /* width of bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH … /* default value of bitfield rx{b}_buf_size[8:0] */ #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT … /* rx rx{b}_xoff_en bitfield definitions * preprocessor definitions for the bitfield "rx{b}_xoff_en". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_rpb_rx_xoff_en_i[0]" */ /* register address for bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) … /* bitmask for bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_MSK … /* inverted bitmask for bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_MSKN … /* lower bit position of bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_SHIFT … /* width of bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_WIDTH … /* default value of bitfield rx{b}_xoff_en */ #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT … /* rx l2_bc_thresh[f:0] bitfield definitions * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". * port="pif_rpf_l2_bc_thresh_i[15:0]" */ /* register address for bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_ADR … /* bitmask for bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_MSK … /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_MSKN … /* lower bit position of bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_SHIFT … /* width of bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_WIDTH … /* default value of bitfield l2_bc_thresh[f:0] */ #define HW_ATL_RPFL2BC_THRESH_DEFAULT … /* rx l2_bc_en bitfield definitions * preprocessor definitions for the bitfield "l2_bc_en". * port="pif_rpf_l2_bc_en_i" */ /* register address for bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_ADR … /* bitmask for bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_MSK … /* inverted bitmask for bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_MSKN … /* lower bit position of bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_SHIFT … /* width of bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_WIDTH … /* default value of bitfield l2_bc_en */ #define HW_ATL_RPFL2BC_EN_DEFAULT … /* rx l2_bc_act[2:0] bitfield definitions * preprocessor definitions for the bitfield "l2_bc_act[2:0]". * port="pif_rpf_l2_bc_act_i[2:0]" */ /* register address for bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_ADR … /* bitmask for bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_MSK … /* inverted bitmask for bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_MSKN … /* lower bit position of bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_SHIFT … /* width of bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_WIDTH … /* default value of bitfield l2_bc_act[2:0] */ #define HW_ATL_RPFL2BC_ACT_DEFAULT … /* rx l2_mc_en{f} bitfield definitions * preprocessor definitions for the bitfield "l2_mc_en{f}". * parameter: filter {f} | stride size 0x4 | range [0, 7] * port="pif_rpf_l2_mc_en_i[0]" */ /* register address for bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_ADR(filter) … /* bitmask for bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_MSK … /* inverted bitmask for bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_MSKN … /* lower bit position of bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_SHIFT … /* width of bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_WIDTH … /* default value of bitfield l2_mc_en{f} */ #define HW_ATL_RPFL2MC_ENF_DEFAULT … /* rx l2_promis_mode bitfield definitions * preprocessor definitions for the bitfield "l2_promis_mode". * port="pif_rpf_l2_promis_mode_i" */ /* register address for bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_ADR … /* bitmask for bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_MSK … /* inverted bitmask for bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_MSKN … /* lower bit position of bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_SHIFT … /* width of bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_WIDTH … /* default value of bitfield l2_promis_mode */ #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT … /* rx l2_uc_act{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". * parameter: filter {f} | stride size 0x8 | range [0, 37] * port="pif_rpf_l2_uc_act0_i[2:0]" */ /* register address for bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_ADR(filter) … /* bitmask for bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_MSK … /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_MSKN … /* lower bit position of bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_SHIFT … /* width of bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_WIDTH … /* default value of bitfield l2_uc_act{f}[2:0] */ #define HW_ATL_RPFL2UC_ACTF_DEFAULT … /* rx l2_uc_en{f} bitfield definitions * preprocessor definitions for the bitfield "l2_uc_en{f}". * parameter: filter {f} | stride size 0x8 | range [0, 37] * port="pif_rpf_l2_uc_en_i[0]" */ /* register address for bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_ADR(filter) … /* bitmask for bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_MSK … /* inverted bitmask for bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_MSKN … /* lower bit position of bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_SHIFT … /* width of bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_WIDTH … /* default value of bitfield l2_uc_en{f} */ #define HW_ATL_RPFL2UC_ENF_DEFAULT … /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) … /* register address for bitfield l2_uc_da{f}_msw[f:0] */ #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) … /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ #define HW_ATL_RPFL2UC_DAFMSW_MSK … /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ #define HW_ATL_RPFL2UC_DAFMSW_SHIFT … /* rx l2_mc_accept_all bitfield definitions * Preprocessor definitions for the bitfield "l2_mc_accept_all". * PORT="pif_rpf_l2_mc_all_accept_i" */ /* Register address for bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR … /* Bitmask for bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK … /* Inverted bitmask for bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN … /* Lower bit position of bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT … /* Width of bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH … /* Default value of bitfield l2_mc_accept_all */ #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT … /* width of bitfield rx_tc_up{t}[2:0] */ #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH … /* default value of bitfield rx_tc_up{t}[2:0] */ #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT … /* rx rss_key_addr[4:0] bitfield definitions * preprocessor definitions for the bitfield "rss_key_addr[4:0]". * port="pif_rpf_rss_key_addr_i[4:0]" */ /* register address for bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_ADR … /* bitmask for bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_MSK … /* inverted bitmask for bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN … /* lower bit position of bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT … /* width of bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH … /* default value of bitfield rss_key_addr[4:0] */ #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT … /* rx rss_key_wr_data[1f:0] bitfield definitions * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". * port="pif_rpf_rss_key_wr_data_i[31:0]" */ /* register address for bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR … /* bitmask for bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK … /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN … /* lower bit position of bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT … /* width of bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH … /* default value of bitfield rss_key_wr_data[1f:0] */ #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT … /* rx rss_key_wr_en_i bitfield definitions * preprocessor definitions for the bitfield "rss_key_wr_en_i". * port="pif_rpf_rss_key_wr_en_i" */ /* register address for bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR … /* bitmask for bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK … /* inverted bitmask for bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN … /* lower bit position of bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT … /* width of bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH … /* default value of bitfield rss_key_wr_en_i */ #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT … /* rx rss_redir_addr[3:0] bitfield definitions * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". * port="pif_rpf_rss_redir_addr_i[3:0]" */ /* register address for bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR … /* bitmask for bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK … /* inverted bitmask for bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN … /* lower bit position of bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT … /* width of bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH … /* default value of bitfield rss_redir_addr[3:0] */ #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT … /* rx rss_redir_wr_data[f:0] bitfield definitions * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". * port="pif_rpf_rss_redir_wr_data_i[15:0]" */ /* register address for bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR … /* bitmask for bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK … /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN … /* lower bit position of bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT … /* width of bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH … /* default value of bitfield rss_redir_wr_data[f:0] */ #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT … /* rx rss_redir_wr_en_i bitfield definitions * preprocessor definitions for the bitfield "rss_redir_wr_en_i". * port="pif_rpf_rss_redir_wr_en_i" */ /* register address for bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR … /* bitmask for bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK … /* inverted bitmask for bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN … /* lower bit position of bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT … /* width of bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH … /* default value of bitfield rss_redir_wr_en_i */ #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT … /* rx tpo_rpf_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". * port="pif_rpf_tpo_pkt_sys_lbk_i" */ /* register address for bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR … /* bitmask for bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK … /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN … /* lower bit position of bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT … /* width of bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH … /* default value of bitfield tpo_rpf_sys_loopback */ #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT … /* rx vl_inner_tpid[f:0] bitfield definitions * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". * port="pif_rpf_vl_inner_tpid_i[15:0]" */ /* register address for bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_ADR … /* bitmask for bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_MSK … /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_MSKN … /* lower bit position of bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_SHIFT … /* width of bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_WIDTH … /* default value of bitfield vl_inner_tpid[f:0] */ #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT … /* rx vl_outer_tpid[f:0] bitfield definitions * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". * port="pif_rpf_vl_outer_tpid_i[15:0]" */ /* register address for bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_ADR … /* bitmask for bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_MSK … /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_MSKN … /* lower bit position of bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT … /* width of bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH … /* default value of bitfield vl_outer_tpid[f:0] */ #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT … /* rx vl_promis_mode bitfield definitions * preprocessor definitions for the bitfield "vl_promis_mode". * port="pif_rpf_vl_promis_mode_i" */ /* register address for bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_ADR … /* bitmask for bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_MSK … /* inverted bitmask for bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN … /* lower bit position of bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT … /* width of bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH … /* default value of bitfield vl_promis_mode */ #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT … /* RX vl_accept_untagged_mode Bitfield Definitions * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". * PORT="pif_rpf_vl_accept_untagged_i" */ /* Register address for bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR … /* Bitmask for bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK … /* Inverted bitmask for bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN … /* Lower bit position of bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT … /* Width of bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH … /* Default value of bitfield vl_accept_untagged_mode */ #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT … /* rX vl_untagged_act[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". * PORT="pif_rpf_vl_untagged_act_i[2:0]" */ /* Register address for bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR … /* Bitmask for bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK … /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN … /* Lower bit position of bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT … /* Width of bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH … /* Default value of bitfield vl_untagged_act[2:0] */ #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT … /* RX vl_en{F} Bitfield Definitions * Preprocessor definitions for the bitfield "vl_en{F}". * Parameter: filter {F} | stride size 0x4 | range [0, 15] * PORT="pif_rpf_vl_en_i[0]" */ /* Register address for bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_ADR(filter) … /* Bitmask for bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_MSK … /* Inverted bitmask for bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_MSKN … /* Lower bit position of bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_SHIFT … /* Width of bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_WIDTH … /* Default value of bitfield vl_en{F} */ #define HW_ATL_RPF_VL_EN_F_DEFAULT … /* RX vl_act{F}[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". * Parameter: filter {F} | stride size 0x4 | range [0, 15] * PORT="pif_rpf_vl_act0_i[2:0]" */ /* Register address for bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_ADR(filter) … /* Bitmask for bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_MSK … /* Inverted bitmask for bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_MSKN … /* Lower bit position of bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_SHIFT … /* Width of bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_WIDTH … /* Default value of bitfield vl_act{F}[2:0] */ #define HW_ATL_RPF_VL_ACT_F_DEFAULT … /* RX vl_id{F}[B:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". * Parameter: filter {F} | stride size 0x4 | range [0, 15] * PORT="pif_rpf_vl_id0_i[11:0]" */ /* Register address for bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_ADR(filter) … /* Bitmask for bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_MSK … /* Inverted bitmask for bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_MSKN … /* Lower bit position of bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_SHIFT … /* Width of bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_WIDTH … /* Default value of bitfield vl_id{F}[B:0] */ #define HW_ATL_RPF_VL_ID_F_DEFAULT … /* RX vl_rxq_en{F} Bitfield Definitions * Preprocessor definitions for the bitfield "vl_rxq{F}". * Parameter: filter {F} | stride size 0x4 | range [0, 15] * PORT="pif_rpf_vl_rxq_en_i" */ /* Register address for bitfield vl_rxq_en{F} */ #define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) … /* Bitmask for bitfield vl_rxq_en{F} */ #define HW_ATL_RPF_VL_RXQ_EN_F_MSK … /* Inverted bitmask for bitfield vl_rxq_en{F}[ */ #define HW_ATL_RPF_VL_RXQ_EN_F_MSKN … /* Lower bit position of bitfield vl_rxq_en{F} */ #define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT … /* Width of bitfield vl_rxq_en{F} */ #define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH … /* Default value of bitfield vl_rxq_en{F} */ #define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT … /* RX vl_rxq{F}[4:0] Bitfield Definitions * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]". * Parameter: filter {F} | stride size 0x4 | range [0, 15] * PORT="pif_rpf_vl_rxq0_i[4:0]" */ /* Register address for bitfield vl_rxq{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_ADR(filter) … /* Bitmask for bitfield vl_rxq{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_MSK … /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_MSKN … /* Lower bit position of bitfield vl_rxq{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_SHIFT … /* Width of bitfield vl_rxw{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_WIDTH … /* Default value of bitfield vl_rxq{F}[4:0] */ #define HW_ATL_RPF_VL_RXQ_F_DEFAULT … /* rx et_en{f} bitfield definitions * preprocessor definitions for the bitfield "et_en{f}". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_en_i[0]" */ /* register address for bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_ADR(filter) … /* bitmask for bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_MSK … /* inverted bitmask for bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_MSKN … /* lower bit position of bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_SHIFT … /* width of bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_WIDTH … /* default value of bitfield et_en{f} */ #define HW_ATL_RPF_ET_ENF_DEFAULT … /* rx et_up{f}_en bitfield definitions * preprocessor definitions for the bitfield "et_up{f}_en". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_up_en_i[0]" */ /* register address for bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_ADR(filter) … /* bitmask for bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_MSK … /* inverted bitmask for bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_MSKN … /* lower bit position of bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_SHIFT … /* width of bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_WIDTH … /* default value of bitfield et_up{f}_en */ #define HW_ATL_RPF_ET_UPFEN_DEFAULT … /* rx et_rxq{f}_en bitfield definitions * preprocessor definitions for the bitfield "et_rxq{f}_en". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_rxq_en_i[0]" */ /* register address for bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) … /* bitmask for bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_MSK … /* inverted bitmask for bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_MSKN … /* lower bit position of bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_SHIFT … /* width of bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_WIDTH … /* default value of bitfield et_rxq{f}_en */ #define HW_ATL_RPF_ET_RXQFEN_DEFAULT … /* rx et_up{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "et_up{f}[2:0]". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_up0_i[2:0]" */ /* register address for bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_ADR(filter) … /* bitmask for bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_MSK … /* inverted bitmask for bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_MSKN … /* lower bit position of bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_SHIFT … /* width of bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_WIDTH … /* default value of bitfield et_up{f}[2:0] */ #define HW_ATL_RPF_ET_UPF_DEFAULT … /* rx et_rxq{f}[4:0] bitfield definitions * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_rxq0_i[4:0]" */ /* register address for bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_ADR(filter) … /* bitmask for bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_MSK … /* inverted bitmask for bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_MSKN … /* lower bit position of bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_SHIFT … /* width of bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_WIDTH … /* default value of bitfield et_rxq{f}[4:0] */ #define HW_ATL_RPF_ET_RXQF_DEFAULT … /* rx et_mng_rxq{f} bitfield definitions * preprocessor definitions for the bitfield "et_mng_rxq{f}". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_mng_rxq_i[0]" */ /* register address for bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) … /* bitmask for bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_MSK … /* inverted bitmask for bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_MSKN … /* lower bit position of bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT … /* width of bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH … /* default value of bitfield et_mng_rxq{f} */ #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT … /* rx et_act{f}[2:0] bitfield definitions * preprocessor definitions for the bitfield "et_act{f}[2:0]". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_act0_i[2:0]" */ /* register address for bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_ADR(filter) … /* bitmask for bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_MSK … /* inverted bitmask for bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_MSKN … /* lower bit position of bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_SHIFT … /* width of bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_WIDTH … /* default value of bitfield et_act{f}[2:0] */ #define HW_ATL_RPF_ET_ACTF_DEFAULT … /* rx et_val{f}[f:0] bitfield definitions * preprocessor definitions for the bitfield "et_val{f}[f:0]". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_et_val0_i[15:0]" */ /* register address for bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_ADR(filter) … /* bitmask for bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_MSK … /* inverted bitmask for bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_MSKN … /* lower bit position of bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_SHIFT … /* width of bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_WIDTH … /* default value of bitfield et_val{f}[f:0] */ #define HW_ATL_RPF_ET_VALF_DEFAULT … /* RX l3_l4_en{F} Bitfield Definitions * Preprocessor definitions for the bitfield "l3_l4_en{F}". * Parameter: filter {F} | stride size 0x4 | range [0, 7] * PORT="pif_rpf_l3_l4_en_i[0]" */ #define HW_ATL_RPF_L3_REG_CTRL_ADR(filter) … /* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]". * Parameter: location {D} | stride size 0x4 | range [0, 7] * PORT="pif_rpf_l3_sa0_i[31:0]" */ /* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */ #define HW_ATL_RPF_L3_SRCA_ADR(filter) … /* Bitmask for bitfield l3_sa0[1F:0] */ #define HW_ATL_RPF_L3_SRCA_MSK … /* Inverted bitmask for bitfield l3_sa0[1F:0] */ #define HW_ATL_RPF_L3_SRCA_MSKN … /* Lower bit position of bitfield l3_sa0[1F:0] */ #define HW_ATL_RPF_L3_SRCA_SHIFT … /* Width of bitfield l3_sa0[1F:0] */ #define HW_ATL_RPF_L3_SRCA_WIDTH … /* Default value of bitfield l3_sa0[1F:0] */ #define HW_ATL_RPF_L3_SRCA_DEFAULT … /* RX rpf_l3_da{D}[1F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]". * Parameter: location {D} | stride size 0x4 | range [0, 7] * PORT="pif_rpf_l3_da0_i[31:0]" */ /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */ #define HW_ATL_RPF_L3_DSTA_ADR(filter) … /* Bitmask for bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_MSK … /* Inverted bitmask for bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_MSKN … /* Lower bit position of bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_SHIFT … /* Width of bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_WIDTH … /* Default value of bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_DEFAULT … /* RX l4_sp{D}[F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]". * Parameter: srcport {D} | stride size 0x4 | range [0, 7] * PORT="pif_rpf_l4_sp0_i[15:0]" */ /* Register address for bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_ADR(srcport) … /* Bitmask for bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_MSK … /* Inverted bitmask for bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_MSKN … /* Lower bit position of bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_SHIFT … /* Width of bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_WIDTH … /* Default value of bitfield l4_sp{D}[F:0] */ #define HW_ATL_RPF_L4_SPD_DEFAULT … /* RX l4_dp{D}[F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]". * Parameter: destport {D} | stride size 0x4 | range [0, 7] * PORT="pif_rpf_l4_dp0_i[15:0]" */ /* Register address for bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_ADR(destport) … /* Bitmask for bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_MSK … /* Inverted bitmask for bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_MSKN … /* Lower bit position of bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_SHIFT … /* Width of bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_WIDTH … /* Default value of bitfield l4_dp{D}[F:0] */ #define HW_ATL_RPF_L4_DPD_DEFAULT … /* rx ipv4_chk_en bitfield definitions * preprocessor definitions for the bitfield "ipv4_chk_en". * port="pif_rpo_ipv4_chk_en_i" */ /* register address for bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_ADR … /* bitmask for bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_MSK … /* inverted bitmask for bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_MSKN … /* lower bit position of bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_SHIFT … /* width of bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_WIDTH … /* default value of bitfield ipv4_chk_en */ #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT … /* rx desc{d}_vl_strip bitfield definitions * preprocessor definitions for the bitfield "desc{d}_vl_strip". * parameter: descriptor {d} | stride size 0x20 | range [0, 31] * port="pif_rpo_desc_vl_strip_i[0]" */ /* register address for bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) … /* bitmask for bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_MSK … /* inverted bitmask for bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_MSKN … /* lower bit position of bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT … /* width of bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH … /* default value of bitfield desc{d}_vl_strip */ #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT … /* rx l4_chk_en bitfield definitions * preprocessor definitions for the bitfield "l4_chk_en". * port="pif_rpo_l4_chk_en_i" */ /* register address for bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_ADR … /* bitmask for bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_MSK … /* inverted bitmask for bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_MSKN … /* lower bit position of bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_SHIFT … /* width of bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_WIDTH … /* default value of bitfield l4_chk_en */ #define HW_ATL_RPOL4CHK_EN_DEFAULT … /* RX outer_vl_ins_mode Bitfield Definitions * Preprocessor definitions for the bitfield "outer_vl_ins_mode". * PORT="pif_rpo_outer_vl_mode_i" */ /* Register address for bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR … /* Bitmask for bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK … /* Inverted bitmask for bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN … /* Lower bit position of bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT … /* Width of bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH … /* Default value of bitfield outer_vl_ins_mode */ #define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT … /* rx reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". * port="pif_rx_reg_res_dsbl_i" */ /* register address for bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_ADR … /* bitmask for bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_MSK … /* inverted bitmask for bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_MSKN … /* lower bit position of bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_SHIFT … /* width of bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_WIDTH … /* default value of bitfield reg_res_dsbl */ #define HW_ATL_RX_REG_RES_DSBL_DEFAULT … /* tx dca{d}_cpuid[7:0] bitfield definitions * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". * parameter: dca {d} | stride size 0x4 | range [0, 31] * port="pif_tdm_dca0_cpuid_i[7:0]" */ /* register address for bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_ADR(dca) … /* bitmask for bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_MSK … /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_MSKN … /* lower bit position of bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_SHIFT … /* width of bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_WIDTH … /* default value of bitfield dca{d}_cpuid[7:0] */ #define HW_ATL_TDM_DCADCPUID_DEFAULT … /* tx lso_en[1f:0] bitfield definitions * preprocessor definitions for the bitfield "lso_en[1f:0]". * port="pif_tdm_lso_en_i[31:0]" */ /* register address for bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_ADR … /* bitmask for bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_MSK … /* inverted bitmask for bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_MSKN … /* lower bit position of bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_SHIFT … /* width of bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_WIDTH … /* default value of bitfield lso_en[1f:0] */ #define HW_ATL_TDM_LSO_EN_DEFAULT … /* tx dca_en bitfield definitions * preprocessor definitions for the bitfield "dca_en". * port="pif_tdm_dca_en_i" */ /* register address for bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_ADR … /* bitmask for bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_MSK … /* inverted bitmask for bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_MSKN … /* lower bit position of bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_SHIFT … /* width of bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_WIDTH … /* default value of bitfield dca_en */ #define HW_ATL_TDM_DCA_EN_DEFAULT … /* tx dca_mode[3:0] bitfield definitions * preprocessor definitions for the bitfield "dca_mode[3:0]". * port="pif_tdm_dca_mode_i[3:0]" */ /* register address for bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_ADR … /* bitmask for bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_MSK … /* inverted bitmask for bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_MSKN … /* lower bit position of bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_SHIFT … /* width of bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_WIDTH … /* default value of bitfield dca_mode[3:0] */ #define HW_ATL_TDM_DCA_MODE_DEFAULT … /* tx dca{d}_desc_en bitfield definitions * preprocessor definitions for the bitfield "dca{d}_desc_en". * parameter: dca {d} | stride size 0x4 | range [0, 31] * port="pif_tdm_dca_desc_en_i[0]" */ /* register address for bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) … /* bitmask for bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_MSK … /* inverted bitmask for bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_MSKN … /* lower bit position of bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_SHIFT … /* width of bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_WIDTH … /* default value of bitfield dca{d}_desc_en */ #define HW_ATL_TDM_DCADDESC_EN_DEFAULT … /* tx desc{d}_en bitfield definitions * preprocessor definitions for the bitfield "desc{d}_en". * parameter: descriptor {d} | stride size 0x40 | range [0, 31] * port="pif_tdm_desc_en_i[0]" */ /* register address for bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_ADR(descriptor) … /* bitmask for bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_MSK … /* inverted bitmask for bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_MSKN … /* lower bit position of bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_SHIFT … /* width of bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_WIDTH … /* default value of bitfield desc{d}_en */ #define HW_ATL_TDM_DESCDEN_DEFAULT … /* tx desc{d}_hd[c:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". * parameter: descriptor {d} | stride size 0x40 | range [0, 31] * port="tdm_pif_desc0_hd_o[12:0]" */ /* register address for bitfield desc{d}_hd[c:0] */ #define HW_ATL_TDM_DESCDHD_ADR(descriptor) … /* bitmask for bitfield desc{d}_hd[c:0] */ #define HW_ATL_TDM_DESCDHD_MSK … /* inverted bitmask for bitfield desc{d}_hd[c:0] */ #define HW_ATL_TDM_DESCDHD_MSKN … /* lower bit position of bitfield desc{d}_hd[c:0] */ #define HW_ATL_TDM_DESCDHD_SHIFT … /* width of bitfield desc{d}_hd[c:0] */ #define HW_ATL_TDM_DESCDHD_WIDTH … /* tx desc{d}_len[9:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_len[9:0]". * parameter: descriptor {d} | stride size 0x40 | range [0, 31] * port="pif_tdm_desc0_len_i[9:0]" */ /* register address for bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) … /* bitmask for bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_MSK … /* inverted bitmask for bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_MSKN … /* lower bit position of bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_SHIFT … /* width of bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_WIDTH … /* default value of bitfield desc{d}_len[9:0] */ #define HW_ATL_TDM_DESCDLEN_DEFAULT … /* tx int_desc_wrb_en bitfield definitions * preprocessor definitions for the bitfield "int_desc_wrb_en". * port="pif_tdm_int_desc_wrb_en_i" */ /* register address for bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR … /* bitmask for bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK … /* inverted bitmask for bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN … /* lower bit position of bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT … /* width of bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH … /* default value of bitfield int_desc_wrb_en */ #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT … /* tx desc{d}_wrb_thresh[6:0] bitfield definitions * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". * parameter: descriptor {d} | stride size 0x40 | range [0, 31] * port="pif_tdm_desc0_wrb_thresh_i[6:0]" */ /* register address for bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) … /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_MSK … /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN … /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT … /* width of bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH … /* default value of bitfield desc{d}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT … /* tx lso_tcp_flag_first[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". * port="pif_thm_lso_tcp_flag_first_i[11:0]" */ /* register address for bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR … /* bitmask for bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK … /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN … /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT … /* width of bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH … /* default value of bitfield lso_tcp_flag_first[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT … /* tx lso_tcp_flag_last[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". * port="pif_thm_lso_tcp_flag_last_i[11:0]" */ /* register address for bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR … /* bitmask for bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK … /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN … /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT … /* width of bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH … /* default value of bitfield lso_tcp_flag_last[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT … /* tx lso_tcp_flag_mid[b:0] bitfield definitions * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". * port="pif_thm_lso_tcp_flag_mid_i[11:0]" */ /* Register address for bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_ADR … /* Bitmask for bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_MSK … /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_MSKN … /* Lower bit position of bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT … /* Width of bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH … /* Default value of bitfield lro_rsc_max[1F:0] */ #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT … /* RX lro_en[1F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_en[1F:0]". * PORT="pif_rpo_lro_en_i[31:0]" */ /* Register address for bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_ADR … /* Bitmask for bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_MSK … /* Inverted bitmask for bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_MSKN … /* Lower bit position of bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_SHIFT … /* Width of bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_WIDTH … /* Default value of bitfield lro_en[1F:0] */ #define HW_ATL_RPO_LRO_EN_DEFAULT … /* RX lro_ptopt_en Bitfield Definitions * Preprocessor definitions for the bitfield "lro_ptopt_en". * PORT="pif_rpo_lro_ptopt_en_i" */ /* Register address for bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_ADR … /* Bitmask for bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_MSK … /* Inverted bitmask for bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN … /* Lower bit position of bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT … /* Width of bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH … /* Default value of bitfield lro_ptopt_en */ #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT … /* RX lro_q_ses_lmt Bitfield Definitions * Preprocessor definitions for the bitfield "lro_q_ses_lmt". * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" */ /* Register address for bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_ADR … /* Bitmask for bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_MSK … /* Inverted bitmask for bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_MSKN … /* Lower bit position of bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT … /* Width of bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH … /* Default value of bitfield lro_q_ses_lmt */ #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT … /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" */ /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR … /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK … /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN … /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT … /* Width of bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH … /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT … /* RX lro_pkt_min[4:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". * PORT="pif_rpo_lro_pkt_min_i[4:0]" */ /* Register address for bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_ADR … /* Bitmask for bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_MSK … /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_MSKN … /* Lower bit position of bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT … /* Width of bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH … /* Default value of bitfield lro_pkt_min[4:0] */ #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT … /* Width of bitfield lro{L}_des_max[1:0] */ #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH … /* Default value of bitfield lro{L}_des_max[1:0] */ #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT … /* RX lro_tb_div[11:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". * PORT="pif_rpo_lro_tb_div_i[11:0]" */ /* Register address for bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_ADR … /* Bitmask for bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_MSK … /* Inverted bitmask for bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_MSKN … /* Lower bit position of bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_SHIFT … /* Width of bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_WIDTH … /* Default value of bitfield lro_tb_div[11:0] */ #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT … /* RX lro_ina_ival[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". * PORT="pif_rpo_lro_ina_ival_i[9:0]" */ /* Register address for bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_ADR … /* Bitmask for bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_MSK … /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_MSKN … /* Lower bit position of bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT … /* Width of bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH … /* Default value of bitfield lro_ina_ival[9:0] */ #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT … /* RX lro_max_ival[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". * PORT="pif_rpo_lro_max_ival_i[9:0]" */ /* Register address for bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_ADR … /* Bitmask for bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_MSK … /* Inverted bitmask for bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN … /* Lower bit position of bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT … /* Width of bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH … /* Default value of bitfield lro_max_ival[9:0] */ #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT … /* TX dca{D}_cpuid[7:0] Bitfield Definitions * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". * Parameter: DCA {D} | stride size 0x4 | range [0, 31] * PORT="pif_tdm_dca0_cpuid_i[7:0]" */ /* Register address for bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) … /* Bitmask for bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_MSK … /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_MSKN … /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_SHIFT … /* Width of bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_WIDTH … /* Default value of bitfield dca{D}_cpuid[7:0] */ #define HW_ATL_TDM_DCA_DCPUID_DEFAULT … /* TX dca{D}_desc_en Bitfield Definitions * Preprocessor definitions for the bitfield "dca{D}_desc_en". * Parameter: DCA {D} | stride size 0x4 | range [0, 31] * PORT="pif_tdm_dca_desc_en_i[0]" */ /* Register address for bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) … /* Bitmask for bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_MSK … /* Inverted bitmask for bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_MSKN … /* Lower bit position of bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT … /* Width of bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH … /* Default value of bitfield dca{D}_desc_en */ #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT … /* TX desc{D}_en Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_en". * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] * PORT="pif_tdm_desc_en_i[0]" */ /* Register address for bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) … /* Bitmask for bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_MSK … /* Inverted bitmask for bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_MSKN … /* Lower bit position of bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_SHIFT … /* Width of bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_WIDTH … /* Default value of bitfield desc{D}_en */ #define HW_ATL_TDM_DESC_DEN_DEFAULT … /* TX desc{D}_hd[C:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] * PORT="tdm_pif_desc0_hd_o[12:0]" */ /* Register address for bitfield desc{D}_hd[C:0] */ #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) … /* Bitmask for bitfield desc{D}_hd[C:0] */ #define HW_ATL_TDM_DESC_DHD_MSK … /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ #define HW_ATL_TDM_DESC_DHD_MSKN … /* Lower bit position of bitfield desc{D}_hd[C:0] */ #define HW_ATL_TDM_DESC_DHD_SHIFT … /* Width of bitfield desc{D}_hd[C:0] */ #define HW_ATL_TDM_DESC_DHD_WIDTH … /* TX desc{D}_len[9:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] * PORT="pif_tdm_desc0_len_i[9:0]" */ /* Register address for bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) … /* Bitmask for bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_MSK … /* Inverted bitmask for bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_MSKN … /* Lower bit position of bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_SHIFT … /* Width of bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_WIDTH … /* Default value of bitfield desc{D}_len[9:0] */ #define HW_ATL_TDM_DESC_DLEN_DEFAULT … /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" */ /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) … /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK … /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN … /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT … /* Width of bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH … /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT … /* TX tdm_int_mod_en Bitfield Definitions * Preprocessor definitions for the bitfield "tdm_int_mod_en". * PORT="pif_tdm_int_mod_en_i" */ /* Register address for bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_ADR … /* Bitmask for bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_MSK … /* Inverted bitmask for bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_MSKN … /* Lower bit position of bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_SHIFT … /* Width of bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_WIDTH … /* Default value of bitfield tdm_int_mod_en */ #define HW_ATL_TDM_INT_MOD_EN_DEFAULT … /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" */ /* register address for bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR … /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK … /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN … /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT … /* width of bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH … /* default value of bitfield lso_tcp_flag_mid[b:0] */ #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT … /* tx tx_tc_mode bitfield definitions * preprocessor definitions for the bitfield "tx_tc_mode". * port="pif_tpb_tx_tc_mode_i,pif_tps_tx_tc_mode_i" */ /* register address for bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_ADDR … /* bitmask for bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_MSK … /* inverted bitmask for bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_MSKN … /* lower bit position of bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_SHIFT … /* width of bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_WIDTH … /* default value of bitfield tx_tc_mode */ #define HW_ATL_TPB_TX_TC_MODE_DEFAULT … /* tx tx_desc_rate_mode bitfield definitions * preprocessor definitions for the bitfield "tx_desc_rate_mode". * port="pif_tps_desc_rate_mode_i" */ /* register address for bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_ADR … /* bitmask for bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSK … /* inverted bitmask for bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_MSKN … /* lower bit position of bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_SHIFT … /* width of bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_WIDTH … /* default value of bitfield tx_desc_rate_mode */ #define HW_ATL_TPS_TX_DESC_RATE_MODE_DEFAULT … /* tx tx_buf_en bitfield definitions * preprocessor definitions for the bitfield "tx_buf_en". * port="pif_tpb_tx_buf_en_i" */ /* register address for bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_ADR … /* bitmask for bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_MSK … /* inverted bitmask for bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_MSKN … /* lower bit position of bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_SHIFT … /* width of bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_WIDTH … /* default value of bitfield tx_buf_en */ #define HW_ATL_TPB_TX_BUF_EN_DEFAULT … /* tx tx{b}_hi_thresh[c:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_tpb_tx0_hi_thresh_i[12:0]" */ /* register address for bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) … /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_MSK … /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_MSKN … /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_SHIFT … /* width of bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_WIDTH … /* default value of bitfield tx{b}_hi_thresh[c:0] */ #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT … /* tx tx{b}_lo_thresh[c:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_tpb_tx0_lo_thresh_i[12:0]" */ /* register address for bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) … /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_MSK … /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_MSKN … /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_SHIFT … /* width of bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_WIDTH … /* default value of bitfield tx{b}_lo_thresh[c:0] */ #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT … /* tx dma_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_sys_loopback". * port="pif_tpb_dma_sys_lbk_i" */ /* register address for bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_ADR … /* bitmask for bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_MSK … /* inverted bitmask for bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_MSKN … /* lower bit position of bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT … /* width of bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH … /* default value of bitfield dma_sys_loopback */ #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT … /* tx dma_net_loopback bitfield definitions * preprocessor definitions for the bitfield "dma_net_loopback". * port="pif_tpb_dma_net_lbk_i" */ /* register address for bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_ADR … /* bitmask for bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_MSK … /* inverted bitmask for bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_MSKN … /* lower bit position of bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_SHIFT … /* width of bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_WIDTH … /* default value of bitfield dma_net_loopback */ #define HW_ATL_TPB_DMA_NET_LBK_DEFAULT … /* tx tx{b}_buf_size[7:0] bitfield definitions * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". * parameter: buffer {b} | stride size 0x10 | range [0, 7] * port="pif_tpb_tx0_buf_size_i[7:0]" */ /* register address for bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) … /* bitmask for bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_MSK … /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_MSKN … /* lower bit position of bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT … /* width of bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH … /* default value of bitfield tx{b}_buf_size[7:0] */ #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT … /* tx tx_scp_ins_en bitfield definitions * preprocessor definitions for the bitfield "tx_scp_ins_en". * port="pif_tpb_scp_ins_en_i" */ /* register address for bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_ADR … /* bitmask for bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_MSK … /* inverted bitmask for bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN … /* lower bit position of bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT … /* width of bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH … /* default value of bitfield tx_scp_ins_en */ #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT … /* tx tx_clk_gate_en bitfield definitions * preprocessor definitions for the bitfield "tx_clk_gate_en". * port="pif_tpb_clk_gate_en_i" */ /* register address for bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_ADR … /* bitmask for bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_MSK … /* inverted bitmask for bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_MSKN … /* lower bit position of bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT … /* width of bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_WIDTH … /* default value of bitfield tx_clk_gate_en */ #define HW_ATL_TPB_TX_CLK_GATE_EN_DEFAULT … /* tx ipv4_chk_en bitfield definitions * preprocessor definitions for the bitfield "ipv4_chk_en". * port="pif_tpo_ipv4_chk_en_i" */ /* register address for bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_ADR … /* bitmask for bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_MSK … /* inverted bitmask for bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_MSKN … /* lower bit position of bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_SHIFT … /* width of bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_WIDTH … /* default value of bitfield ipv4_chk_en */ #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT … /* tx l4_chk_en bitfield definitions * preprocessor definitions for the bitfield "l4_chk_en". * port="pif_tpo_l4_chk_en_i" */ /* register address for bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_ADR … /* bitmask for bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_MSK … /* inverted bitmask for bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_MSKN … /* lower bit position of bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_SHIFT … /* width of bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_WIDTH … /* default value of bitfield l4_chk_en */ #define HW_ATL_TPOL4CHK_EN_DEFAULT … /* tx pkt_sys_loopback bitfield definitions * preprocessor definitions for the bitfield "pkt_sys_loopback". * port="pif_tpo_pkt_sys_lbk_i" */ /* register address for bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_ADR … /* bitmask for bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_MSK … /* inverted bitmask for bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_MSKN … /* lower bit position of bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT … /* width of bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH … /* default value of bitfield pkt_sys_loopback */ #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT … /* tx data_tc_arb_mode bitfield definitions * preprocessor definitions for the bitfield "data_tc_arb_mode". * port="pif_tps_data_tc_arb_mode_i" */ /* register address for bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR … /* bitmask for bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK … /* inverted bitmask for bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN … /* lower bit position of bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT … /* width of bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH … /* default value of bitfield data_tc_arb_mode */ #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT … /* tx desc{r}_rate_en bitfield definitions * preprocessor definitions for the bitfield "desc{r}_rate_en". * port="pif_tps_desc_rate_en_i[0]" */ /* register address for bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_ADR(desc) … /* bitmask for bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_MSK … /* inverted bitmask for bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_MSKN … /* lower bit position of bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_SHIFT … /* width of bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_WIDTH … /* default value of bitfield desc{r}_rate_en */ #define HW_ATL_TPS_DESC_RATE_EN_DEFAULT … /* tx desc{r}_rate_x bitfield definitions * preprocessor definitions for the bitfield "desc{r}_rate_x". * port="pif_tps_desc0_rate_x" */ /* register address for bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_ADR(desc) … /* bitmask for bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_MSK … /* inverted bitmask for bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_MSKN … /* lower bit position of bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_SHIFT … /* width of bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_WIDTH … /* default value of bitfield desc{r}_rate_x */ #define HW_ATL_TPS_DESC_RATE_X_DEFAULT … /* tx desc{r}_rate_y bitfield definitions * preprocessor definitions for the bitfield "desc{r}_rate_y". * port="pif_tps_desc0_rate_y" */ /* register address for bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_ADR(desc) … /* bitmask for bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_MSK … /* inverted bitmask for bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_MSKN … /* lower bit position of bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_SHIFT … /* width of bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_WIDTH … /* default value of bitfield desc{r}_rate_y */ #define HW_ATL_TPS_DESC_RATE_Y_DEFAULT … /* tx desc_rate_ta_rst bitfield definitions * preprocessor definitions for the bitfield "desc_rate_ta_rst". * port="pif_tps_desc_rate_ta_rst_i" */ /* register address for bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR … /* bitmask for bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK … /* inverted bitmask for bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN … /* lower bit position of bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT … /* width of bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH … /* default value of bitfield desc_rate_ta_rst */ #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT … /* tx desc_rate_limit[a:0] bitfield definitions * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". * port="pif_tps_desc_rate_lim_i[10:0]" */ /* register address for bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_ADR … /* bitmask for bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_MSK … /* inverted bitmask for bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_MSKN … /* lower bit position of bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT … /* width of bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH … /* default value of bitfield desc_rate_limit[a:0] */ #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT … /* tx desc_tc_arb_mode[1:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". * port="pif_tps_desc_tc_arb_mode_i[1:0]" */ /* register address for bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR … /* bitmask for bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK … /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN … /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT … /* width of bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH … /* default value of bitfield desc_tc_arb_mode[1:0] */ #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT … /* tx desc_tc{t}_credit_max[b:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_desc_tc0_credit_max_i[11:0]" */ /* register address for bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) … /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK … /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN … /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT … /* width of bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH … /* default value of bitfield desc_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT … /* tx desc_tc{t}_weight[8:0] bitfield definitions * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_desc_tc0_weight_i[8:0]" */ /* register address for bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) … /* bitmask for bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK … /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN … /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT … /* width of bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH … /* default value of bitfield desc_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT … /* tx desc_vm_arb_mode bitfield definitions * preprocessor definitions for the bitfield "desc_vm_arb_mode". * port="pif_tps_desc_vm_arb_mode_i" */ /* register address for bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR … /* bitmask for bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK … /* inverted bitmask for bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN … /* lower bit position of bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT … /* width of bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH … /* default value of bitfield desc_vm_arb_mode */ #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT … /* tx data_tc{t}_credit_max[b:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_data_tc0_credit_max_i[11:0]" */ /* register address for bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) … /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK … /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN … /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT … /* width of bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH … /* default value of bitfield data_tc{t}_credit_max[b:0] */ #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT … /* tx data_tc{t}_weight[8:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_data_tc0_weight_i[8:0]" */ /* register address for bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) … /* bitmask for bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK … /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN … /* lower bit position of bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT … /* width of bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH … /* default value of bitfield data_tc{t}_weight[8:0] */ #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT … /* tx reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". * port="pif_tx_reg_res_dsbl_i" */ /* register address for bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_ADR … /* bitmask for bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_MSK … /* inverted bitmask for bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_MSKN … /* lower bit position of bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_SHIFT … /* width of bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_WIDTH … /* default value of bitfield reg_res_dsbl */ #define HW_ATL_TX_REG_RES_DSBL_DEFAULT … /* mac_phy register access busy bitfield definitions * preprocessor definitions for the bitfield "register access busy". * port="msm_pif_reg_busy_o" */ /* register address for bitfield register access busy */ #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR … /* bitmask for bitfield register access busy */ #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK … /* inverted bitmask for bitfield register access busy */ #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN … /* lower bit position of bitfield register access busy */ #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT … /* width of bitfield register access busy */ #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH … /* mac_phy msm register address[7:0] bitfield definitions * preprocessor definitions for the bitfield "msm register address[7:0]". * port="pif_msm_reg_addr_i[7:0]" */ /* register address for bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_ADR … /* bitmask for bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_MSK … /* inverted bitmask for bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_MSKN … /* lower bit position of bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_SHIFT … /* width of bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_WIDTH … /* default value of bitfield msm register address[7:0] */ #define HW_ATL_MSM_REG_ADDR_DEFAULT … /* mac_phy register read strobe bitfield definitions * preprocessor definitions for the bitfield "register read strobe". * port="pif_msm_reg_rden_i" */ /* register address for bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_ADR … /* bitmask for bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_MSK … /* inverted bitmask for bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_MSKN … /* lower bit position of bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_SHIFT … /* width of bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_WIDTH … /* default value of bitfield register read strobe */ #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT … /* mac_phy msm register read data[31:0] bitfield definitions * preprocessor definitions for the bitfield "msm register read data[31:0]". * port="msm_pif_reg_rd_data_o[31:0]" */ /* register address for bitfield msm register read data[31:0] */ #define HW_ATL_MSM_REG_RD_DATA_ADR … /* bitmask for bitfield msm register read data[31:0] */ #define HW_ATL_MSM_REG_RD_DATA_MSK … /* inverted bitmask for bitfield msm register read data[31:0] */ #define HW_ATL_MSM_REG_RD_DATA_MSKN … /* lower bit position of bitfield msm register read data[31:0] */ #define HW_ATL_MSM_REG_RD_DATA_SHIFT … /* width of bitfield msm register read data[31:0] */ #define HW_ATL_MSM_REG_RD_DATA_WIDTH … /* mac_phy msm register write data[31:0] bitfield definitions * preprocessor definitions for the bitfield "msm register write data[31:0]". * port="pif_msm_reg_wr_data_i[31:0]" */ /* register address for bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_ADR … /* bitmask for bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_MSK … /* inverted bitmask for bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_MSKN … /* lower bit position of bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_SHIFT … /* width of bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_WIDTH … /* default value of bitfield msm register write data[31:0] */ #define HW_ATL_MSM_REG_WR_DATA_DEFAULT … /* mac_phy register write strobe bitfield definitions * preprocessor definitions for the bitfield "register write strobe". * port="pif_msm_reg_wren_i" */ /* register address for bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_ADR … /* bitmask for bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_MSK … /* inverted bitmask for bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_MSKN … /* lower bit position of bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_SHIFT … /* width of bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_WIDTH … /* default value of bitfield register write strobe */ #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT … /* register address for bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR … /* bitmask for bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK … /* inverted bitmask for bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSKN … /* lower bit position of bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT … /* width of bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_WIDTH … /* default value of bitfield PTP Digital Clock Read Enable */ #define HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_DEFAULT … /* register address for ptp counter reading */ #define HW_ATL_PCS_PTP_TS_VAL_ADDR(index) … /* mif soft reset bitfield definitions * preprocessor definitions for the bitfield "soft reset". * port="pif_glb_res_i" */ /* register address for bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_ADR … /* bitmask for bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_MSK … /* inverted bitmask for bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_MSKN … /* lower bit position of bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_SHIFT … /* width of bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_WIDTH … /* default value of bitfield soft reset */ #define HW_ATL_GLB_SOFT_RES_DEFAULT … /* mif register reset disable bitfield definitions * preprocessor definitions for the bitfield "register reset disable". * port="pif_glb_reg_res_dsbl_i" */ /* register address for bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_ADR … /* bitmask for bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_MSK … /* inverted bitmask for bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_MSKN … /* lower bit position of bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_SHIFT … /* width of bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_WIDTH … /* default value of bitfield register reset disable */ #define HW_ATL_GLB_REG_RES_DIS_DEFAULT … /* tx dma debug control definitions */ #define HW_ATL_TX_DMA_DEBUG_CTL_ADR … /* tx dma descriptor base address msw definitions */ #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) … /* tx dma total request limit */ #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR … /* tx interrupt moderation control register definitions * Preprocessor definitions for TX Interrupt Moderation Control Register * Base Address: 0x00008980 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] */ #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) … /* pcie reg_res_dsbl bitfield definitions * preprocessor definitions for the bitfield "reg_res_dsbl". * port="pif_pci_reg_res_dsbl_i" */ /* register address for bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_ADR … /* bitmask for bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_MSK … /* inverted bitmask for bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_MSKN … /* lower bit position of bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_SHIFT … /* width of bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_WIDTH … /* default value of bitfield reg_res_dsbl */ #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT … /* PCI core control register */ #define HW_ATL_PCI_REG_CONTROL6_ADR … /* global microprocessor scratch pad definitions */ #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) … /* register address for bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR … /* bitmask for bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK … /* inverted bitmask for bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN … /* lower bit position of bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT … /* width of bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH … /* default value of bitfield uP Force Interrupt */ #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT … /* Preprocessor definitions for Global MDIO Interfaces * Address: 0x00000280 + 0x4 * Number of interface */ #define HW_ATL_GLB_MDIO_IFACE_ADDR_BEGIN … #define HW_ATL_GLB_MDIO_IFACE_N_ADR(number) … /* MIF MDIO Busy Bitfield Definitions * Preprocessor definitions for the bitfield "MDIO Busy". * PORT="mdio_pif_busy_o" */ /* Register address for bitfield MDIO Busy */ #define HW_ATL_MDIO_BUSY_ADR … /* Bitmask for bitfield MDIO Busy */ #define HW_ATL_MDIO_BUSY_MSK … /* Inverted bitmask for bitfield MDIO Busy */ #define HW_ATL_MDIO_BUSY_MSKN … /* Lower bit position of bitfield MDIO Busy */ #define HW_ATL_MDIO_BUSY_SHIFT … /* Width of bitfield MDIO Busy */ #define HW_ATL_MDIO_BUSY_WIDTH … /* MIF MDIO Execute Operation Bitfield Definitions * Preprocessor definitions for the bitfield "MDIO Execute Operation". * PORT="pif_mdio_op_start_i" */ /* Register address for bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_ADR … /* Bitmask for bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_MSK … /* Inverted bitmask for bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_MSKN … /* Lower bit position of bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_SHIFT … /* Width of bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_WIDTH … /* Default value of bitfield MDIO Execute Operation */ #define HW_ATL_MDIO_EXECUTE_OPERATION_DEFAULT … /* MIF Op Mode [1:0] Bitfield Definitions * Preprocessor definitions for the bitfield "Op Mode [1:0]". * PORT="pif_mdio_mode_i[1:0]" */ /* Register address for bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_ADR … /* Bitmask for bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_MSK … /* Inverted bitmask for bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_MSKN … /* Lower bit position of bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_SHIFT … /* Width of bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_WIDTH … /* Default value of bitfield Op Mode [1:0] */ #define HW_ATL_MDIO_OP_MODE_DEFAULT … /* MIF PHY address Bitfield Definitions * Preprocessor definitions for the bitfield "PHY address". * PORT="pif_mdio_phy_addr_i[9:0]" */ /* Register address for bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_ADR … /* Bitmask for bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_MSK … /* Inverted bitmask for bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_MSKN … /* Lower bit position of bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_SHIFT … /* Width of bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_WIDTH … /* Default value of bitfield PHY address */ #define HW_ATL_MDIO_PHY_ADDRESS_DEFAULT … /* MIF MDIO WriteData [F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "MDIO WriteData [F:0]". * PORT="pif_mdio_wdata_i[15:0]" */ /* Register address for bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_ADR … /* Bitmask for bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_MSK … /* Inverted bitmask for bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_MSKN … /* Lower bit position of bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_SHIFT … /* Width of bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_WIDTH … /* Default value of bitfield MDIO WriteData [F:0] */ #define HW_ATL_MDIO_WRITE_DATA_DEFAULT … /* MIF MDIO Address [F:0] Bitfield Definitions * Preprocessor definitions for the bitfield "MDIO Address [F:0]". * PORT="pif_mdio_addr_i[15:0]" */ /* Register address for bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_ADR … /* Bitmask for bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_MSK … /* Inverted bitmask for bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_MSKN … /* Lower bit position of bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_SHIFT … /* Width of bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_WIDTH … /* Default value of bitfield MDIO Address [F:0] */ #define HW_ATL_MDIO_ADDRESS_DEFAULT … #define HW_ATL_MIF_RESET_TIMEOUT_ADR … #define HW_ATL_FW_SM_MDIO … #define HW_ATL_FW_SM_RAM … #define HW_ATL_FW_SM_RESET1 … #define HW_ATL_FW_SM_RESET2 … #endif /* HW_ATL_LLH_INTERNAL_H */
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