/* SPDX-License-Identifier: GPL-2.0-only */ /* * aQuantia Corporation Network Driver * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved */ /* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific * constants. */ #ifndef HW_ATL_B0_INTERNAL_H #define HW_ATL_B0_INTERNAL_H #include "../aq_common.h" #define HW_ATL_B0_MTU_JUMBO … #define HW_ATL_B0_MTU … #define HW_ATL_B0_TX_RINGS … #define HW_ATL_B0_RX_RINGS … #define HW_ATL_B0_RINGS_MAX … #define HW_ATL_B0_TXD_SIZE … #define HW_ATL_B0_RXD_SIZE … #define HW_ATL_B0_MAC … #define HW_ATL_B0_MAC_MIN … #define HW_ATL_B0_MAC_MAX … /* UCAST/MCAST filters */ #define HW_ATL_B0_UCAST_FILTERS_MAX … #define HW_ATL_B0_MCAST_FILTERS_MAX … /* interrupts */ #define HW_ATL_B0_ERR_INT … #define HW_ATL_B0_INT_MASK … #define HW_ATL_B0_TXD_CTL2_LEN … #define HW_ATL_B0_TXD_CTL2_CTX_EN … #define HW_ATL_B0_TXD_CTL2_CTX_IDX … #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD … #define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC … #define HW_ATL_B0_TXD_CTL_BLEN … #define HW_ATL_B0_TXD_CTL_DD … #define HW_ATL_B0_TXD_CTL_EOP … #define HW_ATL_B0_TXD_CTL_CMD_X … #define HW_ATL_B0_TXD_CTL_CMD_VLAN … #define HW_ATL_B0_TXD_CTL_CMD_FCS … #define HW_ATL_B0_TXD_CTL_CMD_IPCSO … #define HW_ATL_B0_TXD_CTL_CMD_TUCSO … #define HW_ATL_B0_TXD_CTL_CMD_LSO … #define HW_ATL_B0_TXD_CTL_CMD_WB … #define HW_ATL_B0_TXD_CTL_CMD_VXLAN … #define HW_ATL_B0_TXD_CTL_CMD_IPV6 … #define HW_ATL_B0_TXD_CTL_CMD_TCP … #define HW_ATL_B0_MPI_CONTROL_ADR … #define HW_ATL_B0_MPI_STATE_ADR … #define HW_ATL_B0_MPI_SPEED_MSK … #define HW_ATL_B0_MPI_SPEED_SHIFT … #define HW_ATL_B0_TXBUF_MAX … #define HW_ATL_B0_PTP_TXBUF_SIZE … #define HW_ATL_B0_RXBUF_MAX … #define HW_ATL_B0_PTP_RXBUF_SIZE … #define HW_ATL_B0_RSS_REDIRECTION_MAX … #define HW_ATL_B0_RSS_REDIRECTION_BITS … #define HW_ATL_B0_RSS_HASHKEY_BITS … #define HW_ATL_B0_TCRSS_4_8 … #define HW_ATL_B0_TC_MAX … #define HW_ATL_B0_RSS_MAX … #define HW_ATL_B0_LRO_RXD_MAX … #define HW_ATL_B0_RS_SLIP_ENABLED … /* (256k -1(max pay_len) - 54(header)) */ #define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE … /* (256k -1(max pay_len) - 74(header)) */ #define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE … #define HW_ATL_B0_CHIP_REVISION_B0 … #define HW_ATL_B0_CHIP_REVISION_UNKNOWN … #define HW_ATL_B0_FW_SEMA_RAM … #define HW_ATL_B0_TXC_LEN_TUNLEN … #define HW_ATL_B0_TXC_LEN_OUTLEN … #define HW_ATL_B0_TXC_CTL_DESC_TYPE … #define HW_ATL_B0_TXC_CTL_CTX_ID … #define HW_ATL_B0_TXC_CTL_VLAN … #define HW_ATL_B0_TXC_CTL_CMD … #define HW_ATL_B0_TXC_CTL_L2LEN … #define HW_ATL_B0_TXC_CTL_L3LEN … #define HW_ATL_B0_TXC_LEN2_L3LEN … #define HW_ATL_B0_TXC_LEN2_L4LEN … #define HW_ATL_B0_TXC_LEN2_MSSLEN … #define HW_ATL_B0_RXD_DD … #define HW_ATL_B0_RXD_NCEA0 … #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE … #define HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT … #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE … #define HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT … #define HW_ATL_B0_RXD_WB_STAT_RXCTRL … #define HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT … #define HW_ATL_B0_RXD_WB_STAT_SPLHDR … #define HW_ATL_B0_RXD_WB_STAT_HDRLEN … #define HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT … #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN … #define HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE … #define HW_ATL_B0_RXD_WB_STAT2_DD … #define HW_ATL_B0_RXD_WB_STAT2_EOP … #define HW_ATL_B0_RXD_WB_STAT2_RXSTAT … #define HW_ATL_B0_RXD_WB_STAT2_MACERR … #define HW_ATL_B0_RXD_WB_STAT2_IP4ERR … #define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR … #define HW_ATL_B0_RXD_WB_STAT2_RXESTAT … #define HW_ATL_B0_RXD_WB_STAT2_RSCCNT … #define L2_FILTER_ACTION_DISCARD … #define L2_FILTER_ACTION_HOST … #define HW_ATL_B0_UCP_0X370_REG … #define HW_ATL_B0_FLUSH() … #define HW_ATL_B0_FW_VER_EXPECTED … #define HW_ATL_INTR_MODER_MAX … #define HW_ATL_INTR_MODER_MIN … #define HW_ATL_B0_MIN_RXD … #define HW_ATL_B0_MIN_TXD … #define HW_ATL_B0_MAX_RXD … #define HW_ATL_B0_MAX_TXD … #define HW_ATL_RSS_DISABLED … #define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS … #define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS … /* HW layer capabilities */ #endif /* HW_ATL_B0_INTERNAL_H */
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