/* SPDX-License-Identifier: GPL-2.0-only */ /* Atlantic Network Driver * Copyright (C) 2020 Marvell International Ltd. */ #ifndef HW_ATL2_LLH_INTERNAL_H #define HW_ATL2_LLH_INTERNAL_H /* RX pif_rpf_redir_2_en_i Bitfield Definitions * PORT="pif_rpf_redir_2_en_i" */ #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR … #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK … #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN … #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT … #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_WIDTH … #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT … /* RX pif_rpf_rss_hash_type_i Bitfield Definitions */ #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR … #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK … #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN … #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT … #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_WIDTH … /* rx rpf_new_rpf_en bitfield definitions * preprocessor definitions for the bitfield "rpf_new_rpf_en_i". * port="pif_rpf_new_rpf_en_i */ /* register address for bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_ADR … /* bitmask for bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_MSK … /* inverted bitmask for bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_MSKN … /* lower bit position of bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_SHIFT … /* width of bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_WIDTH … /* default value of bitfield rpf_new_rpf_en */ #define HW_ATL2_RPF_NEW_EN_DEFAULT … /* rx l2_uc_req_tag0{f}[5:0] bitfield definitions * preprocessor definitions for the bitfield "l2_uc_req_tag0{f}[7:0]". * parameter: filter {f} | stride size 0x8 | range [0, 37] * port="pif_rpf_l2_uc_req_tag0[5:0]" */ /* register address for bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_ADR(filter) … /* bitmask for bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_MSK … /* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_MSKN … /* lower bit position of bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_SHIFT … /* width of bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_WIDTH … /* default value of bitfield l2_uc_req_tag0{f}[2:0] */ #define HW_ATL2_RPFL2UC_TAG_DEFAULT … /* rpf_l2_bc_req_tag[5:0] bitfield definitions * preprocessor definitions for the bitfield "rpf_l2_bc_req_tag[5:0]". * port="pifrpf_l2_bc_req_tag_i[5:0]" */ /* register address for bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_ADR … /* bitmask for bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_MSK … /* inverted bitmask for bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_MSKN … /* lower bit position of bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_SHIFT … /* width of bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_WIDTH … /* default value of bitfield rpf_l2_bc_req_tag */ #define HW_ATL2_RPF_L2_BC_TAG_DEFAULT … /* rx rpf_rss_red1_data_[4:0] bitfield definitions * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]". * port="pif_rpf_rss_red1_data_i[4:0]" */ /* register address for bitfield rpf_rss_red1_data[4:0] */ #define HW_ATL2_RPF_RSS_REDIR_ADR(TC, INDEX) … /* bitmask for bitfield rpf_rss_red1_data[4:0] */ #define HW_ATL2_RPF_RSS_REDIR_MSK(TC) … /* lower bit position of bitfield rpf_rss_red1_data[4:0] */ #define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) … /* width of bitfield rpf_rss_red1_data[4:0] */ #define HW_ATL2_RPF_RSS_REDIR_WIDTH … /* default value of bitfield rpf_rss_red1_data[4:0] */ #define HW_ATL2_RPF_RSS_REDIR_DEFAULT … /* rx vlan_req_tag0{f}[3:0] bitfield definitions * preprocessor definitions for the bitfield "vlan_req_tag0{f}[3:0]". * parameter: filter {f} | stride size 0x4 | range [0, 15] * port="pif_rpf_vlan_req_tag0[3:0]" */ /* register address for bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_ADR(filter) … /* bitmask for bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_MSK … /* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_MSKN … /* lower bit position of bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_SHIFT … /* width of bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_WIDTH … /* default value of bitfield vlan_req_tag0{f}[3:0] */ #define HW_ATL2_RPF_VL_TAG_DEFAULT … /* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions * Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]". * Parameter: Queue {Q} | bit-level stride | range [0, 31] * PORT="pif_rx_q0_tc_map_i[2:0]" */ /* Register address for bitfield rx_q{Q}_tc_map[2:0] */ #define HW_ATL2_RX_Q_TC_MAP_ADR(queue) … /* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */ #define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) … /* Width of bitfield rx_q{Q}_tc_map[2:0] */ #define HW_ATL2_RX_Q_TC_MAP_WIDTH … /* Default value of bitfield rx_q{Q}_tc_map[2:0] */ #define HW_ATL2_RX_Q_TC_MAP_DEFAULT … /* tx tx_tc_q_rand_map_en bitfield definitions * preprocessor definitions for the bitfield "tx_tc_q_rand_map_en". * port="pif_tpb_tx_tc_q_rand_map_en_i" */ /* register address for bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR … /* bitmask for bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK … /* inverted bitmask for bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSKN … /* lower bit position of bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT … /* width of bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_WIDTH … /* default value of bitfield tx_tc_q_rand_map_en */ #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_DEFAULT … /* tx tx_buffer_clk_gate_en bitfield definitions * preprocessor definitions for the bitfield "tx_buffer_clk_gate_en". * port="pif_tpb_tx_buffer_clk_gate_en_i" */ /* register address for bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR … /* bitmask for bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK … /* inverted bitmask for bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN … /* lower bit position of bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT … /* width of bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH … /* default value of bitfield tx_buffer_clk_gate_en */ #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT … /* tx tx_q_tc_map{q} bitfield definitions * preprocessor definitions for the bitfield "tx_q_tc_map{q}". * parameter: queue {q} | bit-level stride | range [0, 31] * port="pif_tpb_tx_q_tc_map0_i[2:0]" */ /* register address for bitfield tx_q_tc_map{q} */ #define HW_ATL2_TX_Q_TC_MAP_ADR(queue) … /* lower bit position of bitfield tx_q_tc_map{q} */ #define HW_ATL2_TX_Q_TC_MAP_SHIFT(queue) … /* width of bitfield tx_q_tc_map{q} */ #define HW_ATL2_TX_Q_TC_MAP_WIDTH … /* default value of bitfield tx_q_tc_map{q} */ #define HW_ATL2_TX_Q_TC_MAP_DEFAULT … /* tx data_tc_arb_mode bitfield definitions * preprocessor definitions for the bitfield "data_tc_arb_mode". * port="pif_tps_data_tc_arb_mode_i" */ /* register address for bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR … /* bitmask for bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK … /* inverted bitmask for bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSKN … /* lower bit position of bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT … /* width of bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_WIDTH … /* default value of bitfield data_tc_arb_mode */ #define HW_ATL2_TPS_DATA_TC_ARB_MODE_DEFAULT … /* tx data_tc{t}_credit_max[f:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_data_tc0_credit_max_i[15:0]" */ /* register address for bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) … /* bitmask for bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK … /* inverted bitmask for bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN … /* lower bit position of bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT … /* width of bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH … /* default value of bitfield data_tc{t}_credit_max[f:0] */ #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT … /* tx data_tc{t}_weight[e:0] bitfield definitions * preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]". * parameter: tc {t} | stride size 0x4 | range [0, 7] * port="pif_tps_data_tc0_weight_i[14:0]" */ /* register address for bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) … /* bitmask for bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK … /* inverted bitmask for bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN … /* lower bit position of bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT … /* width of bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH … /* default value of bitfield data_tc{t}_weight[e:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT … /* tx interrupt moderation control register definitions * Preprocessor definitions for TX Interrupt Moderation Control Register * Base Address: 0x00007c28 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] */ #define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) … /* Launch time control register */ #define HW_ATL2_LT_CTRL_ADR … #define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK … #define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT … #define HW_ATL2_LT_CTRL_CLK_RATIO_MSK … #define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT … #define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED … #define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED … #define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED … #define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK … #define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT … #define HW_ATL2_LT_CTRL_LINK_SPEED_MSK … #define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT … /* FPGA VER register */ #define HW_ATL2_FPGA_VER_ADR … #define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) … /* ahb_mem_addr{f}[31:0] Bitfield Definitions * Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]". * Parameter: filter {f} | stride size 0x10 | range [0, 127] * PORT="ahb_mem_addr{f}[31:0]" */ /* Register address for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(filter) … /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSK … /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSKN … /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_SHIFT … /* Width of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_WIDTH … /* Default value of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_DEFAULT … /* Register address for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(filter) … /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSK … /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSKN … /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_SHIFT … /* Width of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_WIDTH … /* Default value of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_DEFAULT … /* Register address for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(filter) … /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSK … /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSKN … /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_SHIFT … /* Width of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_WIDTH … /* Default value of bitfield ahb_mem_addr{f}[31:0] */ #define HW_ATL2_RPF_ACT_RSLVR_ACTN_DEFAULT … /* rpf_rec_tab_en[15:0] Bitfield Definitions * Preprocessor definitions for the bitfield "rpf_rec_tab_en[15:0]". * PORT="pif_rpf_rec_tab_en[15:0]" */ /* Register address for bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_ADR … /* Bitmask for bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_MSK … /* Inverted bitmask for bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_MSKN … /* Lower bit position of bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_SHIFT … /* Width of bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_WIDTH … /* Default value of bitfield rpf_rec_tab_en[15:0] */ #define HW_ATL2_RPF_REC_TAB_EN_DEFAULT … /* Register address for firmware shared input buffer */ #define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) … /* Register address for firmware shared output buffer */ #define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) … /* pif_host_finished_buf_wr_i Bitfield Definitions * Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i". * PORT="pif_host_finished_buf_wr_i" */ /* Register address for bitfield rpif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR … /* Bitmask for bitfield pif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK … /* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN … /* Lower bit position of bitfield pif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT … /* Width of bitfield pif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH … /* Default value of bitfield pif_host_finished_buf_wr_i */ #define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT … /* pif_mcp_finished_buf_rd_i Bitfield Definitions * Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i". * PORT="pif_mcp_finished_buf_rd_i" */ /* Register address for bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_ADR … /* Bitmask for bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_MSK … /* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN … /* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT … /* Width of bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH … /* Default value of bitfield pif_mcp_finished_buf_rd_i */ #define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT … /* Register address for bitfield pif_mcp_boot_reg */ #define HW_ATL2_MIF_BOOT_REG_ADR … #define HW_ATL2_MCP_HOST_REQ_INT_READY … #define HW_ATL2_MCP_HOST_REQ_INT_ADR … #define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR … #define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR … #endif /* HW_ATL2_LLH_INTERNAL_H */
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