/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014-2024 Broadcom */ #ifndef __BCMGENET_H__ #define __BCMGENET_H__ #include <linux/skbuff.h> #include <linux/netdevice.h> #include <linux/spinlock.h> #include <linux/clk.h> #include <linux/mii.h> #include <linux/if_vlan.h> #include <linux/phy.h> #include <linux/dim.h> #include <linux/ethtool.h> #include "../unimac.h" /* total number of Buffer Descriptors, same for Rx/Tx */ #define TOTAL_DESC … /* which ring is descriptor based */ #define DESC_INDEX … /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. * 1536 is multiple of 256 bytes */ #define ENET_BRCM_TAG_LEN … #define ENET_PAD … #define ENET_MAX_MTU_SIZE … #define DMA_MAX_BURST_LENGTH … /* misc. configuration */ #define MAX_NUM_OF_FS_RULES … #define CLEAR_ALL_HFB … #define DMA_FC_THRESH_HI … #define DMA_FC_THRESH_LO … /* 64B receive/transmit status block */ struct status_64 { … }; /* Rx status bits */ #define STATUS_RX_EXT_MASK … #define STATUS_RX_CSUM_MASK … #define STATUS_RX_CSUM_OK … #define STATUS_RX_CSUM_FR … #define STATUS_RX_PROTO_TCP … #define STATUS_RX_PROTO_UDP … #define STATUS_RX_PROTO_ICMP … #define STATUS_RX_PROTO_OTHER … #define STATUS_RX_PROTO_MASK … #define STATUS_RX_PROTO_SHIFT … #define STATUS_FILTER_INDEX_MASK … /* Tx status bits */ #define STATUS_TX_CSUM_START_MASK … #define STATUS_TX_CSUM_START_SHIFT … #define STATUS_TX_CSUM_PROTO_UDP … #define STATUS_TX_CSUM_OFFSET_MASK … #define STATUS_TX_CSUM_LV … /* DMA Descriptor */ #define DMA_DESC_LENGTH_STATUS … #define DMA_DESC_ADDRESS_LO … #define DMA_DESC_ADDRESS_HI … /* Rx/Tx common counter group */ struct bcmgenet_pkt_counters { … }; /* RSV, Receive Status Vector */ struct bcmgenet_rx_counters { … }; /* TSV, Transmit Status Vector */ struct bcmgenet_tx_counters { … }; struct bcmgenet_mib_counters { … }; #define UMAC_MIB_START … #define UMAC_MDIO_CMD … #define MDIO_START_BUSY … #define MDIO_READ_FAIL … #define MDIO_RD … #define MDIO_WR … #define MDIO_PMD_SHIFT … #define MDIO_PMD_MASK … #define MDIO_REG_SHIFT … #define MDIO_REG_MASK … #define UMAC_RBUF_OVFL_CNT_V1 … #define RBUF_OVFL_CNT_V2 … #define RBUF_OVFL_CNT_V3PLUS … #define UMAC_MPD_CTRL … #define MPD_EN … #define MPD_PW_EN … #define MPD_MSEQ_LEN_SHIFT … #define MPD_MSEQ_LEN_MASK … #define UMAC_MPD_PW_MS … #define UMAC_MPD_PW_LS … #define UMAC_RBUF_ERR_CNT_V1 … #define RBUF_ERR_CNT_V2 … #define RBUF_ERR_CNT_V3PLUS … #define UMAC_MDF_ERR_CNT … #define UMAC_MDF_CTRL … #define UMAC_MDF_ADDR … #define UMAC_MIB_CTRL … #define MIB_RESET_RX … #define MIB_RESET_RUNT … #define MIB_RESET_TX … #define RBUF_CTRL … #define RBUF_64B_EN … #define RBUF_ALIGN_2B … #define RBUF_BAD_DIS … #define RBUF_STATUS … #define RBUF_STATUS_WOL … #define RBUF_STATUS_MPD_INTR_ACTIVE … #define RBUF_STATUS_ACPI_INTR_ACTIVE … #define RBUF_CHK_CTRL … #define RBUF_RXCHK_EN … #define RBUF_SKIP_FCS … #define RBUF_L3_PARSE_DIS … #define RBUF_ENERGY_CTRL … #define RBUF_EEE_EN … #define RBUF_PM_EN … #define RBUF_TBUF_SIZE_CTRL … #define RBUF_HFB_CTRL_V1 … #define RBUF_HFB_FILTER_EN_SHIFT … #define RBUF_HFB_FILTER_EN_MASK … #define RBUF_HFB_EN … #define RBUF_HFB_256B … #define RBUF_ACPI_EN … #define RBUF_HFB_LEN_V1 … #define RBUF_FLTR_LEN_MASK … #define RBUF_FLTR_LEN_SHIFT … #define TBUF_CTRL … #define TBUF_64B_EN … #define TBUF_BP_MC … #define TBUF_ENERGY_CTRL … #define TBUF_EEE_EN … #define TBUF_PM_EN … #define TBUF_CTRL_V1 … #define TBUF_BP_MC_V1 … #define HFB_CTRL … #define HFB_FLT_ENABLE_V3PLUS … #define HFB_FLT_LEN_V2 … #define HFB_FLT_LEN_V3PLUS … /* uniMac intrl2 registers */ #define INTRL2_CPU_STAT … #define INTRL2_CPU_SET … #define INTRL2_CPU_CLEAR … #define INTRL2_CPU_MASK_STATUS … #define INTRL2_CPU_MASK_SET … #define INTRL2_CPU_MASK_CLEAR … /* INTRL2 instance 0 definitions */ #define UMAC_IRQ_SCB … #define UMAC_IRQ_EPHY … #define UMAC_IRQ_PHY_DET_R … #define UMAC_IRQ_PHY_DET_F … #define UMAC_IRQ_LINK_UP … #define UMAC_IRQ_LINK_DOWN … #define UMAC_IRQ_LINK_EVENT … #define UMAC_IRQ_UMAC … #define UMAC_IRQ_UMAC_TSV … #define UMAC_IRQ_TBUF_UNDERRUN … #define UMAC_IRQ_RBUF_OVERFLOW … #define UMAC_IRQ_HFB_SM … #define UMAC_IRQ_HFB_MM … #define UMAC_IRQ_MPD_R … #define UMAC_IRQ_WAKE_EVENT … #define UMAC_IRQ_RXDMA_MBDONE … #define UMAC_IRQ_RXDMA_PDONE … #define UMAC_IRQ_RXDMA_BDONE … #define UMAC_IRQ_RXDMA_DONE … #define UMAC_IRQ_TXDMA_MBDONE … #define UMAC_IRQ_TXDMA_PDONE … #define UMAC_IRQ_TXDMA_BDONE … #define UMAC_IRQ_TXDMA_DONE … /* Only valid for GENETv3+ */ #define UMAC_IRQ_MDIO_DONE … #define UMAC_IRQ_MDIO_ERROR … /* INTRL2 instance 1 definitions */ #define UMAC_IRQ1_TX_INTR_MASK … #define UMAC_IRQ1_RX_INTR_MASK … #define UMAC_IRQ1_RX_INTR_SHIFT … /* Register block offsets */ #define GENET_SYS_OFF … #define GENET_GR_BRIDGE_OFF … #define GENET_EXT_OFF … #define GENET_INTRL2_0_OFF … #define GENET_INTRL2_1_OFF … #define GENET_RBUF_OFF … #define GENET_UMAC_OFF … /* SYS block offsets and register definitions */ #define SYS_REV_CTRL … #define SYS_PORT_CTRL … #define PORT_MODE_INT_EPHY … #define PORT_MODE_INT_GPHY … #define PORT_MODE_EXT_EPHY … #define PORT_MODE_EXT_GPHY … #define PORT_MODE_EXT_RVMII_25 … #define PORT_MODE_EXT_RVMII_50 … #define LED_ACT_SOURCE_MAC … #define SYS_RBUF_FLUSH_CTRL … #define SYS_TBUF_FLUSH_CTRL … #define RBUF_FLUSH_CTRL_V1 … /* Ext block register offsets and definitions */ #define EXT_EXT_PWR_MGMT … #define EXT_PWR_DOWN_BIAS … #define EXT_PWR_DOWN_DLL … #define EXT_PWR_DOWN_PHY … #define EXT_PWR_DN_EN_LD … #define EXT_ENERGY_DET … #define EXT_IDDQ_FROM_PHY … #define EXT_IDDQ_GLBL_PWR … #define EXT_PHY_RESET … #define EXT_ENERGY_DET_MASK … #define EXT_PWR_DOWN_PHY_TX … #define EXT_PWR_DOWN_PHY_RX … #define EXT_PWR_DOWN_PHY_SD … #define EXT_PWR_DOWN_PHY_RD … #define EXT_PWR_DOWN_PHY_EN … #define EXT_RGMII_OOB_CTRL … #define RGMII_MODE_EN_V123 … #define RGMII_LINK … #define OOB_DISABLE … #define RGMII_MODE_EN … #define ID_MODE_DIS … #define EXT_GPHY_CTRL … #define EXT_CFG_IDDQ_BIAS … #define EXT_CFG_PWR_DOWN … #define EXT_CK25_DIS … #define EXT_CFG_IDDQ_GLOBAL_PWR … #define EXT_GPHY_RESET … /* DMA rings size */ #define DMA_RING_SIZE … #define DMA_RINGS_SIZE … /* DMA registers common definitions */ #define DMA_RW_POINTER_MASK … #define DMA_P_INDEX_DISCARD_CNT_MASK … #define DMA_P_INDEX_DISCARD_CNT_SHIFT … #define DMA_BUFFER_DONE_CNT_MASK … #define DMA_BUFFER_DONE_CNT_SHIFT … #define DMA_P_INDEX_MASK … #define DMA_C_INDEX_MASK … /* DMA ring size register */ #define DMA_RING_SIZE_MASK … #define DMA_RING_SIZE_SHIFT … #define DMA_RING_BUFFER_SIZE_MASK … /* DMA interrupt threshold register */ #define DMA_INTR_THRESHOLD_MASK … /* DMA XON/XOFF register */ #define DMA_XON_THREHOLD_MASK … #define DMA_XOFF_THRESHOLD_MASK … #define DMA_XOFF_THRESHOLD_SHIFT … /* DMA flow period register */ #define DMA_FLOW_PERIOD_MASK … #define DMA_MAX_PKT_SIZE_MASK … #define DMA_MAX_PKT_SIZE_SHIFT … /* DMA control register */ #define DMA_EN … #define DMA_RING_BUF_EN_SHIFT … #define DMA_RING_BUF_EN_MASK … #define DMA_TSB_SWAP_EN … /* DMA status register */ #define DMA_DISABLED … #define DMA_DESC_RAM_INIT_BUSY … /* DMA SCB burst size register */ #define DMA_SCB_BURST_SIZE_MASK … /* DMA activity vector register */ #define DMA_ACTIVITY_VECTOR_MASK … /* DMA backpressure mask register */ #define DMA_BACKPRESSURE_MASK … #define DMA_PFC_ENABLE … /* DMA backpressure status register */ #define DMA_BACKPRESSURE_STATUS_MASK … /* DMA override register */ #define DMA_LITTLE_ENDIAN_MODE … #define DMA_REGISTER_MODE … /* DMA timeout register */ #define DMA_TIMEOUT_MASK … #define DMA_TIMEOUT_VAL … /* TDMA rate limiting control register */ #define DMA_RATE_LIMIT_EN_MASK … /* TDMA arbitration control register */ #define DMA_ARBITER_MODE_MASK … #define DMA_RING_BUF_PRIORITY_MASK … #define DMA_RING_BUF_PRIORITY_SHIFT … #define DMA_PRIO_REG_INDEX(q) … #define DMA_PRIO_REG_SHIFT(q) … #define DMA_RATE_ADJ_MASK … /* Tx/Rx Dma Descriptor common bits*/ #define DMA_BUFLENGTH_MASK … #define DMA_BUFLENGTH_SHIFT … #define DMA_OWN … #define DMA_EOP … #define DMA_SOP … #define DMA_WRAP … /* Tx specific Dma descriptor bits */ #define DMA_TX_UNDERRUN … #define DMA_TX_APPEND_CRC … #define DMA_TX_OW_CRC … #define DMA_TX_DO_CSUM … #define DMA_TX_QTAG_SHIFT … /* Rx Specific Dma descriptor bits */ #define DMA_RX_CHK_V3PLUS … #define DMA_RX_CHK_V12 … #define DMA_RX_BRDCAST … #define DMA_RX_MULT … #define DMA_RX_LG … #define DMA_RX_NO … #define DMA_RX_RXER … #define DMA_RX_CRC_ERROR … #define DMA_RX_OV … #define DMA_RX_FI_MASK … #define DMA_RX_FI_SHIFT … #define DMA_DESC_ALLOC_MASK … #define DMA_ARBITER_RR … #define DMA_ARBITER_WRR … #define DMA_ARBITER_SP … struct enet_cb { … }; /* power management mode */ enum bcmgenet_power_mode { … }; struct bcmgenet_priv; /* We support both runtime GENET detection and compile-time * to optimize code-paths for a given hardware */ enum bcmgenet_version { … }; #define GENET_IS_V1(p) … #define GENET_IS_V2(p) … #define GENET_IS_V3(p) … #define GENET_IS_V4(p) … #define GENET_IS_V5(p) … /* Hardware flags */ #define GENET_HAS_40BITS … #define GENET_HAS_EXT … #define GENET_HAS_MDIO_INTR … #define GENET_HAS_MOCA_LINK_DET … /* BCMGENET hardware parameters, keep this structure nicely aligned * since it is going to be used in hot paths */ struct bcmgenet_hw_params { … }; struct bcmgenet_skb_cb { … }; #define GENET_CB(skb) … struct bcmgenet_tx_ring { … }; struct bcmgenet_net_dim { … }; struct bcmgenet_rx_ring { … }; enum bcmgenet_rxnfc_state { … }; struct bcmgenet_rxnfc_rule { … }; /* device context */ struct bcmgenet_priv { … }; #define GENET_IO_MACRO(name, offset) … GENET_IO_MACRO(ext, GENET_EXT_OFF); GENET_IO_MACRO(umac, GENET_UMAC_OFF); GENET_IO_MACRO(sys, GENET_SYS_OFF); /* interrupt l2 registers accessors */ GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); /* HFB register accessors */ GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); /* GENET v2+ HFB control and filter len helpers */ GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); /* RBUF register accessors */ GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); /* MDIO routines */ int bcmgenet_mii_init(struct net_device *dev); int bcmgenet_mii_config(struct net_device *dev, bool init); int bcmgenet_mii_probe(struct net_device *dev); void bcmgenet_mii_exit(struct net_device *dev); void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx); void bcmgenet_phy_power_set(struct net_device *dev, bool enable); void bcmgenet_mii_setup(struct net_device *dev); /* Wake-on-LAN routines */ void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, enum bcmgenet_power_mode mode); void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, enum bcmgenet_power_mode mode); void bcmgenet_eee_enable_set(struct net_device *dev, bool enable, bool tx_lpi_enabled); #endif /* __BCMGENET_H__ */
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