/* Copyright 2008-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation * All rights reserved * * Unless you and QLogic execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2, available * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Qlogic software provided under a * license other than the GPL, without Qlogic's express prior written * consent. * * Written by Yaniv Rosner * */ #ifndef BNX2X_LINK_H #define BNX2X_LINK_H /***********************************************************/ /* Defines */ /***********************************************************/ #define DEFAULT_PHY_DEV_ADDR … #define E2_DEFAULT_PHY_DEV_ADDR … #define BNX2X_FLOW_CTRL_AUTO … #define BNX2X_FLOW_CTRL_TX … #define BNX2X_FLOW_CTRL_RX … #define BNX2X_FLOW_CTRL_BOTH … #define BNX2X_FLOW_CTRL_NONE … #define NET_SERDES_IF_XFI … #define NET_SERDES_IF_SFI … #define NET_SERDES_IF_KR … #define NET_SERDES_IF_DXGXS … #define SPEED_AUTO_NEG … #define SPEED_20000 … #define I2C_DEV_ADDR_A0 … #define I2C_DEV_ADDR_A2 … #define SFP_EEPROM_PAGE_SIZE … #define SFP_EEPROM_VENDOR_NAME_ADDR … #define SFP_EEPROM_VENDOR_NAME_SIZE … #define SFP_EEPROM_VENDOR_OUI_ADDR … #define SFP_EEPROM_VENDOR_OUI_SIZE … #define SFP_EEPROM_PART_NO_ADDR … #define SFP_EEPROM_PART_NO_SIZE … #define SFP_EEPROM_REVISION_ADDR … #define SFP_EEPROM_REVISION_SIZE … #define SFP_EEPROM_SERIAL_ADDR … #define SFP_EEPROM_SERIAL_SIZE … #define SFP_EEPROM_DATE_ADDR … #define SFP_EEPROM_DATE_SIZE … #define SFP_EEPROM_DIAG_TYPE_ADDR … #define SFP_EEPROM_DIAG_TYPE_SIZE … #define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ … #define SFP_EEPROM_DDM_IMPLEMENTED … #define SFP_EEPROM_SFF_8472_COMP_ADDR … #define SFP_EEPROM_SFF_8472_COMP_SIZE … #define SFP_EEPROM_A2_CHECKSUM_RANGE … #define SFP_EEPROM_A2_CC_DMI_ADDR … #define PWR_FLT_ERR_MSG_LEN … #define XGXS_EXT_PHY_TYPE(ext_phy_config) … #define XGXS_EXT_PHY_ADDR(ext_phy_config) … #define SERDES_EXT_PHY_TYPE(ext_phy_config) … /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ #define SINGLE_MEDIA_DIRECT(params) … /* Single Media board contains single external phy */ #define SINGLE_MEDIA(params) … /* Dual Media board contains two external phy with different media */ #define DUAL_MEDIA(params) … #define FW_PARAM_PHY_ADDR_MASK … #define FW_PARAM_PHY_TYPE_MASK … #define FW_PARAM_MDIO_CTRL_MASK … #define FW_PARAM_MDIO_CTRL_OFFSET … #define FW_PARAM_PHY_ADDR(fw_param) … #define FW_PARAM_PHY_TYPE(fw_param) … #define FW_PARAM_MDIO_CTRL(fw_param) … #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) … #define PFC_BRB_FULL_LB_XOFF_THRESHOLD … #define PFC_BRB_FULL_LB_XON_THRESHOLD … #define MAXVAL(a, b) … #define BMAC_CONTROL_RX_ENABLE … /***********************************************************/ /* Structs */ /***********************************************************/ #define INT_PHY … #define EXT_PHY1 … #define EXT_PHY2 … #define MAX_PHYS … /* Same configuration is shared between the XGXS and the first external phy */ #define LINK_CONFIG_SIZE … #define LINK_CONFIG_IDX(_phy_idx) … /***********************************************************/ /* bnx2x_phy struct */ /* Defines the required arguments and function per phy */ /***********************************************************/ struct link_vars; struct link_params; struct bnx2x_phy; config_init_t; read_status_t; link_reset_t; config_loopback_t; format_fw_ver_t; hw_reset_t; set_link_led_t; phy_specific_func_t; struct bnx2x_reg_set { … }; struct bnx2x_phy { … }; /* Inputs parameters to the CLC */ struct link_params { … }; /* Output parameters */ struct link_vars { … }; /***********************************************************/ /* Functions */ /***********************************************************/ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars); /* Reset the link. Should be called when driver or interface goes down Before calling phy firmware upgrade, the reset_ext_phy should be set to 0 */ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars, u8 reset_ext_phy); int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars); /* bnx2x_link_update should be called upon link interrupt */ int bnx2x_link_update(struct link_params *params, struct link_vars *vars); /* use the following phy functions to read/write from external_phy In order to use it to read/write internal phy registers, use DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as the register */ int bnx2x_phy_read(struct link_params *params, u8 phy_addr, u8 devad, u16 reg, u16 *ret_val); int bnx2x_phy_write(struct link_params *params, u8 phy_addr, u8 devad, u16 reg, u16 val); /* Reads the link_status from the shmem, and update the link vars accordingly */ void bnx2x_link_status_update(struct link_params *input, struct link_vars *output); /* returns string representing the fw_version of the external phy */ int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version, u16 len); /* Set/Unset the led Basically, the CLC takes care of the led for the link, but in case one needs to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink the led, and LED_MODE_OFF to set the led off.*/ int bnx2x_set_led(struct link_params *params, struct link_vars *vars, u8 mode, u32 speed); #define LED_MODE_OFF … #define LED_MODE_ON … #define LED_MODE_OPER … #define LED_MODE_FRONT_PANEL_OFF … /* bnx2x_handle_module_detect_int should be called upon module detection interrupt */ void bnx2x_handle_module_detect_int(struct link_params *params); /* Get the actual link status. In case it returns 0, link is up, otherwise link is down*/ int bnx2x_test_link(struct link_params *params, struct link_vars *vars, u8 is_serdes); /* One-time initialization for external phy after power up */ int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], u32 shmem2_base_path[], u32 chip_id); /* Reset the external PHY using GPIO */ void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); /* Reset the external of SFX7101 */ void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy); /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, struct link_params *params, u8 dev_addr, u16 addr, u16 byte_cnt, u8 *o_buf); void bnx2x_hw_reset_phy(struct link_params *params); /* Check swap bit and adjust PHY order */ u32 bnx2x_phy_selection(struct link_params *params); /* Probe the phys on board, and populate them in "params" */ int bnx2x_phy_probe(struct link_params *params); /* Checks if fan failure detection is required on one of the phys on board */ u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base, u8 port); /* Open / close the gate between the NIG and the BRB */ void bnx2x_set_rx_filter(struct link_params *params, u8 en); /* DCBX structs */ /* Number of maximum COS per chip */ #define DCBX_E2E3_MAX_NUM_COS … #define DCBX_E3B0_MAX_NUM_COS_PORT0 … #define DCBX_E3B0_MAX_NUM_COS_PORT1 … #define DCBX_E3B0_MAX_NUM_COS … #define DCBX_MAX_NUM_COS … /* PFC port configuration params */ struct bnx2x_nig_brb_pfc_port_params { … }; /* ETS port configuration params */ struct bnx2x_ets_bw_params { … }; struct bnx2x_ets_sp_params { … }; enum bnx2x_cos_state { … }; struct bnx2x_ets_cos_params { … }; struct bnx2x_ets_params { … }; /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB * when link is already up */ int bnx2x_update_pfc(struct link_params *params, struct link_vars *vars, struct bnx2x_nig_brb_pfc_port_params *pfc_params); /* Used to configure the ETS to disable */ int bnx2x_ets_disabled(struct link_params *params, struct link_vars *vars); /* Used to configure the ETS to BW limited */ void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, const u32 cos1_bw); /* Used to configure the ETS to strict */ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos); /* Configure the COS to ETS according to BW and SP settings.*/ int bnx2x_ets_e3b0_config(const struct link_params *params, const struct link_vars *vars, struct bnx2x_ets_params *ets_params); void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, u32 chip_id, u32 shmem_base, u32 shmem2_base, u8 port); void bnx2x_period_func(struct link_params *params, struct link_vars *vars); #endif /* BNX2X_LINK_H */
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