/* bnx2x.h: QLogic Everest network driver. * * Copyright (c) 2007-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation * All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Maintained by: Ariel Elior <[email protected]> * Written by: Eliezer Tamir * Based on code from Michael Chan's bnx2 driver */ #ifndef BNX2X_H #define BNX2X_H #include <linux/pci.h> #include <linux/netdevice.h> #include <linux/dma-mapping.h> #include <linux/types.h> #include <linux/pci_regs.h> #include <linux/ptp_clock_kernel.h> #include <linux/net_tstamp.h> #include <linux/timecounter.h> /* compilation time flags */ /* define this to make the driver freeze on error to allow getting debug info * (you will need to reboot afterwards) */ /* #define BNX2X_STOP_ON_ERROR */ /* FIXME: Delete the DRV_MODULE_VERSION below, but please be warned * that it is not an easy task because such change has all chances * to break this driver due to amount of abuse of in-kernel interfaces * between modules and FW. * * DO NOT UPDATE DRV_MODULE_VERSION below. */ #define DRV_MODULE_VERSION … #define BNX2X_BC_VER … #if defined(CONFIG_DCB) #define BCM_DCBNL #endif #include "bnx2x_hsi.h" #include "../cnic_if.h" #define BNX2X_MIN_MSIX_VEC_CNT(bp) … #include <linux/mdio.h> #include "bnx2x_reg.h" #include "bnx2x_fw_defs.h" #include "bnx2x_mfw_req.h" #include "bnx2x_link.h" #include "bnx2x_sp.h" #include "bnx2x_dcb.h" #include "bnx2x_stats.h" #include "bnx2x_vfpf.h" enum bnx2x_int_mode { … }; /* error/debug prints */ #define DRV_MODULE_NAME … /* for messages that are currently off */ #define BNX2X_MSG_OFF … #define BNX2X_MSG_MCP … #define BNX2X_MSG_STATS … #define BNX2X_MSG_NVM … #define BNX2X_MSG_DMAE … #define BNX2X_MSG_SP … #define BNX2X_MSG_FP … #define BNX2X_MSG_IOV … #define BNX2X_MSG_PTP … #define BNX2X_MSG_IDLE … #define BNX2X_MSG_ETHTOOL … #define BNX2X_MSG_DCB … /* regular debug print */ #define DP_INNER(fmt, ...) … #define DP(__mask, fmt, ...) … #define DP_AND(__mask, fmt, ...) … #define DP_CONT(__mask, fmt, ...) … /* errors debug print */ #define BNX2X_DBG_ERR(fmt, ...) … /* for errors (never masked) */ #define BNX2X_ERR(fmt, ...) … #define BNX2X_ERROR(fmt, ...) … /* before we have a dev->name use dev_info() */ #define BNX2X_DEV_INFO(fmt, ...) … /* Error handling */ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); #ifdef BNX2X_STOP_ON_ERROR #define bnx2x_panic … #else #define bnx2x_panic() … #endif #define bnx2x_mc_addr(ha) … #define bnx2x_uc_addr(ha) … #define U64_LO(x) … #define U64_HI(x) … #define HILO_U64(hi, lo) … #define REG_ADDR(bp, offset) … #define REG_RD(bp, offset) … #define REG_RD8(bp, offset) … #define REG_RD16(bp, offset) … #define REG_WR_RELAXED(bp, offset, val) … #define REG_WR16_RELAXED(bp, offset, val) … #define REG_WR(bp, offset, val) … #define REG_WR8(bp, offset, val) … #define REG_WR16(bp, offset, val) … #define REG_RD_IND(bp, offset) … #define REG_WR_IND(bp, offset, val) … #define REG_RD_DMAE(bp, offset, valp, len32) … #define REG_WR_DMAE(bp, offset, valp, len32) … #define REG_WR_DMAE_LEN(bp, offset, valp, len32) … #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) … #define SHMEM_ADDR(bp, field) … #define SHMEM_RD(bp, field) … #define SHMEM_WR(bp, field, val) … #define SHMEM2_ADDR(bp, field) … #define SHMEM2_RD(bp, field) … #define SHMEM2_WR(bp, field, val) … #define MF_CFG_ADDR(bp, field) … #define MF2_CFG_ADDR(bp, field) … #define MF_CFG_RD(bp, field) … #define MF_CFG_WR(bp, field, val) … #define MF2_CFG_RD(bp, field) … #define SHMEM2_HAS(bp, field) … #define EMAC_RD(bp, reg) … #define EMAC_WR(bp, reg, val) … /* SP SB indices */ /* General SP events - stats query, cfc delete, etc */ #define HC_SP_INDEX_ETH_DEF_CONS … /* EQ completions */ #define HC_SP_INDEX_EQ_CONS … /* FCoE L2 connection completions */ #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS … #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS … /* iSCSI L2 */ #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS … #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS … /* Special clients parameters */ /* SB indices */ /* FCoE L2 */ #define BNX2X_FCOE_L2_RX_INDEX … #define BNX2X_FCOE_L2_TX_INDEX … /** * CIDs and CLIDs: * CLIDs below is a CLID for func 0, then the CLID for other * functions will be calculated by the formula: * * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X * */ enum { … }; /* use a value high enough to be above all the PFs, which has least significant * nibble as 8, so when cnic needs to come up with a CID for UIO to use to * calculate doorbell address according to old doorbell configuration scheme * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number * We must avoid coming up with cid 8 for iscsi since according to this method * the designated UIO cid will come out 0 and it has a special handling for that * case which doesn't suit us. Therefore will will cieling to closes cid which * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. */ #define BNX2X_1st_NON_L2_ETH_CID(bp) … /* amount of cids traversed by UIO's DPM addition to doorbell */ #define UIO_DPM … /* roundup to DPM offset */ #define UIO_ROUNDUP(bp) … /* offset to nearest value which has lsb nibble matching DPM */ #define UIO_CID_OFFSET(bp) … /* add offset to rounded-up cid to get a value which could be used with UIO */ #define UIO_DPM_ALIGN(bp) … /* but wait - avoid UIO special case for cid 0 */ #define UIO_DPM_CID0_OFFSET(bp) … /* Properly DPM aligned CID dajusted to cid 0 secal case */ #define BNX2X_CNIC_START_ETH_CID(bp) … /* how many cids were wasted - need this value for cid allocation */ #define UIO_CID_PAD(bp) … /* iSCSI L2 */ #define BNX2X_ISCSI_ETH_CID(bp) … /* FCoE L2 */ #define BNX2X_FCOE_ETH_CID(bp) … #define CNIC_SUPPORT(bp) … #define CNIC_ENABLED(bp) … #define CNIC_LOADED(bp) … #define FCOE_INIT(bp) … #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR … #define SM_RX_ID … #define SM_TX_ID … /* defines for multiple tx priority indices */ #define FIRST_TX_ONLY_COS_INDEX … #define FIRST_TX_COS_INDEX … /* rules for calculating the cids of tx-only connections */ #define CID_TO_FP(cid, bp) … #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) … /* fp index inside class of service range */ #define FP_COS_TO_TXQ(fp, cos, bp) … /* Indexes for transmission queues array: * txdata for RSS i CoS j is at location i + (j * num of RSS) * txdata for FCoE (if exist) is at location max cos * num of RSS * txdata for FWD (if exist) is one location after FCoE * txdata for OOO (if exist) is one location after FWD */ enum { … }; #define MAX_ETH_TXQ_IDX(bp) … #define FCOE_TXQ_IDX(bp) … /* fast path */ /* * This driver uses new build_skb() API : * RX ring buffer contains pointer to kmalloc() data only, * skb are built only after Hardware filled the frame. */ struct sw_rx_bd { … }; struct sw_tx_bd { … }; struct sw_rx_page { … }; db_prod; /* dropless fc FW/HW related params */ #define BRB_SIZE(bp) … #define MAX_AGG_QS(bp) … #define FW_DROP_LEVEL(bp) … #define FW_PREFETCH_CNT … #define DROPLESS_FC_HEADROOM … /* MC hsi */ #define BCM_PAGE_SHIFT … #define BCM_PAGE_SIZE … #define BCM_PAGE_MASK … #define BCM_PAGE_ALIGN(addr) … #define PAGES_PER_SGE_SHIFT … #define PAGES_PER_SGE … #define SGE_PAGE_SHIFT … #define SGE_PAGE_SIZE … #define SGE_PAGE_MASK … #define SGE_PAGE_ALIGN(addr) … #define SGE_PAGES … #define TPA_AGG_SIZE … /* SGE ring related macros */ #define NUM_RX_SGE_PAGES … #define RX_SGE_CNT … #define NEXT_PAGE_SGE_DESC_CNT … #define MAX_RX_SGE_CNT … /* RX_SGE_CNT is promised to be a power of 2 */ #define RX_SGE_MASK … #define NUM_RX_SGE … #define MAX_RX_SGE … #define NEXT_SGE_IDX(x) … #define RX_SGE(x) … /* * Number of required SGEs is the sum of two: * 1. Number of possible opened aggregations (next packet for * these aggregations will probably consume SGE immediately) * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only * after placement on BD for new TPA aggregation) * * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page */ #define NUM_SGE_REQ … #define NUM_SGE_PG_REQ … #define SGE_TH_LO(bp) … #define SGE_TH_HI(bp) … /* Manipulate a bit vector defined as an array of u64 */ /* Number of bits in one sge_mask array element */ #define BIT_VEC64_ELEM_SZ … #define BIT_VEC64_ELEM_SHIFT … #define BIT_VEC64_ELEM_MASK … #define __BIT_VEC64_SET_BIT(el, bit) … #define __BIT_VEC64_CLEAR_BIT(el, bit) … #define BIT_VEC64_SET_BIT(vec64, idx) … #define BIT_VEC64_CLEAR_BIT(vec64, idx) … #define BIT_VEC64_TEST_BIT(vec64, idx) … /* Creates a bitmask of all ones in less significant bits. idx - index of the most significant bit in the created mask */ #define BIT_VEC64_ONES_MASK(idx) … #define BIT_VEC64_ELEM_ONE_MASK … /*******************************************************/ /* Number of u64 elements in SGE mask array */ #define RX_SGE_MASK_LEN … #define RX_SGE_MASK_LEN_MASK … #define NEXT_SGE_MASK_ELEM(el) … host_hc_status_block; struct bnx2x_agg_info { … }; #define Q_STATS_OFFSET32(stat_name) … struct bnx2x_fp_txdata { … }; enum bnx2x_tpa_mode_t { … }; struct bnx2x_alloc_pool { … }; struct bnx2x_fastpath { … }; #define bnx2x_fp(bp, nr, var) … #define bnx2x_sp_obj(bp, fp) … #define bnx2x_fp_stats(bp, fp) … #define bnx2x_fp_qstats(bp, fp) … /* Use 2500 as a mini-jumbo MTU for FCoE */ #define BNX2X_FCOE_MINI_JUMBO_MTU … #define FCOE_IDX_OFFSET … #define FCOE_IDX(bp) … #define bnx2x_fcoe_fp(bp) … #define bnx2x_fcoe(bp, var) … #define bnx2x_fcoe_inner_sp_obj(bp) … #define bnx2x_fcoe_sp_obj(bp, var) … #define bnx2x_fcoe_tx(bp, var) … #define IS_ETH_FP(fp) … #define IS_FCOE_FP(fp) … #define IS_FCOE_IDX(idx) … /* MC hsi */ #define MAX_FETCH_BD … #define RX_COPY_THRESH … #define NUM_TX_RINGS … #define TX_DESC_CNT … #define NEXT_PAGE_TX_DESC_CNT … #define MAX_TX_DESC_CNT … #define NUM_TX_BD … #define MAX_TX_BD … #define MAX_TX_AVAIL … #define NEXT_TX_IDX(x) … #define TX_BD(x) … #define TX_BD_POFF(x) … /* number of NEXT_PAGE descriptors may be required during placement */ #define NEXT_CNT_PER_TX_PKT(bds) … /* max BDs per tx packet w/o next_pages: * START_BD - describes packed * START_BD(splitted) - includes unpaged data segment for GSO * PARSING_BD - for TSO and CSUM data * PARSING_BD2 - for encapsulation data * Frag BDs - describes pages for frags */ #define BDS_PER_TX_PKT … #define MAX_BDS_PER_TX_PKT … /* max BDs per tx packet including next pages */ #define MAX_DESC_PER_TX_PKT … /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ #define NUM_RX_RINGS … #define RX_DESC_CNT … #define NEXT_PAGE_RX_DESC_CNT … #define MAX_RX_DESC_CNT … #define RX_DESC_MASK … #define NUM_RX_BD … #define MAX_RX_BD … #define MAX_RX_AVAIL … /* dropless fc calculations for BDs * * Number of BDs should as number of buffers in BRB: * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT * "next" elements on each page */ #define NUM_BD_REQ … #define NUM_BD_PG_REQ … #define BD_TH_LO(bp) … #define BD_TH_HI(bp) … #define MIN_RX_AVAIL … #define MIN_RX_SIZE_TPA_HW … #define MIN_RX_SIZE_NONTPA_HW … #define MIN_RX_SIZE_TPA … #define MIN_RX_SIZE_NONTPA … #define NEXT_RX_IDX(x) … #define RX_BD(x) … /* * As long as CQE is X times bigger than BD entry we have to allocate X times * more pages for CQ ring in order to keep it balanced with BD ring */ #define CQE_BD_REL … #define NUM_RCQ_RINGS … #define RCQ_DESC_CNT … #define NEXT_PAGE_RCQ_DESC_CNT … #define MAX_RCQ_DESC_CNT … #define NUM_RCQ_BD … #define MAX_RCQ_BD … #define MAX_RCQ_AVAIL … #define NEXT_RCQ_IDX(x) … #define RCQ_BD(x) … /* dropless fc calculations for RCQs * * Number of RCQs should be as number of buffers in BRB: * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT * "next" elements on each page */ #define NUM_RCQ_REQ … #define NUM_RCQ_PG_REQ … #define RCQ_TH_LO(bp) … #define RCQ_TH_HI(bp) … /* This is needed for determining of last_max */ #define SUB_S16(a, b) … #define SUB_S32(a, b) … #define BNX2X_SWCID_SHIFT … #define BNX2X_SWCID_MASK … /* used on a CID received from the HW */ #define SW_CID(x) … #define CQE_CMD(x) … #define BD_UNMAP_ADDR(bd) … #define BD_UNMAP_LEN(bd) … #define BNX2X_DB_MIN_SHIFT … #define BNX2X_DB_SHIFT … #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) #error "Min DB doorbell stride is 8" #endif #define DOORBELL_RELAXED(bp, cid, val) … /* TX CSUM helpers */ #define SKB_CS_OFF(skb) … #define SKB_CS(skb) … #define pbd_tcp_flags(tcp_hdr) … #define XMIT_PLAIN … #define XMIT_CSUM_V4 … #define XMIT_CSUM_V6 … #define XMIT_CSUM_TCP … #define XMIT_GSO_V4 … #define XMIT_GSO_V6 … #define XMIT_CSUM_ENC_V4 … #define XMIT_CSUM_ENC_V6 … #define XMIT_GSO_ENC_V4 … #define XMIT_GSO_ENC_V6 … #define XMIT_CSUM_ENC … #define XMIT_GSO_ENC … #define XMIT_CSUM … #define XMIT_GSO … /* stuff added to make the code fit 80Col */ #define CQE_TYPE(cqe_fp_flags) … #define CQE_TYPE_START(cqe_type) … #define CQE_TYPE_STOP(cqe_type) … #define CQE_TYPE_SLOW(cqe_type) … #define CQE_TYPE_FAST(cqe_type) … #define ETH_RX_ERROR_FALGS … #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) … #define BNX2X_RX_SUM_FIX(cqe) … #define FP_USB_FUNC_OFF … #define FP_CSB_FUNC_OFF … #define HC_INDEX_ETH_RX_CQ_CONS … #define HC_INDEX_OOO_TX_CQ_CONS … #define HC_INDEX_ETH_TX_CQ_CONS_COS0 … #define HC_INDEX_ETH_TX_CQ_CONS_COS1 … #define HC_INDEX_ETH_TX_CQ_CONS_COS2 … #define HC_INDEX_ETH_FIRST_TX_CQ_CONS … #define BNX2X_RX_SB_INDEX … #define BNX2X_TX_SB_INDEX_BASE … #define BNX2X_TX_SB_INDEX_COS0 … /* end of fast path */ /* common */ struct bnx2x_common { … }; /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ #define BNX2X_IGU_STAS_MSG_VF_CNT … #define BNX2X_IGU_STAS_MSG_PF_CNT … #define MAX_IGU_ATTN_ACK_TO … /* end of common */ /* port */ struct bnx2x_port { … }; /* end of port */ #define STATS_OFFSET32(stat_name) … /* slow path */ #define BNX2X_MAX_NUM_OF_VFS … #define BNX2X_VF_CID_WND … #define BNX2X_CIDS_PER_VF … /* We need to reserve doorbell addresses for all VF and queue combinations */ #define BNX2X_VF_CIDS … /* The doorbell is configured to have the same number of CIDs for PFs and for * VFs. For this reason the PF CID zone is as large as the VF zone. */ #define BNX2X_FIRST_VF_CID … #define BNX2X_MAX_NUM_VF_QUEUES … #define BNX2X_VF_ID_INVALID … /* the number of VF CIDS multiplied by the amount of bytes reserved for each * cid must not exceed the size of the VF doorbell */ #define BNX2X_VF_BAR_SIZE … #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) #error "VF doorbell bar size is 512" #endif /* * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is * control by the number of fast-path status blocks supported by the * device (HW/FW). Each fast-path status block (FP-SB) aka non-default * status block represents an independent interrupts context that can * serve a regular L2 networking queue. However special L2 queues such * as the FCoE queue do not require a FP-SB and other components like * the CNIC may consume FP-SB reducing the number of possible L2 queues * * If the maximum number of FP-SB available is X then: * a. If CNIC is supported it consumes 1 FP-SB thus the max number of * regular L2 queues is Y=X-1 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) * c. If the FCoE L2 queue is supported the actual number of L2 queues * is Y+1 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for * slow-path interrupts) or Y+2 if CNIC is supported (one additional * FP interrupt context for the CNIC). * e. The number of HW context (CID count) is always X or X+1 if FCoE * L2 queue is supported. The cid for the FCoE L2 queue is always X. */ /* fast-path interrupt contexts E1x */ #define FP_SB_MAX_E1x … /* fast-path interrupt contexts E2 */ #define FP_SB_MAX_E2 … cdu_context; /* CDU host DB constants */ #define CDU_ILT_PAGE_SZ_HW … #define CDU_ILT_PAGE_SZ … #define ILT_PAGE_CIDS … #define CNIC_ISCSI_CID_MAX … #define CNIC_FCOE_CID_MAX … #define CNIC_CID_MAX … #define CNIC_ILT_LINES … #define QM_ILT_PAGE_SZ_HW … #define QM_ILT_PAGE_SZ … #define QM_CID_ROUND … /* TM (timers) host DB constants */ #define TM_ILT_PAGE_SZ_HW … #define TM_ILT_PAGE_SZ … #define TM_CONN_NUM … #define TM_ILT_SZ … #define TM_ILT_LINES … /* SRC (Searcher) host DB constants */ #define SRC_ILT_PAGE_SZ_HW … #define SRC_ILT_PAGE_SZ … #define SRC_HASH_BITS … #define SRC_CONN_NUM … #define SRC_ILT_SZ … #define SRC_T2_SZ … #define SRC_ILT_LINES … #define MAX_DMAE_C … /* DMA memory not used in fastpath */ struct bnx2x_slowpath { … }; #define bnx2x_sp(bp, var) … #define bnx2x_sp_mapping(bp, var) … /* attn group wiring */ #define MAX_DYNAMIC_ATTN_GRPS … struct attn_route { … }; struct iro { … }; struct hw_context { … }; /* forward */ struct bnx2x_ilt; struct bnx2x_vfdb; enum bnx2x_recovery_state { … }; /* * Event queue (EQ or event ring) MC hsi * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 */ #define NUM_EQ_PAGES … #define EQ_DESC_CNT_PAGE … #define EQ_DESC_MAX_PAGE … #define NUM_EQ_DESC … #define EQ_DESC_MASK … #define MAX_EQ_AVAIL … /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ #define NEXT_EQ_IDX(x) … /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ #define EQ_DESC(x) … #define BNX2X_EQ_INDEX … /* This is a data that will be used to create a link report message. * We will keep the data used for the last link report in order * to prevent reporting the same link parameters twice. */ struct bnx2x_link_report_data { … }; enum { … }; enum { … }; struct bnx2x_fw_stats_req { … }; struct bnx2x_fw_stats_data { … }; /* Public slow path states */ enum sp_rtnl_flag { … }; enum bnx2x_iov_flag { … }; struct bnx2x_prev_path_list { … }; struct bnx2x_sp_objs { … }; struct bnx2x_fp_stats { … }; enum { … }; struct bnx2x_vlan_entry { … }; enum bnx2x_udp_port_type { … }; struct bnx2x { … }; /* Tx queues may be less or equal to Rx queues */ extern int num_queues; #define BNX2X_NUM_QUEUES(bp) … #define BNX2X_NUM_ETH_QUEUES(bp) … #define BNX2X_NUM_NON_CNIC_QUEUES(bp) … #define BNX2X_NUM_RX_QUEUES(bp) … #define is_multi(bp) … #define BNX2X_MAX_QUEUES(bp) … /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ #define RSS_IPV4_CAP_MASK … #define RSS_IPV4_TCP_CAP_MASK … #define RSS_IPV6_CAP_MASK … #define RSS_IPV6_TCP_CAP_MASK … struct bnx2x_func_init_params { … }; #define for_each_cnic_queue(bp, var) … #define for_each_eth_queue(bp, var) … #define for_each_nondefault_eth_queue(bp, var) … #define for_each_queue(bp, var) … /* Skip forwarding FP */ #define for_each_valid_rx_queue(bp, var) … #define for_each_rx_queue_cnic(bp, var) … #define for_each_rx_queue(bp, var) … /* Skip OOO FP */ #define for_each_valid_tx_queue(bp, var) … #define for_each_tx_queue_cnic(bp, var) … #define for_each_tx_queue(bp, var) … #define for_each_nondefault_queue(bp, var) … #define for_each_cos_in_tx_queue(fp, var) … /* skip rx queue * if FCOE l2 support is disabled and this is the fcoe L2 queue */ #define skip_rx_queue(bp, idx) … /* skip tx queue * if FCOE l2 support is disabled and this is the fcoe L2 queue */ #define skip_tx_queue(bp, idx) … #define skip_queue(bp, idx) … /*self test*/ int bnx2x_idle_chk(struct bnx2x *bp); /** * bnx2x_set_mac_one - configure a single MAC address * * @bp: driver handle * @mac: MAC to configure * @obj: MAC object handle * @set: if 'true' add a new MAC, otherwise - delete * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) * * Configures one MAC according to provided parameters or continues the * execution of previously scheduled commands if RAMROD_CONT is set in * ramrod_flags. * * Returns zero if operation has successfully completed, a positive value if the * operation has been successfully scheduled and a negative - if a requested * operations has failed. */ int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac, struct bnx2x_vlan_mac_obj *obj, bool set, int mac_type, unsigned long *ramrod_flags); int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, struct bnx2x_vlan_mac_obj *obj, bool set, unsigned long *ramrod_flags); /** * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object * * @bp: driver handle * @mac_obj: MAC object handle * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) * @wait_for_comp: if 'true' block until completion * * Deletes all MACs of the specific type (e.g. ETH, UC list). * * Returns zero if operation has successfully completed, a positive value if the * operation has been successfully scheduled and a negative - if a requested * operations has failed. */ int bnx2x_del_all_macs(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *mac_obj, int mac_type, bool wait_for_comp); /* Init Function API */ void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, u8 vf_valid, int fw_sb_id, int igu_sb_id); int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); void bnx2x_read_mf_cfg(struct bnx2x *bp); int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); /* dmae */ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, u32 len32); void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, bool with_comp, u8 comp_type); void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, u8 src_type, u8 dst_type); int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, u32 *comp); /* FLR related routines */ u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); u8 bnx2x_is_pcie_pending(struct pci_dev *dev); int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, char *msg, u32 poll_cnt); void bnx2x_calc_fc_adv(struct bnx2x *bp); int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, u32 data_hi, u32 data_lo, int cmd_type); void bnx2x_update_coalesce(struct bnx2x *bp); int bnx2x_get_cur_phy_idx(struct bnx2x *bp); bool bnx2x_port_after_undi(struct bnx2x *bp); static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, int wait) { … } void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf); #define BNX2X_ILT_ZALLOC(x, y, size) … #define BNX2X_ILT_FREE(x, y, size) … #define ILOG2(x) … #define ILT_NUM_PAGE_ENTRIES … /* In 57710/11 we use whole table since we have 8 func * In 57712 we have only 4 func, but use same size per func, then only half of * the table in use */ #define ILT_PER_FUNC … #define FUNC_ILT_BASE(func) … /* * the phys address is shifted right 12 bits and has an added * 1=valid bit added to the 53rd bit * then since this is a wide register(TM) * we split it into two 32 bit writes */ #define ONCHIP_ADDR1(x) … #define ONCHIP_ADDR2(x) … /* load/unload mode */ #define LOAD_NORMAL … #define LOAD_OPEN … #define LOAD_DIAG … #define LOAD_LOOPBACK_EXT … #define UNLOAD_NORMAL … #define UNLOAD_CLOSE … #define UNLOAD_RECOVERY … /* DMAE command defines */ #define DMAE_TIMEOUT … #define DMAE_PCI_ERROR … #define DMAE_NOT_RDY … #define DMAE_PCI_ERR_FLAG … #define DMAE_SRC_PCI … #define DMAE_SRC_GRC … #define DMAE_DST_NONE … #define DMAE_DST_PCI … #define DMAE_DST_GRC … #define DMAE_COMP_PCI … #define DMAE_COMP_GRC … /* E2 and onward - PCI error handling in the completion */ #define DMAE_COMP_REGULAR … #define DMAE_COM_SET_ERR … #define DMAE_CMD_SRC_PCI … #define DMAE_CMD_SRC_GRC … #define DMAE_CMD_DST_PCI … #define DMAE_CMD_DST_GRC … #define DMAE_CMD_C_DST_PCI … #define DMAE_CMD_C_DST_GRC … #define DMAE_CMD_C_ENABLE … #define DMAE_CMD_ENDIANITY_NO_SWAP … #define DMAE_CMD_ENDIANITY_B_SWAP … #define DMAE_CMD_ENDIANITY_DW_SWAP … #define DMAE_CMD_ENDIANITY_B_DW_SWAP … #define DMAE_CMD_PORT_0 … #define DMAE_CMD_PORT_1 … #define DMAE_CMD_SRC_RESET … #define DMAE_CMD_DST_RESET … #define DMAE_CMD_E1HVN_SHIFT … #define DMAE_SRC_PF … #define DMAE_SRC_VF … #define DMAE_DST_PF … #define DMAE_DST_VF … #define DMAE_C_SRC … #define DMAE_C_DST … #define DMAE_LEN32_RD_MAX … #define DMAE_LEN32_WR_MAX(bp) … #define DMAE_COMP_VAL … #define MAX_DMAE_C_PER_PORT … #define INIT_DMAE_C(bp) … #define PMF_DMAE_C(bp) … /* Following is the DMAE channel number allocation for the clients. * MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively. * Driver: 0-3 and 8-11 (for PF dmae operations) * 4 and 12 (for stats requests) */ #define BNX2X_FW_DMAE_C … /* PCIE link and speed */ #define PCICFG_LINK_WIDTH … #define PCICFG_LINK_WIDTH_SHIFT … #define PCICFG_LINK_SPEED … #define PCICFG_LINK_SPEED_SHIFT … #define BNX2X_NUM_TESTS_SF … #define BNX2X_NUM_TESTS_MF … #define BNX2X_NUM_TESTS(bp) … #define BNX2X_PHY_LOOPBACK … #define BNX2X_MAC_LOOPBACK … #define BNX2X_EXT_LOOPBACK … #define BNX2X_PHY_LOOPBACK_FAILED … #define BNX2X_MAC_LOOPBACK_FAILED … #define BNX2X_EXT_LOOPBACK_FAILED … #define BNX2X_LOOPBACK_FAILED … #define STROM_ASSERT_ARRAY_SIZE … /* must be used on a CID before placing it on a HW ring */ #define HW_CID(bp, x) … #define SP_DESC_CNT … #define MAX_SP_DESC_CNT … #define BNX2X_BTR … #define MAX_SPQ_PENDING … /* CMNG constants, as derived from system spec calculations */ /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ #define DEF_MIN_RATE … /* resolution of the rate shaping timer - 400 usec */ #define RS_PERIODIC_TIMEOUT_USEC … /* number of bytes in single QM arbitration cycle - * coefficient for calculating the fairness timer */ #define QM_ARB_BYTES … /* resolution of Min algorithm 1:100 */ #define MIN_RES … /* how many bytes above threshold for the minimal credit of Min algorithm*/ #define MIN_ABOVE_THRESH … /* Fairness algorithm integration time coefficient - * for calculating the actual Tfair */ #define T_FAIR_COEF … /* Memory of fairness algorithm . 2 cycles */ #define FAIR_MEM … #define ATTN_NIG_FOR_FUNC … #define ATTN_SW_TIMER_4_FUNC … #define GPIO_2_FUNC … #define GPIO_3_FUNC … #define GPIO_4_FUNC … #define ATTN_GENERAL_ATTN_1 … #define ATTN_GENERAL_ATTN_2 … #define ATTN_GENERAL_ATTN_3 … #define ATTN_GENERAL_ATTN_4 … #define ATTN_GENERAL_ATTN_5 … #define ATTN_GENERAL_ATTN_6 … #define ATTN_HARD_WIRED_MASK … #define ATTENTION_ID … #define IS_MF_STORAGE_ONLY(bp) … /* stuff added to make the code fit 80Col */ #define BNX2X_PMF_LINK_ASSERT … #define BNX2X_MC_ASSERT_BITS … #define BNX2X_MCP_ASSERT … #define BNX2X_GRC_TIMEOUT … #define BNX2X_GRC_RSV … #define HW_INTERRUPT_ASSERT_SET_0 … #define HW_PRTY_ASSERT_SET_0 … #define HW_INTERRUPT_ASSERT_SET_1 … #define HW_PRTY_ASSERT_SET_1 … #define HW_INTERRUPT_ASSERT_SET_2 … #define HW_PRTY_ASSERT_SET_2 … #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD … #define HW_PRTY_ASSERT_SET_3 … #define HW_PRTY_ASSERT_SET_4 … #define MULTI_MASK … #define DEF_USB_FUNC_OFF … #define DEF_CSB_FUNC_OFF … #define DEF_XSB_FUNC_OFF … #define DEF_TSB_FUNC_OFF … #define DEF_USB_IGU_INDEX_OFF … #define DEF_CSB_IGU_INDEX_OFF … #define DEF_XSB_IGU_INDEX_OFF … #define DEF_TSB_IGU_INDEX_OFF … #define DEF_USB_SEGMENT_OFF … #define DEF_CSB_SEGMENT_OFF … #define DEF_XSB_SEGMENT_OFF … #define DEF_TSB_SEGMENT_OFF … #define BNX2X_SP_DSB_INDEX … #define CAM_IS_INVALID(x) … /* Number of u32 elements in MC hash array */ #define MC_HASH_SIZE … #define MC_HASH_OFFSET(bp, i) … #ifndef PXP2_REG_PXP2_INT_STS #define PXP2_REG_PXP2_INT_STS … #endif #ifndef ETH_MAX_RX_CLIENTS_E2 #define ETH_MAX_RX_CLIENTS_E2 … #endif #define VENDOR_ID_LEN … #define VF_ACQUIRE_THRESH … #define VF_ACQUIRE_MAC_FILTERS … #define VF_ACQUIRE_MC_FILTERS … #define VF_ACQUIRE_VLAN_FILTERS … #define GOOD_ME_REG(me_reg) … int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); /* Congestion management fairness mode */ #define CMNG_FNS_NONE … #define CMNG_FNS_MINMAX … #define HC_SEG_ACCESS_DEF … #define HC_SEG_ACCESS_ATTN … #define HC_SEG_ACCESS_NORM … void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); void bnx2x_notify_link_changed(struct bnx2x *bp); #define BNX2X_MF_SD_PROTOCOL(bp) … #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) … #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) … #define IS_MF_ISCSI_SD(bp) … #define IS_MF_FCOE_SD(bp) … #define IS_MF_ISCSI_SI(bp) … #define IS_MF_ISCSI_ONLY(bp) … #define BNX2X_MF_EXT_PROTOCOL_MASK … #define BNX2X_MF_EXT_PROT(bp) … #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) … #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) … #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) … #define IS_MF_FCOE_AFEX(bp) … #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) … #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) … #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) … /* Determines whether BW configuration arrives in 100Mb units or in * percentages from actual physical link speed. */ #define IS_MF_PERCENT_BW(bp) … #define SET_FLAG(value, mask, flag) … #define GET_FLAG(value, mask) … #define GET_FIELD(value, fname) … enum { … }; #define NUM_MACS … void bnx2x_set_local_cmng(struct bnx2x *bp); void bnx2x_update_mng_version(struct bnx2x *bp); void bnx2x_update_mfw_dump(struct bnx2x *bp); #define MCPR_SCRATCH_BASE(bp) … #define E1H_MAX_MF_SB_COUNT … void bnx2x_init_ptp(struct bnx2x *bp); int bnx2x_configure_ptp_filters(struct bnx2x *bp); void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb); void bnx2x_register_phc(struct bnx2x *bp); #define BNX2X_MAX_PHC_DRIFT … #define BNX2X_PTP_TX_TIMEOUT /* Re-configure all previously configured vlan filters. * Meant for implicit re-load flows. */ int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp); #endif /* bnx2x.h */
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