/* bnx2x_init_ops.h: Qlogic Everest network driver. * Static functions needed during the initialization. * This file is "included" in bnx2x_main.c. * * Copyright (c) 2007-2013 Broadcom Corporation * Copyright (c) 2014 QLogic Corporation All rights reserved * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Maintained by: Ariel Elior <[email protected]> * Written by: Vladislav Zolotarov */ #ifndef BNX2X_INIT_OPS_H #define BNX2X_INIT_OPS_H #ifndef BP_ILT #define BP_ILT … #endif #ifndef BP_FUNC #define BP_FUNC … #endif #ifndef BP_PORT #define BP_PORT … #endif #ifndef BNX2X_ILT_FREE #define BNX2X_ILT_FREE … #endif #ifndef BNX2X_ILT_ZALLOC #define BNX2X_ILT_ZALLOC … #endif #ifndef ILOG2 #define ILOG2 … #endif static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len); static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, u32 addr, u32 len); static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, u32 len) { … } static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, u32 len) { … } static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len, u8 wb) { … } static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len, u8 wb) { … } static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len) { … } static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, u32 len64) { … } /********************************************************* There are different blobs for each PRAM section. In addition, each blob write operation is divided into a few operations in order to decrease the amount of phys. contiguous buffer needed. Thus, when we select a blob the address may be with some offset from the beginning of PRAM section. The same holds for the INT_TABLE sections. **********************************************************/ #define IF_IS_INT_TABLE_ADDR(base, addr) … #define IF_IS_PRAM_ADDR(base, addr) … static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr, const u8 *data) { … } static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, u32 len) { … } static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, u32 val_hi) { … } static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len, u32 blob_off) { … } static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) { … } /**************************************************************************** * PXP Arbiter ****************************************************************************/ /* * This code configures the PCI read/write arbiter * which implements a weighted round robin * between the virtual queues in the chip. * * The values were derived for each PCI max payload and max request size. * since max payload and max request size are only known at run time, * this is done as a separate init stage. */ #define NUM_WR_Q … #define NUM_RD_Q … #define MAX_RD_ORD … #define MAX_WR_ORD … /* configuration for one arbiter queue */ struct arb_line { … }; /* derived configuration for each read queue for each max request size */ static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = …; /* derived configuration for each write queue for each max request size */ static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = …; /* register addresses for read queues */ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = …; /* register addresses for write queues */ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = …; static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order, int w_order) { … } /**************************************************************************** * ILT management ****************************************************************************/ /* * This codes hides the low level HW interaction for ILT management and * configuration. The API consists of a shadow ILT table which is set by the * driver and a set of routines to use it to configure the HW. * */ /* ILT HW init operations */ /* ILT memory management operations */ #define ILT_MEMOP_ALLOC … #define ILT_MEMOP_FREE … /* the phys address is shifted right 12 bits and has an added * 1=valid bit added to the 53rd bit * then since this is a wide register(TM) * we split it into two 32 bit writes */ #define ILT_ADDR1(x) … #define ILT_ADDR2(x) … #define ILT_RANGE(f, l) … static int bnx2x_ilt_line_mem_op(struct bnx2x *bp, struct ilt_line *line, u32 size, u8 memop) { … } static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num, u8 memop) { … } static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, u8 memop) { … } static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop) { … } static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx, dma_addr_t page_mapping) { … } static void bnx2x_ilt_line_init_op(struct bnx2x *bp, struct bnx2x_ilt *ilt, int idx, u8 initop) { … } static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp, struct ilt_client_info *ilt_cli, u32 ilt_start, u8 initop) { … } static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp, struct bnx2x_ilt *ilt, struct ilt_client_info *ilt_cli, u8 initop) { … } static void bnx2x_ilt_client_init_op(struct bnx2x *bp, struct ilt_client_info *ilt_cli, u8 initop) { … } static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp, int cli_num, u8 initop) { … } static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, u8 initop) { … } static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop) { … } static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num, u32 psz_reg, u8 initop) { … } /* * called during init common stage, ilt clients should be initialized * prioir to calling this function */ static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop) { … } /**************************************************************************** * QM initializations ****************************************************************************/ #define QM_QUEUES_PER_FUNC … #define QM_INIT_MIN_CID_COUNT … #define QM_INIT(cid_cnt) … /* called during init port stage */ static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count, u8 initop) { … } static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count, u32 base_reg, u32 reg) { … } /* called during init common stage */ static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count, u8 initop) { … } /**************************************************************************** * SRC initializations ****************************************************************************/ /* called during init func stage */ static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2, dma_addr_t t2_mapping, int src_cid_count) { … } #endif /* BNX2X_INIT_OPS_H */
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