/* Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2014-2016 Broadcom Corporation * Copyright (c) 2016-2018 Broadcom Limited * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. */ #ifndef BNXT_H #define BNXT_H #define DRV_MODULE_NAME … /* DO NOT CHANGE DRV_VER_* defines * FIXME: Delete them */ #define DRV_VER_MAJ … #define DRV_VER_MIN … #define DRV_VER_UPD … #include <linux/ethtool.h> #include <linux/interrupt.h> #include <linux/rhashtable.h> #include <linux/crash_dump.h> #include <linux/auxiliary_bus.h> #include <net/devlink.h> #include <net/dst_metadata.h> #include <net/xdp.h> #include <linux/dim.h> #include <linux/io-64-nonatomic-lo-hi.h> #ifdef CONFIG_TEE_BNXT_FW #include <linux/firmware/broadcom/tee_bnxt_fw.h> #endif extern struct list_head bnxt_block_cb_list; struct page_pool; struct tx_bd { … } __packed; #define TX_OPAQUE_IDX_MASK … #define TX_OPAQUE_BDS_MASK … #define TX_OPAQUE_BDS_SHIFT … #define TX_OPAQUE_RING_MASK … #define TX_OPAQUE_RING_SHIFT … #define SET_TX_OPAQUE(bp, txr, idx, bds) … #define TX_OPAQUE_IDX(opq) … #define TX_OPAQUE_RING(opq) … #define TX_OPAQUE_BDS(opq) … #define TX_OPAQUE_PROD(bp, opq) … struct tx_bd_ext { … }; #define BNXT_TX_PTP_IS_SET(lflags) … struct rx_bd { … }; struct tx_cmp { … }; #define TX_CMP_SQ_CONS_IDX(txcmp) … struct tx_ts_cmp { … }; #define BNXT_GET_TX_TS_48B_NS(tscmp) … #define BNXT_TX_TS_ERR(tscmp) … struct rx_cmp { … }; #define BNXT_PTP_RX_TS_VALID(flags) … #define BNXT_ALL_RX_TS_VALID(flags) … #define RX_CMP_HASH_VALID(rxcmp) … #define RSS_PROFILE_ID_MASK … #define RX_CMP_HASH_TYPE(rxcmp) … #define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) … #define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) … #define RX_CMP_V3_HASH_TYPE(bp, rxcmp) … #define EXT_OP_INNER_4 … #define EXT_OP_OUTER_4 … #define EXT_OP_INNFL_3 … #define EXT_OP_OUTFL_3 … #define RX_CMP_VLAN_VALID(rxcmp) … #define RX_CMP_VLAN_TPID_SEL(rxcmp) … struct rx_cmp_ext { … }; #define RX_CMP_L2_ERRORS … #define RX_CMP_L4_CS_BITS … #define RX_CMP_L4_CS_ERR_BITS … #define RX_CMP_L4_CS_OK(rxcmp1) … #define RX_CMP_ENCAP(rxcmp1) … #define RX_CMP_CFA_CODE(rxcmpl1) … #define RX_CMP_METADATA0_TCI(rxcmp1) … struct rx_agg_cmp { … }; #define TPA_AGG_AGG_ID(rx_agg) … struct rx_tpa_start_cmp { … }; #define TPA_START_HASH_VALID(rx_tpa_start) … #define TPA_START_HASH_TYPE(rx_tpa_start) … #define TPA_START_V3_HASH_TYPE(rx_tpa_start) … #define TPA_START_AGG_ID(rx_tpa_start) … #define TPA_START_AGG_ID_P5(rx_tpa_start) … #define TPA_START_ERROR(rx_tpa_start) … #define TPA_START_VLAN_VALID(rx_tpa_start) … #define TPA_START_VLAN_TPID_SEL(rx_tpa_start) … struct rx_tpa_start_cmp_ext { … }; #define TPA_START_CFA_CODE(rx_tpa_start) … #define TPA_START_IS_IPV6(rx_tpa_start) … #define TPA_START_ERROR_CODE(rx_tpa_start) … #define TPA_START_METADATA0_TCI(rx_tpa_start) … struct rx_tpa_end_cmp { … }; #define TPA_END_AGG_ID(rx_tpa_end) … #define TPA_END_AGG_ID_P5(rx_tpa_end) … #define TPA_END_PAYLOAD_OFF(rx_tpa_end) … #define TPA_END_AGG_BUFS(rx_tpa_end) … #define TPA_END_TPA_SEGS(rx_tpa_end) … #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO … #define TPA_END_GRO(rx_tpa_end) … #define TPA_END_GRO_TS(rx_tpa_end) … struct rx_tpa_end_cmp_ext { … }; #define TPA_END_ERRORS(rx_tpa_end_ext) … #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) … #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) … #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) … #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) … #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) … #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) … #define EVENT_DATA1_RECOVERY_ENABLED(data1) … #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) … #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) … struct nqe_cn { … }; #define BNXT_NQ_HDL_IDX_MASK … #define BNXT_NQ_HDL_TYPE_MASK … #define BNXT_NQ_HDL_TYPE_SHIFT … #define BNXT_NQ_HDL_TYPE_RX … #define BNXT_NQ_HDL_TYPE_TX … #define BNXT_NQ_HDL_IDX(hdl) … #define BNXT_NQ_HDL_TYPE(hdl) … #define BNXT_SET_NQ_HDL(cpr) … #define NQE_CN_TYPE(type) … #define NQE_CN_TOGGLE(type) … #define DB_IDX_MASK … #define DB_IDX_VALID … #define DB_IRQ_DIS … #define DB_KEY_TX … #define DB_KEY_RX … #define DB_KEY_CP … #define DB_KEY_ST … #define DB_KEY_TX_PUSH … #define DB_LONG_TX_PUSH … #define BNXT_MIN_ROCE_CP_RINGS … #define BNXT_MIN_ROCE_STAT_CTXS … /* 64-bit doorbell */ #define DBR_INDEX_MASK … #define DBR_EPOCH_MASK … #define DBR_EPOCH_SFT … #define DBR_TOGGLE_MASK … #define DBR_TOGGLE_SFT … #define DBR_XID_MASK … #define DBR_XID_SFT … #define DBR_PATH_L2 … #define DBR_VALID … #define DBR_TYPE_SQ … #define DBR_TYPE_RQ … #define DBR_TYPE_SRQ … #define DBR_TYPE_SRQ_ARM … #define DBR_TYPE_CQ … #define DBR_TYPE_CQ_ARMSE … #define DBR_TYPE_CQ_ARMALL … #define DBR_TYPE_CQ_ARMENA … #define DBR_TYPE_SRQ_ARMENA … #define DBR_TYPE_CQ_CUTOFF_ACK … #define DBR_TYPE_NQ … #define DBR_TYPE_NQ_ARM … #define DBR_TYPE_NQ_MASK … #define DBR_TYPE_NULL … #define DB_PF_OFFSET_P5 … #define DB_VF_OFFSET_P5 … #define INVALID_HW_RING_ID … /* The hardware supports certain page sizes. Use the supported page sizes * to allocate the rings. */ #if (PAGE_SHIFT < 12) #define BNXT_PAGE_SHIFT … #elif (PAGE_SHIFT <= 13) #define BNXT_PAGE_SHIFT … #elif (PAGE_SHIFT < 16) #define BNXT_PAGE_SHIFT … #else #define BNXT_PAGE_SHIFT … #endif #define BNXT_PAGE_SIZE … /* The RXBD length is 16-bit so we can only support page sizes < 64K */ #if (PAGE_SHIFT > 15) #define BNXT_RX_PAGE_SHIFT … #else #define BNXT_RX_PAGE_SHIFT … #endif #define BNXT_RX_PAGE_SIZE … #define BNXT_MAX_MTU … /* First RX buffer page in XDP multi-buf mode * * +-------------------------------------------------------------------------+ * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info| * | (bp->rx_dma_offset) | | | * +-------------------------------------------------------------------------+ */ #define BNXT_MAX_PAGE_MODE_MTU_SBUF … #define BNXT_MAX_PAGE_MODE_MTU … #define BNXT_MIN_PKT_SIZE … #define BNXT_DEFAULT_RX_RING_SIZE … #define BNXT_DEFAULT_TX_RING_SIZE … #define MAX_TPA … #define MAX_TPA_P5 … #define MAX_TPA_P5_MASK … #define MAX_TPA_SEGS_P5 … #if (BNXT_PAGE_SHIFT == 16) #define MAX_RX_PAGES_AGG_ENA … #define MAX_RX_PAGES … #define MAX_RX_AGG_PAGES … #define MAX_TX_PAGES … #define MAX_CP_PAGES … #else #define MAX_RX_PAGES_AGG_ENA … #define MAX_RX_PAGES … #define MAX_RX_AGG_PAGES … #define MAX_TX_PAGES … #define MAX_CP_PAGES … #endif #define RX_DESC_CNT … #define TX_DESC_CNT … #define CP_DESC_CNT … #define SW_RXBD_RING_SIZE … #define HW_RXBD_RING_SIZE … #define SW_RXBD_AGG_RING_SIZE … #define SW_TXBD_RING_SIZE … #define HW_TXBD_RING_SIZE … #define HW_CMPD_RING_SIZE … #define BNXT_MAX_RX_DESC_CNT … #define BNXT_MAX_RX_DESC_CNT_JUM_ENA … #define BNXT_MAX_RX_JUM_DESC_CNT … #define BNXT_MAX_TX_DESC_CNT … /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra * BD because the first TX BD is always a long BD. */ #define BNXT_MIN_TX_DESC_CNT … #define RX_RING(bp, x) … #define RX_AGG_RING(bp, x) … #define RX_IDX(x) … #define TX_RING(bp, x) … #define TX_IDX(x) … #define CP_RING(x) … #define CP_IDX(x) … #define TX_CMP_VALID(txcmp, raw_cons) … #define RX_CMP_VALID(rxcmp1, raw_cons) … #define RX_AGG_CMP_VALID(agg, raw_cons) … #define NQ_CMP_VALID(nqcmp, raw_cons) … #define TX_CMP_TYPE(txcmp) … #define RX_CMP_TYPE(rxcmp) … #define RING_RX(bp, idx) … #define NEXT_RX(idx) … #define RING_RX_AGG(bp, idx) … #define NEXT_RX_AGG(idx) … #define RING_TX(bp, idx) … #define NEXT_TX(idx) … #define ADV_RAW_CMP(idx, n) … #define NEXT_RAW_CMP(idx) … #define RING_CMP(idx) … #define NEXT_CMP(idx) … #define DFLT_HWRM_CMD_TIMEOUT … #define BNXT_RX_EVENT … #define BNXT_AGG_EVENT … #define BNXT_TX_EVENT … #define BNXT_REDIRECT_EVENT … #define BNXT_TX_CMP_EVENT … struct bnxt_sw_tx_bd { … }; struct bnxt_sw_rx_bd { … }; struct bnxt_sw_rx_agg_bd { … }; struct bnxt_ring_mem_info { … }; struct bnxt_ring_struct { … }; struct tx_push_bd { … }; struct tx_push_buffer { … }; struct bnxt_db_info { … }; #define DB_EPOCH(db, idx) … #define DB_TOGGLE(tgl) … #define DB_RING_IDX(db, idx) … struct bnxt_tx_ring_info { … }; #define BNXT_LEGACY_COAL_CMPL_PARAMS … #define BNXT_COAL_CMPL_ENABLES … #define BNXT_COAL_CMPL_MIN_TMR_ENABLE … #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE … struct bnxt_coal_cap { … }; struct bnxt_coal { … }; struct bnxt_tpa_info { … }; #define BNXT_AGG_IDX_BMAP_SIZE … struct bnxt_tpa_idx_map { … }; struct bnxt_rx_ring_info { … }; struct bnxt_rx_sw_stats { … }; struct bnxt_tx_sw_stats { … }; struct bnxt_cmn_sw_stats { … }; struct bnxt_sw_stats { … }; struct bnxt_total_ring_err_stats { … }; struct bnxt_stats_mem { … }; struct bnxt_cp_ring_info { … }; #define BNXT_MAX_QUEUE … #define BNXT_MAX_TXR_PER_NAPI … #define bnxt_for_each_napi_tx(iter, bnapi, txr) … struct bnxt_napi { … }; /* "TxRx", 2 hypens, plus maximum integer */ #define BNXT_IRQ_NAME_EXTRA … struct bnxt_irq { … }; #define HWRM_RING_ALLOC_TX … #define HWRM_RING_ALLOC_RX … #define HWRM_RING_ALLOC_AGG … #define HWRM_RING_ALLOC_CMPL … #define HWRM_RING_ALLOC_NQ … #define INVALID_STATS_CTX_ID … struct bnxt_ring_grp_info { … }; #define BNXT_VNIC_DEFAULT … #define BNXT_VNIC_NTUPLE … struct bnxt_vnic_info { … }; struct bnxt_rss_ctx { … }; #define BNXT_MAX_ETH_RSS_CTX … #define BNXT_VNIC_ID_INVALID … struct bnxt_hw_rings { … }; struct bnxt_hw_resc { … }; #if defined(CONFIG_BNXT_SRIOV) struct bnxt_vf_info { … }; #endif struct bnxt_pf_info { … }; struct bnxt_filter_base { … }; struct bnxt_flow_masks { … }; extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE; extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL; extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL; struct bnxt_ntuple_filter { … }; struct bnxt_l2_key { … }; struct bnxt_ipv4_tuple { … }; struct bnxt_ipv6_tuple { … }; #define BNXT_L2_KEY_SIZE … struct bnxt_l2_filter { … }; /* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes. The * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h. * The last valid byte in the compat version is different. */ struct hwrm_port_phy_qcfg_output_compat { … }; struct bnxt_link_info { … }; #define BNXT_FEC_RS544_ON … #define BNXT_FEC_RS544_OFF … #define BNXT_FEC_RS272_ON … #define BNXT_FEC_RS272_OFF … #define BNXT_PAM4_SUPPORTED(link_info) … #define BNXT_FEC_RS_ON(link_info) … #define BNXT_FEC_LLRS_ON … #define BNXT_FEC_RS_OFF(link_info) … #define BNXT_FEC_BASE_R_ON(link_info) … #define BNXT_FEC_ALL_OFF(link_info) … struct bnxt_queue_info { … }; #define BNXT_MAX_LED … struct bnxt_led_info { … }; #define BNXT_MAX_TEST … struct bnxt_test_info { … }; #define CHIMP_REG_VIEW_ADDR … #define BNXT_GRCPF_REG_CHIMP_COMM … #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER … #define BNXT_GRCPF_REG_WINDOW_BASE_OUT … #define BNXT_GRC_REG_STATUS_P5 … #define BNXT_GRCPF_REG_KONG_COMM … #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER … #define BNXT_GRC_REG_CHIP_NUM … #define BNXT_GRC_REG_BASE … #define BNXT_TS_REG_TIMESYNC_TS0_LOWER … #define BNXT_TS_REG_TIMESYNC_TS0_UPPER … #define BNXT_GRC_BASE_MASK … #define BNXT_GRC_OFFSET_MASK … struct bnxt_tc_flow_stats { … }; #ifdef CONFIG_BNXT_FLOWER_OFFLOAD struct bnxt_flower_indr_block_cb_priv { … }; #endif struct bnxt_tc_info { … }; struct bnxt_vf_rep_stats { … }; struct bnxt_vf_rep { … }; #define PTU_PTE_VALID … #define PTU_PTE_LAST … #define PTU_PTE_NEXT_TO_LAST … #define MAX_CTX_PAGES … #define MAX_CTX_TOTAL_PAGES … struct bnxt_ctx_pg_info { … }; #define BNXT_MAX_TQM_SP_RINGS … #define BNXT_MAX_TQM_FP_RINGS … #define BNXT_MAX_TQM_RINGS … #define BNXT_BACKING_STORE_CFG_LEGACY_LEN … #define BNXT_SET_CTX_PAGE_ATTR(attr) … struct bnxt_ctx_mem_type { … }; #define BNXT_CTX_MRAV_AV_SPLIT_ENTRY … #define BNXT_CTX_QP … #define BNXT_CTX_SRQ … #define BNXT_CTX_CQ … #define BNXT_CTX_VNIC … #define BNXT_CTX_STAT … #define BNXT_CTX_STQM … #define BNXT_CTX_FTQM … #define BNXT_CTX_MRAV … #define BNXT_CTX_TIM … #define BNXT_CTX_TKC … #define BNXT_CTX_RKC … #define BNXT_CTX_MTQM … #define BNXT_CTX_SQDBS … #define BNXT_CTX_RQDBS … #define BNXT_CTX_SRQDBS … #define BNXT_CTX_CQDBS … #define BNXT_CTX_QTKC … #define BNXT_CTX_QRKC … #define BNXT_CTX_TBLSC … #define BNXT_CTX_XPAR … #define BNXT_CTX_MAX … #define BNXT_CTX_L2_MAX … #define BNXT_CTX_V2_MAX … #define BNXT_CTX_INV … struct bnxt_ctx_mem_info { … }; enum bnxt_health_severity { … }; enum bnxt_health_remedy { … }; struct bnxt_fw_health { … }; #define BNXT_FW_HEALTH_REG_TYPE_MASK … #define BNXT_FW_HEALTH_REG_TYPE_CFG … #define BNXT_FW_HEALTH_REG_TYPE_GRC … #define BNXT_FW_HEALTH_REG_TYPE_BAR0 … #define BNXT_FW_HEALTH_REG_TYPE_BAR1 … #define BNXT_FW_HEALTH_REG_TYPE(reg) … #define BNXT_FW_HEALTH_REG_OFF(reg) … #define BNXT_FW_HEALTH_WIN_BASE … #define BNXT_FW_HEALTH_WIN_MAP_OFF … #define BNXT_FW_HEALTH_WIN_OFF(reg) … #define BNXT_FW_STATUS_HEALTH_MSK … #define BNXT_FW_STATUS_HEALTHY … #define BNXT_FW_STATUS_SHUTDOWN … #define BNXT_FW_STATUS_RECOVERING … #define BNXT_FW_IS_HEALTHY(sts) … #define BNXT_FW_IS_BOOTING(sts) … #define BNXT_FW_IS_ERR(sts) … #define BNXT_FW_IS_RECOVERING(sts) … #define BNXT_FW_RETRY … #define BNXT_FW_IF_RETRY … #define BNXT_FW_SLOT_RESET_RETRY … struct bnxt_aux_priv { … }; enum board_idx { … }; struct bnxt { … }; #define BNXT_NUM_RX_RING_STATS … #define BNXT_NUM_TX_RING_STATS … #define BNXT_NUM_TPA_RING_STATS … #define BNXT_NUM_TPA_RING_STATS_P5 … #define BNXT_NUM_TPA_RING_STATS_P7 … #define BNXT_RING_STATS_SIZE_P5 … #define BNXT_RING_STATS_SIZE_P7 … #define BNXT_GET_RING_STATS64(sw, counter) … #define BNXT_GET_RX_PORT_STATS64(sw, counter) … #define BNXT_GET_TX_PORT_STATS64(sw, counter) … #define BNXT_PORT_STATS_SIZE … #define BNXT_TX_PORT_STATS_BYTE_OFFSET … #define BNXT_RX_STATS_OFFSET(counter) … #define BNXT_TX_STATS_OFFSET(counter) … #define BNXT_RX_STATS_EXT_OFFSET(counter) … #define BNXT_RX_STATS_EXT_NUM_LEGACY … #define BNXT_TX_STATS_EXT_OFFSET(counter) … #define BNXT_HW_FEATURE_VLAN_ALL_RX … #define BNXT_HW_FEATURE_VLAN_ALL_TX … #define I2C_DEV_ADDR_A0 … #define I2C_DEV_ADDR_A2 … #define SFF_DIAG_SUPPORT_OFFSET … #define SFF_MODULE_ID_SFP … #define SFF_MODULE_ID_QSFP … #define SFF_MODULE_ID_QSFP_PLUS … #define SFF_MODULE_ID_QSFP28 … #define BNXT_MAX_PHY_I2C_RESP_SIZE … static inline u32 bnxt_tx_avail(struct bnxt *bp, const struct bnxt_tx_ring_info *txr) { … } static inline void bnxt_writeq(struct bnxt *bp, u64 val, volatile void __iomem *addr) { … } static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val, volatile void __iomem *addr) { … } /* For TX and RX ring doorbells with no ordering guarantee*/ static inline void bnxt_db_write_relaxed(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { … } /* For TX and RX ring doorbells */ static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, u32 idx) { … } /* Must hold rtnl_lock */ static inline bool bnxt_sriov_cfg(struct bnxt *bp) { … } extern const u16 bnxt_lhint_arr[]; int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 prod, gfp_t gfp); void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx); void bnxt_set_tpa_flags(struct bnxt *bp); void bnxt_set_ring_params(struct bnxt *); int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); void bnxt_insert_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr); void bnxt_del_one_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr); int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size, bool async_only); int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp); void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr); struct bnxt_l2_filter *bnxt_alloc_new_l2_filter(struct bnxt *bp, struct bnxt_l2_key *key, u16 flags); int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr); int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr); int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, struct bnxt_ntuple_filter *fltr); int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, struct bnxt_ntuple_filter *fltr); int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, struct bnxt_vnic_info *vnic, u32 tpa_flags); void bnxt_fill_ipv6_mask(__be32 mask[4]); void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp, struct ethtool_rxfh_context *rss_ctx); int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings); int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic); int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic, unsigned int start_rx_ring_idx, unsigned int nr_rings); int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); int bnxt_nq_rings_in_use(struct bnxt *bp); int bnxt_hwrm_set_coal(struct bnxt *); void bnxt_free_ctx_mem(struct bnxt *bp); int bnxt_num_tx_to_cp(struct bnxt *bp, int tx); unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp); unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp); int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init); void bnxt_tx_disable(struct bnxt *bp); void bnxt_tx_enable(struct bnxt *bp); void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr, u16 curr); void bnxt_report_link(struct bnxt *bp); int bnxt_update_link(struct bnxt *bp, bool chng_link_state); int bnxt_hwrm_set_pause(struct bnxt *); int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset); int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); int bnxt_hwrm_func_qcaps(struct bnxt *bp); int bnxt_hwrm_fw_set_time(struct bnxt *); int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic, u8 valid); int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic); void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx, bool all); int bnxt_open_nic(struct bnxt *, bool, bool); int bnxt_half_open_nic(struct bnxt *bp); void bnxt_half_close_nic(struct bnxt *bp); void bnxt_reenable_sriov(struct bnxt *bp); void bnxt_close_nic(struct bnxt *, bool, bool); void bnxt_get_ring_err_stats(struct bnxt *bp, struct bnxt_total_ring_err_stats *stats); bool bnxt_rfs_capable(struct bnxt *bp, bool new_rss_ctx); int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words, u32 *reg_buf); void bnxt_fw_exception(struct bnxt *bp); void bnxt_fw_reset(struct bnxt *bp); int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, int tx_xdp); int bnxt_fw_init_one(struct bnxt *bp); bool bnxt_hwrm_reset_permitted(struct bnxt *bp); int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp, struct bnxt_ntuple_filter *fltr, u32 idx); u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys, const struct sk_buff *skb); int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr, u32 idx); void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr); int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); int bnxt_restore_pf_fw_resources(struct bnxt *bp); int bnxt_get_port_parent_id(struct net_device *dev, struct netdev_phys_item_id *ppid); void bnxt_dim_work(struct work_struct *work); int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); void bnxt_print_device_info(struct bnxt *bp); #endif
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