/* SPDX-License-Identifier: GPL-2.0-only */ /* * Broadcom BCM7xxx System Port Ethernet MAC driver * * Copyright (C) 2014 Broadcom Corporation */ #ifndef __BCM_SYSPORT_H #define __BCM_SYSPORT_H #include <linux/bitmap.h> #include <linux/ethtool.h> #include <linux/if_vlan.h> #include <linux/dim.h> #include "unimac.h" /* Receive/transmit descriptor format */ #define DESC_ADDR_HI_STATUS_LEN … #define DESC_ADDR_HI_SHIFT … #define DESC_ADDR_HI_MASK … #define DESC_STATUS_SHIFT … #define DESC_STATUS_MASK … #define DESC_LEN_SHIFT … #define DESC_LEN_MASK … #define DESC_ADDR_LO … /* HW supports 40-bit addressing hence the */ #define DESC_SIZE … /* Default RX buffer allocation size */ #define RX_BUF_LENGTH … /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. * 1536 is multiple of 256 bytes */ #define ENET_BRCM_TAG_LEN … #define ENET_PAD … #define UMAC_MAX_MTU_SIZE … /* Transmit status block */ struct bcm_tsb { … }; /* Receive status block uses the same * definitions as the DMA descriptor */ struct bcm_rsb { … }; /* Common Receive/Transmit status bits */ #define DESC_L4_CSUM … #define DESC_SOP … #define DESC_EOP … /* Receive Status bits */ #define RX_STATUS_UCAST … #define RX_STATUS_BCAST … #define RX_STATUS_MCAST … #define RX_STATUS_L2_MCAST … #define RX_STATUS_ERR … #define RX_STATUS_OVFLOW … #define RX_STATUS_PARSE_FAIL … /* Transmit Status bits */ #define TX_STATUS_VLAN_NO_ACT … #define TX_STATUS_VLAN_PCP_TSB … #define TX_STATUS_VLAN_QUEUE … #define TX_STATUS_VLAN_VID_TSB … #define TX_STATUS_OWR_CRC … #define TX_STATUS_APP_CRC … #define TX_STATUS_BRCM_TAG_NO_ACT … #define TX_STATUS_BRCM_TAG_ZERO … #define TX_STATUS_BRCM_TAG_ONE_QUEUE … #define TX_STATUS_BRCM_TAG_ONE_TSB … #define TX_STATUS_SKIP_BYTES … /* Specific register definitions */ #define SYS_PORT_TOPCTRL_OFFSET … #define REV_CNTL … #define REV_MASK … #define RX_FLUSH_CNTL … #define RX_FLUSH … #define TX_FLUSH_CNTL … #define TX_FLUSH … #define MISC_CNTL … #define SYS_CLK_SEL … #define TDMA_EOP_SEL … /* Level-2 Interrupt controller offsets and defines */ #define SYS_PORT_INTRL2_0_OFFSET … #define SYS_PORT_INTRL2_1_OFFSET … #define INTRL2_CPU_STATUS … #define INTRL2_CPU_SET … #define INTRL2_CPU_CLEAR … #define INTRL2_CPU_MASK_STATUS … #define INTRL2_CPU_MASK_SET … #define INTRL2_CPU_MASK_CLEAR … /* Level-2 instance 0 interrupt bits */ #define INTRL2_0_GISB_ERR … #define INTRL2_0_RBUF_OVFLOW … #define INTRL2_0_TBUF_UNDFLOW … #define INTRL2_0_MPD … #define INTRL2_0_BRCM_MATCH_TAG … #define INTRL2_0_RDMA_MBDONE … #define INTRL2_0_OVER_MAX_THRESH … #define INTRL2_0_BELOW_HYST_THRESH … #define INTRL2_0_FREE_LIST_EMPTY … #define INTRL2_0_TX_RING_FULL … #define INTRL2_0_DESC_ALLOC_ERR … #define INTRL2_0_UNEXP_PKTSIZE_ACK … /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ #define INTRL2_0_TDMA_MBDONE_SHIFT … #define INTRL2_0_TDMA_MBDONE_MASK … /* RXCHK offset and defines */ #define SYS_PORT_RXCHK_OFFSET … #define RXCHK_CONTROL … #define RXCHK_EN … #define RXCHK_SKIP_FCS … #define RXCHK_BAD_CSUM_DIS … #define RXCHK_BRCM_TAG_EN … #define RXCHK_BRCM_TAG_MATCH_SHIFT … #define RXCHK_BRCM_TAG_MATCH_MASK … #define RXCHK_PARSE_TNL … #define RXCHK_VIOL_EN … #define RXCHK_VIOL_DIS … #define RXCHK_INCOM_PKT … #define RXCHK_V6_DUPEXT_EN … #define RXCHK_V6_DUPEXT_DIS … #define RXCHK_ETHERTYPE_DIS … #define RXCHK_L2_HDR_DIS … #define RXCHK_L3_HDR_DIS … #define RXCHK_MAC_RX_ERR_DIS … #define RXCHK_PARSE_AUTH … #define RXCHK_BRCM_TAG0 … #define RXCHK_BRCM_TAG(i) … #define RXCHK_BRCM_TAG0_MASK … #define RXCHK_BRCM_TAG_MASK(i) … #define RXCHK_BRCM_TAG_MATCH_STATUS … #define RXCHK_ETHERTYPE … #define RXCHK_BAD_CSUM_CNTR … #define RXCHK_OTHER_DISC_CNTR … #define RXCHK_BRCM_TAG_MAX … #define RXCHK_BRCM_TAG_CID_SHIFT … #define RXCHK_BRCM_TAG_CID_MASK … /* TXCHCK offsets and defines */ #define SYS_PORT_TXCHK_OFFSET … #define TXCHK_PKT_RDY_THRESH … /* Receive buffer offset and defines */ #define SYS_PORT_RBUF_OFFSET … #define RBUF_CONTROL … #define RBUF_RSB_EN … #define RBUF_4B_ALGN … #define RBUF_BRCM_TAG_STRIP … #define RBUF_BAD_PKT_DISC … #define RBUF_RESUME_THRESH_SHIFT … #define RBUF_RESUME_THRESH_MASK … #define RBUF_OK_TO_SEND_SHIFT … #define RBUF_OK_TO_SEND_MASK … #define RBUF_CRC_REPLACE … #define RBUF_OK_TO_SEND_MODE … /* SYSTEMPORT Lite uses two bits here */ #define RBUF_RSB_SWAP0 … #define RBUF_RSB_SWAP1 … #define RBUF_ACPI_EN … #define RBUF_ACPI_EN_LITE … #define RBUF_PKT_RDY_THRESH … #define RBUF_STATUS … #define RBUF_WOL_MODE … #define RBUF_MPD … #define RBUF_ACPI … #define RBUF_OVFL_DISC_CNTR … #define RBUF_ERR_PKT_CNTR … /* Transmit buffer offset and defines */ #define SYS_PORT_TBUF_OFFSET … #define TBUF_CONTROL … #define TBUF_BP_EN … #define TBUF_MAX_PKT_THRESH_SHIFT … #define TBUF_MAX_PKT_THRESH_MASK … #define TBUF_FULL_THRESH_SHIFT … #define TBUF_FULL_THRESH_MASK … /* UniMAC offset and defines */ #define SYS_PORT_UMAC_OFFSET … #define UMAC_MIB_START … /* There is a 0xC gap between the end of RX and beginning of TX stats and then * between the end of TX stats and the beginning of the RX RUNT */ #define UMAC_MIB_STAT_OFFSET … #define UMAC_MIB_CTRL … #define MIB_RX_CNT_RST … #define MIB_RUNT_CNT_RST … #define MIB_TX_CNT_RST … /* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ #define UMAC_MPD_CTRL … #define MPD_EN … #define MSEQ_LEN_SHIFT … #define MSEQ_LEN_MASK … #define PSW_EN … #define UMAC_PSW_MS … #define UMAC_PSW_LS … #define UMAC_MDF_CTRL … #define UMAC_MDF_ADDR … /* Only valid on SYSTEMPORT Lite */ #define SYS_PORT_GIB_OFFSET … #define GIB_CONTROL … #define GIB_TX_EN … #define GIB_RX_EN … #define GIB_TX_FLUSH … #define GIB_RX_FLUSH … #define GIB_GTX_CLK_SEL_SHIFT … #define GIB_GTX_CLK_EXT_CLK … #define GIB_GTX_CLK_125MHZ … #define GIB_GTX_CLK_250MHZ … #define GIB_FCS_STRIP_SHIFT … #define GIB_FCS_STRIP … #define GIB_LCL_LOOP_EN … #define GIB_LCL_LOOP_TXEN … #define GIB_RMT_LOOP_EN … #define GIB_RMT_LOOP_RXEN … #define GIB_RX_PAUSE_EN … #define GIB_PREAMBLE_LEN_SHIFT … #define GIB_PREAMBLE_LEN_MASK … #define GIB_IPG_LEN_SHIFT … #define GIB_IPG_LEN_MASK … #define GIB_PAD_EXTENSION_SHIFT … #define GIB_PAD_EXTENSION_MASK … #define GIB_MAC1 … #define GIB_MAC0 … /* Receive DMA offset and defines */ #define SYS_PORT_RDMA_OFFSET … #define RDMA_CONTROL … #define RDMA_EN … #define RDMA_RING_CFG … #define RDMA_DISC_EN … #define RDMA_BUF_DATA_OFFSET_SHIFT … #define RDMA_BUF_DATA_OFFSET_MASK … #define RDMA_STATUS … #define RDMA_DISABLED … #define RDMA_DESC_RAM_INIT_BUSY … #define RDMA_BP_STATUS … #define RDMA_SCB_BURST_SIZE … #define RDMA_RING_BUF_SIZE … #define RDMA_RING_SIZE_SHIFT … #define RDMA_WRITE_PTR_HI … #define RDMA_WRITE_PTR_LO … #define RDMA_OVFL_DISC_CNTR … #define RDMA_PROD_INDEX … #define RDMA_PROD_INDEX_MASK … #define RDMA_CONS_INDEX … #define RDMA_CONS_INDEX_MASK … #define RDMA_START_ADDR_HI … #define RDMA_START_ADDR_LO … #define RDMA_END_ADDR_HI … #define RDMA_END_ADDR_LO … #define RDMA_MBDONE_INTR … #define RDMA_INTR_THRESH_MASK … #define RDMA_TIMEOUT_SHIFT … #define RDMA_TIMEOUT_MASK … #define RDMA_XON_XOFF_THRESH … #define RDMA_XON_XOFF_THRESH_MASK … #define RDMA_XOFF_THRESH_SHIFT … #define RDMA_READ_PTR_HI … #define RDMA_READ_PTR_LO … #define RDMA_OVERRIDE … #define RDMA_LE_MODE … #define RDMA_REG_MODE … #define RDMA_TEST … #define RDMA_TP_OUT_SEL … #define RDMA_MEM_SEL … #define RDMA_DEBUG … /* Transmit DMA offset and defines */ #define TDMA_NUM_RINGS … #define TDMA_PORT_SIZE … #define SYS_PORT_TDMA_OFFSET … #define TDMA_WRITE_PORT_OFFSET … #define TDMA_WRITE_PORT_HI(i) … #define TDMA_WRITE_PORT_LO(i) … #define TDMA_READ_PORT_OFFSET … #define TDMA_READ_PORT_HI(i) … #define TDMA_READ_PORT_LO(i) … #define TDMA_READ_PORT_CMD_OFFSET … #define TDMA_READ_PORT_CMD(i) … #define TDMA_DESC_RING_00_BASE … /* Register offsets and defines relatives to a specific ring number */ #define RING_HEAD_TAIL_PTR … #define RING_HEAD_MASK … #define RING_TAIL_SHIFT … #define RING_TAIL_MASK … #define RING_FLUSH … #define RING_EN … #define RING_COUNT … #define RING_COUNT_MASK … #define RING_BUFF_DONE_SHIFT … #define RING_BUFF_DONE_MASK … #define RING_MAX_HYST … #define RING_MAX_THRESH_MASK … #define RING_HYST_THRESH_SHIFT … #define RING_HYST_THRESH_MASK … #define RING_INTR_CONTROL … #define RING_INTR_THRESH_MASK … #define RING_EMPTY_INTR_EN … #define RING_TIMEOUT_SHIFT … #define RING_TIMEOUT_MASK … #define RING_PROD_CONS_INDEX … #define RING_PROD_INDEX_MASK … #define RING_CONS_INDEX_SHIFT … #define RING_CONS_INDEX_MASK … #define RING_MAPPING … #define RING_QID_MASK … #define RING_PORT_ID_SHIFT … #define RING_PORT_ID_MASK … #define RING_IGNORE_STATUS … #define RING_FAILOVER_EN … #define RING_CREDIT_SHIFT … #define RING_CREDIT_MASK … #define RING_PCP_DEI_VID … #define RING_VID_MASK … #define RING_DEI … #define RING_PCP_SHIFT … #define RING_PCP_MASK … #define RING_PKT_SIZE_ADJ_SHIFT … #define RING_PKT_SIZE_ADJ_MASK … #define TDMA_DESC_RING_SIZE … /* Defininition for a given TX ring base address */ #define TDMA_DESC_RING_BASE(i) … /* Ring indexed register addreses */ #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) … #define TDMA_DESC_RING_COUNT(i) … #define TDMA_DESC_RING_MAX_HYST(i) … #define TDMA_DESC_RING_INTR_CONTROL(i) … #define TDMA_DESC_RING_PROD_CONS_INDEX(i) … #define TDMA_DESC_RING_MAPPING(i) … #define TDMA_DESC_RING_PCP_DEI_VID(i) … #define TDMA_CONTROL … #define TDMA_EN … #define TSB_EN … /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we * keep the SYSTEMPORT layout here and adjust with tdma_control_bit() */ #define TSB_SWAP0 … #define TSB_SWAP1 … #define ACB_ALGO … #define BUF_DATA_OFFSET_SHIFT … #define BUF_DATA_OFFSET_MASK … #define VLAN_EN … #define SW_BRCM_TAG … #define WNC_KPT_SIZE_UPDATE … #define SYNC_PKT_SIZE … #define ACH_TXDONE_DELAY_SHIFT … #define ACH_TXDONE_DELAY_MASK … #define TDMA_STATUS … #define TDMA_DISABLED … #define TDMA_LL_RAM_INIT_BUSY … #define TDMA_SCB_BURST_SIZE … #define TDMA_OVER_MAX_THRESH_STATUS … #define TDMA_OVER_HYST_THRESH_STATUS … #define TDMA_TPID … #define TDMA_FREE_LIST_HEAD_TAIL_PTR … #define TDMA_FREE_HEAD_MASK … #define TDMA_FREE_TAIL_SHIFT … #define TDMA_FREE_TAIL_MASK … #define TDMA_FREE_LIST_COUNT … #define TDMA_FREE_LIST_COUNT_MASK … #define TDMA_TIER2_ARB_CTRL … #define TDMA_ARB_MODE_RR … #define TDMA_ARB_MODE_WEIGHT_RR … #define TDMA_ARB_MODE_STRICT … #define TDMA_ARB_MODE_DEFICIT_RR … #define TDMA_CREDIT_SHIFT … #define TDMA_CREDIT_MASK … #define TDMA_TIER1_ARB_0_CTRL … #define TDMA_ARB_EN … #define TDMA_TIER1_ARB_0_QUEUE_EN … #define TDMA_TIER1_ARB_1_CTRL … #define TDMA_TIER1_ARB_1_QUEUE_EN … #define TDMA_TIER1_ARB_2_CTRL … #define TDMA_TIER1_ARB_2_QUEUE_EN … #define TDMA_TIER1_ARB_3_CTRL … #define TDMA_TIER1_ARB_3_QUEUE_EN … #define TDMA_SCB_ENDIAN_OVERRIDE … #define TDMA_LE_MODE … #define TDMA_REG_MODE … #define TDMA_TEST … #define TDMA_TP_OUT_SEL … #define TDMA_MEM_TM … #define TDMA_DEBUG … /* Number of Receive hardware descriptor words */ #define SP_NUM_HW_RX_DESC_WORDS … #define SP_LT_NUM_HW_RX_DESC_WORDS … /* Internal linked-list RAM size */ #define SP_NUM_TX_DESC … #define SP_LT_NUM_TX_DESC … #define WORDS_PER_DESC … /* Rx/Tx common counter group.*/ struct bcm_sysport_pkt_counters { … }; /* RSV, Receive Status Vector */ struct bcm_sysport_rx_counters { … }; /* TSV, Transmit Status Vector */ struct bcm_sysport_tx_counters { … }; struct bcm_sysport_mib { … }; /* HW maintains a large list of counters */ enum bcm_sysport_stat_type { … }; /* Macros to help define ethtool statistics */ #define STAT_NETDEV(m) … #define STAT_NETDEV64(m) … #define STAT_MIB(str, m, _type) … #define STAT_MIB_RX(str, m) … #define STAT_MIB_TX(str, m) … #define STAT_RUNT(str, m) … #define STAT_MIB_SOFT(str, m) … #define STAT_RXCHK(str, m, ofs) … #define STAT_RBUF(str, m, ofs) … #define STAT_RDMA(str, m, ofs) … /* TX bytes and packets */ #define NUM_SYSPORT_TXQ_STAT … struct bcm_sysport_stats { … }; struct bcm_sysport_stats64 { … }; /* Software house keeping helper structure */ struct bcm_sysport_cb { … }; enum bcm_sysport_type { … }; struct bcm_sysport_hw_params { … }; struct bcm_sysport_net_dim { … }; /* Software view of the TX ring */ struct bcm_sysport_tx_ring { … }; /* Driver private structure */ struct bcm_sysport_priv { … }; #endif /* __BCM_SYSPORT_H */
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