/* SPDX-License-Identifier: GPL-2.0-only */ /* * Linux network driver for QLogic BR-series Converged Network Adapter. */ /* * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. * Copyright (c) 2014-2015 QLogic Corporation * All rights reserved * www.qlogic.com */ /* File for interrupt macros and functions */ #ifndef __BNA_HW_DEFS_H__ #define __BNA_HW_DEFS_H__ #include "bfi_reg.h" /* SW imposed limits */ #define BFI_ENET_DEF_TXQ … #define BFI_ENET_DEF_RXP … #define BFI_ENET_DEF_UCAM … #define BFI_ENET_DEF_RITSZ … #define BFI_ENET_MAX_MCAM … #define BFI_INVALID_RID … #define BFI_IBIDX_SIZE … #define BFI_VLAN_WORD_SHIFT … #define BFI_VLAN_WORD_MASK … #define BFI_VLAN_BLOCK_SHIFT … #define BFI_VLAN_BMASK_ALL … #define BFI_COALESCING_TIMER_UNIT … #define BFI_MAX_COALESCING_TIMEO … #define BFI_MAX_INTERPKT_COUNT … #define BFI_MAX_INTERPKT_TIMEO … #define BFI_TX_COALESCING_TIMEO … #define BFI_TX_INTERPKT_COUNT … #define BFI_TX_INTERPKT_TIMEO … #define BFI_RX_COALESCING_TIMEO … #define BFI_RX_INTERPKT_COUNT … #define BFI_RX_INTERPKT_TIMEO … #define BFI_TXQ_WI_SIZE … #define BFI_RXQ_WI_SIZE … #define BFI_CQ_WI_SIZE … #define BFI_TX_MAX_WRR_QUOTA … #define BFI_TX_MAX_VECTORS_PER_WI … #define BFI_TX_MAX_VECTORS_PER_PKT … #define BFI_TX_MAX_DATA_PER_VECTOR … #define BFI_TX_MAX_DATA_PER_PKT … /* Small Q buffer size */ #define BFI_SMALL_RXBUF_SIZE … #define BFI_TX_MAX_PRIO … #define BFI_TX_PRIO_MAP_ALL … /* * * Register definitions and macros * */ #define BNA_PCI_REG_CT_ADDRSZ … #define ct_reg_addr_init(_bna, _pcidev) … #define ct_bit_defn_init(_bna, _pcidev) … #define ct2_reg_addr_init(_bna, _pcidev) … #define ct2_bit_defn_init(_bna, _pcidev) … #define bna_reg_addr_init(_bna, _pcidev) … #define bna_port_id_get(_bna) … /* Interrupt related bits, flags and macros */ #define IB_STATUS_BITS … #define BNA_IS_MBOX_INTR(_bna, _intr_status) … #define BNA_IS_HALT_INTR(_bna, _intr_status) … #define BNA_IS_ERR_INTR(_bna, _intr_status) … #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status) … #define BNA_IS_INTX_DATA_INTR(_intr_status) … #define bna_halt_clear(_bna) … #define bna_intx_disable(_bna, _cur_mask) … #define bna_intx_enable(bna, new_mask) … #define bna_mbox_intr_disable(bna) … #define bna_mbox_intr_enable(bna) … #define bna_intr_status_get(_bna, _status) … /* * MAX ACK EVENTS : No. of acks that can be accumulated in driver, * before acking to h/w. The no. of bits is 16 in the doorbell register, * however we keep this limited to 15 bits. * This is because around the edge of 64K boundary (16 bits), one * single poll can make the accumulated ACK counter cross the 64K boundary, * causing problems, when we try to ack with a value greater than 64K. * 15 bits (32K) should be large enough to accumulate, anyways, and the max. * acked events to h/w can be (32K + max poll weight) (currently 64). */ #define BNA_IB_MAX_ACK_EVENTS … /* These macros build the data portion of the TxQ/RxQ doorbell */ #define BNA_DOORBELL_Q_PRD_IDX(_pi) … #define BNA_DOORBELL_Q_STOP … /* These macros build the data portion of the IB doorbell */ #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) … #define BNA_DOORBELL_IB_INT_DISABLE … /* Set the coalescing timer for the given ib */ #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) … /* Acks 'events' # of events for a given ib while disabling interrupts */ #define bna_ib_ack_disable_irq(_i_dbell, _events) … /* Acks 'events' # of events for a given ib */ #define bna_ib_ack(_i_dbell, _events) … #define bna_ib_start(_bna, _ib, _is_regular) … #define bna_ib_stop(_bna, _ib) … #define bna_txq_prod_indx_doorbell(_tcb) … #define bna_rxq_prod_indx_doorbell(_rcb) … /* TxQ, RxQ, CQ related bits, offsets, macros */ /* TxQ Entry Opcodes */ #define BNA_TXQ_WI_SEND … #define BNA_TXQ_WI_SEND_LSO … #define BNA_TXQ_WI_EXTENSION … /* TxQ Entry Control Flags */ #define BNA_TXQ_WI_CF_FCOE_CRC … #define BNA_TXQ_WI_CF_IPID_MODE … #define BNA_TXQ_WI_CF_INS_PRIO … #define BNA_TXQ_WI_CF_INS_VLAN … #define BNA_TXQ_WI_CF_UDP_CKSUM … #define BNA_TXQ_WI_CF_TCP_CKSUM … #define BNA_TXQ_WI_CF_IP_CKSUM … #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) … /* * Completion Q defines */ /* CQ Entry Flags */ #define BNA_CQ_EF_MAC_ERROR … #define BNA_CQ_EF_FCS_ERROR … #define BNA_CQ_EF_TOO_LONG … #define BNA_CQ_EF_FC_CRC_OK … #define BNA_CQ_EF_RSVD1 … #define BNA_CQ_EF_L4_CKSUM_OK … #define BNA_CQ_EF_L3_CKSUM_OK … #define BNA_CQ_EF_HDS_HEADER … #define BNA_CQ_EF_UDP … #define BNA_CQ_EF_TCP … #define BNA_CQ_EF_IP_OPTIONS … #define BNA_CQ_EF_IPV6 … #define BNA_CQ_EF_IPV4 … #define BNA_CQ_EF_VLAN … #define BNA_CQ_EF_RSS … #define BNA_CQ_EF_RSVD2 … #define BNA_CQ_EF_MCAST_MATCH … #define BNA_CQ_EF_MCAST … #define BNA_CQ_EF_BCAST … #define BNA_CQ_EF_REMOTE … #define BNA_CQ_EF_LOCAL … /* CAT2 ASIC does not use bit 21 as per the SPEC. * Bit 31 is set in every end of frame completion */ #define BNA_CQ_EF_EOP … /* Data structures */ struct bna_reg_offset { … }; struct bna_bit_defn { … }; struct bna_reg { … }; /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ struct bna_dma_addr { … }; struct bna_txq_wi_vector { … }; /* TxQ Entry Structure * * BEWARE: Load values into this structure with correct endianness. */ struct bna_txq_entry { … }; /* RxQ Entry Structure */ struct bna_rxq_entry { … }; /* CQ Entry Structure */ struct bna_cq_entry { … }; #endif /* __BNA_HW_DEFS_H__ */
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