/* SPDX-License-Identifier: GPL-2.0-only */ /***************************************************************************** * * * File: elmer0.h * * $Revision: 1.6 $ * * $Date: 2005/06/21 22:49:43 $ * * Description: * * part of the Chelsio 10Gb Ethernet Driver. * * * * * * http://www.chelsio.com * * * * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. * * All rights reserved. * * * * Maintainers: [email protected] * * * * Authors: Dimitrios Michailidis <[email protected]> * * Tina Yang <[email protected]> * * Felix Marti <[email protected]> * * Scott Bardone <[email protected]> * * Kurt Ottaway <[email protected]> * * Frank DiMambro <[email protected]> * * * * History: * * * ****************************************************************************/ #ifndef _CXGB_ELMER0_H_ #define _CXGB_ELMER0_H_ /* ELMER0 flavors */ enum { … }; /* ELMER0 registers */ #define A_ELMER0_VERSION … #define A_ELMER0_PHY_CFG … #define A_ELMER0_INT_ENABLE … #define A_ELMER0_INT_CAUSE … #define A_ELMER0_GPI_CFG … #define A_ELMER0_GPI_STAT … #define A_ELMER0_GPO … #define A_ELMER0_PORT0_MI1_CFG … #define S_MI1_MDI_ENABLE … #define V_MI1_MDI_ENABLE(x) … #define F_MI1_MDI_ENABLE … #define S_MI1_MDI_INVERT … #define V_MI1_MDI_INVERT(x) … #define F_MI1_MDI_INVERT … #define S_MI1_PREAMBLE_ENABLE … #define V_MI1_PREAMBLE_ENABLE(x) … #define F_MI1_PREAMBLE_ENABLE … #define S_MI1_SOF … #define M_MI1_SOF … #define V_MI1_SOF(x) … #define G_MI1_SOF(x) … #define S_MI1_CLK_DIV … #define M_MI1_CLK_DIV … #define V_MI1_CLK_DIV(x) … #define G_MI1_CLK_DIV(x) … #define A_ELMER0_PORT0_MI1_ADDR … #define S_MI1_REG_ADDR … #define M_MI1_REG_ADDR … #define V_MI1_REG_ADDR(x) … #define G_MI1_REG_ADDR(x) … #define S_MI1_PHY_ADDR … #define M_MI1_PHY_ADDR … #define V_MI1_PHY_ADDR(x) … #define G_MI1_PHY_ADDR(x) … #define A_ELMER0_PORT0_MI1_DATA … #define S_MI1_DATA … #define M_MI1_DATA … #define V_MI1_DATA(x) … #define G_MI1_DATA(x) … #define A_ELMER0_PORT0_MI1_OP … #define S_MI1_OP … #define M_MI1_OP … #define V_MI1_OP(x) … #define G_MI1_OP(x) … #define S_MI1_ADDR_AUTOINC … #define V_MI1_ADDR_AUTOINC(x) … #define F_MI1_ADDR_AUTOINC … #define S_MI1_OP_BUSY … #define V_MI1_OP_BUSY(x) … #define F_MI1_OP_BUSY … #define A_ELMER0_PORT1_MI1_CFG … #define A_ELMER0_PORT1_MI1_ADDR … #define A_ELMER0_PORT1_MI1_DATA … #define A_ELMER0_PORT1_MI1_OP … #define A_ELMER0_PORT2_MI1_CFG … #define A_ELMER0_PORT2_MI1_ADDR … #define A_ELMER0_PORT2_MI1_DATA … #define A_ELMER0_PORT2_MI1_OP … #define A_ELMER0_PORT3_MI1_CFG … #define A_ELMER0_PORT3_MI1_ADDR … #define A_ELMER0_PORT3_MI1_DATA … #define A_ELMER0_PORT3_MI1_OP … /* Simple bit definition for GPI and GP0 registers. */ #define ELMER0_GP_BIT0 … #define ELMER0_GP_BIT1 … #define ELMER0_GP_BIT2 … #define ELMER0_GP_BIT3 … #define ELMER0_GP_BIT4 … #define ELMER0_GP_BIT5 … #define ELMER0_GP_BIT6 … #define ELMER0_GP_BIT7 … #define ELMER0_GP_BIT8 … #define ELMER0_GP_BIT9 … #define ELMER0_GP_BIT10 … #define ELMER0_GP_BIT11 … #define ELMER0_GP_BIT12 … #define ELMER0_GP_BIT13 … #define ELMER0_GP_BIT14 … #define ELMER0_GP_BIT15 … #define ELMER0_GP_BIT16 … #define ELMER0_GP_BIT17 … #define ELMER0_GP_BIT18 … #define ELMER0_GP_BIT19 … #define MI1_OP_DIRECT_WRITE … #define MI1_OP_DIRECT_READ … #define MI1_OP_INDIRECT_ADDRESS … #define MI1_OP_INDIRECT_WRITE … #define MI1_OP_INDIRECT_READ_INC … #define MI1_OP_INDIRECT_READ … #endif /* _CXGB_ELMER0_H_ */
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