/* SPDX-License-Identifier: GPL-2.0-only */ /***************************************************************************** * * * File: suni1x10gexp_regs.h * * $Revision: 1.9 $ * * $Date: 2005/06/22 00:17:04 $ * * Description: * * PMC/SIERRA (pm3393) MAC-PHY functionality. * * part of the Chelsio 10Gb Ethernet Driver. * * * * * * http://www.chelsio.com * * * * Maintainers: [email protected] * * * * Authors: PMC/SIERRA * * * * History: * * * ****************************************************************************/ #ifndef _CXGB_SUNI1x10GEXP_REGS_H_ #define _CXGB_SUNI1x10GEXP_REGS_H_ /* ** Space allocated for each Exact Match Filter ** There are 8 filter configurations */ #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER … #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) … /* ** Space allocated for VLAN-Id Filter ** There are 8 filter configurations */ #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER … #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) … /* ** Space allocated for each MSTAT Counter */ #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT … #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) … /******************************************************************************/ /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ /******************************************************************************/ /* Refer to the Register Bit Masks bellow for the naming of each register and */ /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ /******************************************************************************/ #define SUNI1x10GEXP_REG_IDENTIFICATION … #define SUNI1x10GEXP_REG_PRODUCT_REVISION … #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL … #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL … #define SUNI1x10GEXP_REG_DEVICE_STATUS … #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE … #define SUNI1x10GEXP_REG_MDIO_COMMAND … #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS … #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA … #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA … #define SUNI1x10GEXP_REG_OAM_INTF_CTRL … #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_FREE … #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL … #define SUNI1x10GEXP_REG_XRF_MISC_CTRL … #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 … #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 … #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE … #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG … #define SUNI1x10GEXP_REG_RXXG_CONFIG_1 … #define SUNI1x10GEXP_REG_RXXG_CONFIG_2 … #define SUNI1x10GEXP_REG_RXXG_CONFIG_3 … #define SUNI1x10GEXP_REG_RXXG_INTERRUPT … #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH … #define SUNI1x10GEXP_REG_RXXG_SA_15_0 … #define SUNI1x10GEXP_REG_RXXG_SA_31_16 … #define SUNI1x10GEXP_REG_RXXG_SA_47_32 … #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD … #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) … #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) … #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId) … #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 … #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 … #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW … #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW … #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH … #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH … #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 … #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 … #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 … #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL … #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 … #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 … #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 … #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 … #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_XRF_ERR_STATUS … #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES … #define SUNI1x10GEXP_REG_RXOAM_CONFIG … #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG … #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG … #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 … #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG … #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES … #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_RXOAM_STATUS … #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT … #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT … #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB … #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB … #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB … #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB … #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB … #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB … #define SUNI1x10GEXP_REG_MSTAT_CONTROL … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 … #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 … #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 … #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 … #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH … #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) … #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) … #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID … #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH … #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM … #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG … #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION … #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE … #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT … #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS … #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION … #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT … #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT … #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT … #define SUNI1x10GEXP_REG_PL4MOS_CONFIG … #define SUNI1x10GEXP_REG_PL4MOS_MASK … #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING … #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 … #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 … #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE … #define SUNI1x10GEXP_REG_PL4ODP_CONFIG … #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK … #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT … #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T … #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS … #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE … #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK … #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS … #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS … #define SUNI1x10GEXP_REG_PL4IO_CONFIG … #define SUNI1x10GEXP_REG_TXXG_CONFIG_1 … #define SUNI1x10GEXP_REG_TXXG_CONFIG_2 … #define SUNI1x10GEXP_REG_TXXG_CONFIG_3 … #define SUNI1x10GEXP_REG_TXXG_INTERRUPT … #define SUNI1x10GEXP_REG_TXXG_STATUS … #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE … #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE … #define SUNI1x10GEXP_REG_TXXG_SA_15_0 … #define SUNI1x10GEXP_REG_TXXG_SA_31_16 … #define SUNI1x10GEXP_REG_TXXG_SA_47_32 … #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER … #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL … #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER … #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG … #define SUNI1x10GEXP_REG_XTEF_CTRL … #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_XTEF_VISIBILITY … #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG … #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG … #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG … #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES … #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES … #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES … #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE … #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS … #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB … #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB … #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB … #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB … #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK … #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK … #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK … #define SUNI1x10GEXP_REG_TXOAM_COSET … #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB … #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB … #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB … #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB … #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG … #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS … #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS … #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT … #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT … #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT … #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT … #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD … #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE … #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION … #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION … #define SUNI1x10GEXP_REG_PL4IDU_CONFIG … #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK … #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT … /*----------------------------------------*/ #define SUNI1x10GEXP_REG_MAX_OFFSET … /******************************************************************************/ /* -- End register offset definitions -- */ /******************************************************************************/ /******************************************************************************/ /** SUNI-1x10GE-XP REGISTER BIT MASKS **/ /******************************************************************************/ #define SUNI1x10GEXP_BITMSK_BITS_1 … #define SUNI1x10GEXP_BITMSK_BITS_2 … #define SUNI1x10GEXP_BITMSK_BITS_3 … #define SUNI1x10GEXP_BITMSK_BITS_4 … #define SUNI1x10GEXP_BITMSK_BITS_5 … #define SUNI1x10GEXP_BITMSK_BITS_6 … #define SUNI1x10GEXP_BITMSK_BITS_7 … #define SUNI1x10GEXP_BITMSK_BITS_8 … #define SUNI1x10GEXP_BITMSK_BITS_9 … #define SUNI1x10GEXP_BITMSK_BITS_10 … #define SUNI1x10GEXP_BITMSK_BITS_11 … #define SUNI1x10GEXP_BITMSK_BITS_12 … #define SUNI1x10GEXP_BITMSK_BITS_13 … #define SUNI1x10GEXP_BITMSK_BITS_14 … #define SUNI1x10GEXP_BITMSK_BITS_15 … #define SUNI1x10GEXP_BITMSK_BITS_16 … #define mSUNI1x10GEXP_CLR_MSBITS_1(v) … #define mSUNI1x10GEXP_CLR_MSBITS_2(v) … #define mSUNI1x10GEXP_CLR_MSBITS_3(v) … #define mSUNI1x10GEXP_CLR_MSBITS_4(v) … #define mSUNI1x10GEXP_CLR_MSBITS_5(v) … #define mSUNI1x10GEXP_CLR_MSBITS_6(v) … #define mSUNI1x10GEXP_CLR_MSBITS_7(v) … #define mSUNI1x10GEXP_CLR_MSBITS_8(v) … #define mSUNI1x10GEXP_CLR_MSBITS_9(v) … #define mSUNI1x10GEXP_CLR_MSBITS_10(v) … #define mSUNI1x10GEXP_CLR_MSBITS_11(v) … #define mSUNI1x10GEXP_CLR_MSBITS_12(v) … #define mSUNI1x10GEXP_CLR_MSBITS_13(v) … #define mSUNI1x10GEXP_CLR_MSBITS_14(v) … #define mSUNI1x10GEXP_CLR_MSBITS_15(v) … #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) … /*---------------------------------------------------------------------------- * Register 0x0001: S/UNI-1x10GE-XP Product Revision * Bit 3-0 REVISION *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_REVISION … /*---------------------------------------------------------------------------- * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control * Bit 2 XAUI_ARESETB * Bit 1 PL4_ARESETB * Bit 0 DRESETB *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_XAUI_ARESET … #define SUNI1x10GEXP_BITMSK_PL4_ARESET … #define SUNI1x10GEXP_BITMSK_DRESETB … /*---------------------------------------------------------------------------- * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control * Bit 11 PL4IO_OUTCLKSEL * Bit 9 SYSPCSLB * Bit 8 LINEPCSLB * Bit 7 MSTAT_BYPASS * Bit 6 RXXG_BYPASS * Bit 5 TXXG_BYPASS * Bit 4 SOP_PAD_EN * Bit 1 LOS_INV * Bit 0 OVERRIDE_LOS *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL … #define SUNI1x10GEXP_BITMSK_SYSPCSLB … #define SUNI1x10GEXP_BITMSK_LINEPCSLB … #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS … #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS … #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS … #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN … #define SUNI1x10GEXP_BITMSK_LOS_INV … #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS … /*---------------------------------------------------------------------------- * Register 0x0004: S/UNI-1x10GE-XP Device Status * Bit 9 TOP_SXRA_EXPIRED * Bit 8 TOP_MDIO_BUSY * Bit 7 TOP_DTRB * Bit 6 TOP_EXPIRED * Bit 5 TOP_PAUSED * Bit 4 TOP_PL4_ID_DOOL * Bit 3 TOP_PL4_IS_DOOL * Bit 2 TOP_PL4_ID_ROOL * Bit 1 TOP_PL4_IS_ROOL * Bit 0 TOP_PL4_OUT_ROOL *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED … #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY … #define SUNI1x10GEXP_BITMSK_TOP_DTRB … #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED … #define SUNI1x10GEXP_BITMSK_TOP_PAUSED … #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL … #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL … #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL … #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL … #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL … /*---------------------------------------------------------------------------- * Register 0x0005: Global Performance Update and Clock Monitors * Bit 15 TIP * Bit 8 XAUI_REF_CLKA * Bit 7 RXLANE3CLKA * Bit 6 RXLANE2CLKA * Bit 5 RXLANE1CLKA * Bit 4 RXLANE0CLKA * Bit 3 CSUCLKA * Bit 2 TDCLKA * Bit 1 RSCLKA * Bit 0 RDCLKA *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TIP … #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA … #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA … #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA … #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA … #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA … #define SUNI1x10GEXP_BITMSK_CSUCLKA … #define SUNI1x10GEXP_BITMSK_TDCLKA … #define SUNI1x10GEXP_BITMSK_RSCLKA … #define SUNI1x10GEXP_BITMSK_RDCLKA … /*---------------------------------------------------------------------------- * Register 0x0006: MDIO Command * Bit 4 MDIO_RDINC * Bit 3 MDIO_RSTAT * Bit 2 MDIO_LCTLD * Bit 1 MDIO_LCTLA * Bit 0 MDIO_SPRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MDIO_RDINC … #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT … #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD … #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA … #define SUNI1x10GEXP_BITMSK_MDIO_SPRE … /*---------------------------------------------------------------------------- * Register 0x0007: MDIO Interrupt Enable * Bit 0 MDIO_BUSY_EN *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN … /*---------------------------------------------------------------------------- * Register 0x0008: MDIO Interrupt Status * Bit 0 MDIO_BUSYI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI … /*---------------------------------------------------------------------------- * Register 0x0009: MMD PHY Address * Bit 12-8 MDIO_DEVADR * Bit 4-0 MDIO_PRTADR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR … #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR … #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR … #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR … /*---------------------------------------------------------------------------- * Register 0x000C: OAM Interface Control * Bit 6 MDO_OD_ENB * Bit 5 MDI_INV * Bit 4 MDI_SEL * Bit 3 RXOAMEN * Bit 2 RXOAMCLKEN * Bit 1 TXOAMEN * Bit 0 TXOAMCLKEN *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB … #define SUNI1x10GEXP_BITMSK_MDI_INV … #define SUNI1x10GEXP_BITMSK_MDI_SEL … #define SUNI1x10GEXP_BITMSK_RXOAMEN … #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN … #define SUNI1x10GEXP_BITMSK_TXOAMEN … #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN … /*---------------------------------------------------------------------------- * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status * Bit 15 TOP_PL4IO_INT * Bit 14 TOP_IRAM_INT * Bit 13 TOP_ERAM_INT * Bit 12 TOP_XAUI_INT * Bit 11 TOP_MSTAT_INT * Bit 10 TOP_RXXG_INT * Bit 9 TOP_TXXG_INT * Bit 8 TOP_XRF_INT * Bit 7 TOP_XTEF_INT * Bit 6 TOP_MDIO_BUSY_INT * Bit 5 TOP_RXOAM_INT * Bit 4 TOP_TXOAM_INT * Bit 3 TOP_IFLX_INT * Bit 2 TOP_EFLX_INT * Bit 1 TOP_PL4ODP_INT * Bit 0 TOP_PL4IDU_INT *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT … #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT … #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT … #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT … #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT … #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT … #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT … #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT … #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT … #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT … #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT … #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT … #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT … #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT … #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT … #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT … /*---------------------------------------------------------------------------- * Register 0x000E:PM3393 Global interrupt enable * Bit 15 TOP_INTE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TOP_INTE … /*---------------------------------------------------------------------------- * Register 0x0010: XTEF Miscellaneous Control * Bit 7 RF_VAL * Bit 6 RF_OVERRIDE * Bit 5 LF_VAL * Bit 4 LF_OVERRIDE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RF_VAL … #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE … #define SUNI1x10GEXP_BITMSK_LF_VAL … #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE … #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL … /*---------------------------------------------------------------------------- * Register 0x0011: XRF Miscellaneous Control * Bit 6-4 EN_IDLE_REP *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP … /*---------------------------------------------------------------------------- * Register 0x0100: SERDES 3125 Configuration Register 1 * Bit 10 RXEQB_3 * Bit 8 RXEQB_2 * Bit 6 RXEQB_1 * Bit 4 RXEQB_0 *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXEQB … #define SUNI1x10GEXP_BITOFF_RXEQB_3 … #define SUNI1x10GEXP_BITOFF_RXEQB_2 … #define SUNI1x10GEXP_BITOFF_RXEQB_1 … #define SUNI1x10GEXP_BITOFF_RXEQB_0 … /*---------------------------------------------------------------------------- * Register 0x0101: SERDES 3125 Configuration Register 2 * Bit 12 YSEL * Bit 7 PRE_EMPH_3 * Bit 6 PRE_EMPH_2 * Bit 5 PRE_EMPH_1 * Bit 4 PRE_EMPH_0 *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_YSEL … #define SUNI1x10GEXP_BITMSK_PRE_EMPH … #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 … #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 … #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 … #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 … /*---------------------------------------------------------------------------- * Register 0x0102: SERDES 3125 Interrupt Enable Register * Bit 3 LASIE * Bit 2 SPLL_RAE * Bit 1 MPLL_RAE * Bit 0 PLL_LOCKE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LASIE … #define SUNI1x10GEXP_BITMSK_SPLL_RAE … #define SUNI1x10GEXP_BITMSK_MPLL_RAE … #define SUNI1x10GEXP_BITMSK_PLL_LOCKE … /*---------------------------------------------------------------------------- * Register 0x0103: SERDES 3125 Interrupt Visibility Register * Bit 3 LASIV * Bit 2 SPLL_RAV * Bit 1 MPLL_RAV * Bit 0 PLL_LOCKV *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LASIV … #define SUNI1x10GEXP_BITMSK_SPLL_RAV … #define SUNI1x10GEXP_BITMSK_MPLL_RAV … #define SUNI1x10GEXP_BITMSK_PLL_LOCKV … /*---------------------------------------------------------------------------- * Register 0x0104: SERDES 3125 Interrupt Status Register * Bit 3 LASII * Bit 2 SPLL_RAI * Bit 1 MPLL_RAI * Bit 0 PLL_LOCKI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LASII … #define SUNI1x10GEXP_BITMSK_SPLL_RAI … #define SUNI1x10GEXP_BITMSK_MPLL_RAI … #define SUNI1x10GEXP_BITMSK_PLL_LOCKI … /*---------------------------------------------------------------------------- * Register 0x0107: SERDES 3125 Test Configuration * Bit 12 DUALTX * Bit 10 HC_1 * Bit 9 HC_0 *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_DUALTX … #define SUNI1x10GEXP_BITMSK_HC … #define SUNI1x10GEXP_BITOFF_HC_0 … /*---------------------------------------------------------------------------- * Register 0x2040: RXXG Configuration 1 * Bit 15 RXXG_RXEN * Bit 14 RXXG_ROCF * Bit 13 RXXG_PAD_STRIP * Bit 10 RXXG_PUREP * Bit 9 RXXG_LONGP * Bit 8 RXXG_PARF * Bit 7 RXXG_FLCHK * Bit 5 RXXG_PASS_CTRL * Bit 3 RXXG_CRC_STRIP * Bit 2-0 RXXG_MIFG *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_RXEN … #define SUNI1x10GEXP_BITMSK_RXXG_ROCF … #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP … #define SUNI1x10GEXP_BITMSK_RXXG_PUREP … #define SUNI1x10GEXP_BITMSK_RXXG_LONGP … #define SUNI1x10GEXP_BITMSK_RXXG_PARF … #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK … #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL … #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP … /*---------------------------------------------------------------------------- * Register 0x02041: RXXG Configuration 2 * Bit 7-0 RXXG_HDRSIZE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE … /*---------------------------------------------------------------------------- * Register 0x2042: RXXG Configuration 3 * Bit 15 RXXG_MIN_LERRE * Bit 14 RXXG_MAX_LERRE * Bit 12 RXXG_LINE_ERRE * Bit 10 RXXG_RX_OVRE * Bit 9 RXXG_ADR_FILTERE * Bit 8 RXXG_ERR_FILTERE * Bit 5 RXXG_PRMB_ERRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE … #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE … #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE … #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE … #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE … #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE … #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE … /*---------------------------------------------------------------------------- * Register 0x2043: RXXG Interrupt * Bit 15 RXXG_MIN_LERRI * Bit 14 RXXG_MAX_LERRI * Bit 12 RXXG_LINE_ERRI * Bit 10 RXXG_RX_OVRI * Bit 9 RXXG_ADR_FILTERI * Bit 8 RXXG_ERR_FILTERI * Bit 5 RXXG_PRMB_ERRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI … #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI … #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI … #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI … #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI … #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI … #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE … /*---------------------------------------------------------------------------- * Register 0x2049: RXXG Receive FIFO Threshold * Bit 2-0 RXXG_CUT_THRU *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU … #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU … /*---------------------------------------------------------------------------- * Register 0x2062H - 0x2069: RXXG Exact Match VID * Bit 11-0 RXXG_VID_MATCH *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH … #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH … /*---------------------------------------------------------------------------- * Register 0x206EH - 0x206F: RXXG Address Filter Control * Bit 3 RXXG_FORWARD_ENABLE * Bit 2 RXXG_VLAN_ENABLE * Bit 1 RXXG_SRC_ADDR * Bit 0 RXXG_MATCH_ENABLE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE … #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE … #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR … #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE … /*---------------------------------------------------------------------------- * Register 0x2070: RXXG Address Filter Control 2 * Bit 1 RXXG_PMODE * Bit 0 RXXG_MHASH_EN *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXXG_PMODE … #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN … /*---------------------------------------------------------------------------- * Register 0x2081: XRF Control Register 2 * Bit 6 EN_PKT_GEN * Bit 4-2 PATT *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN … #define SUNI1x10GEXP_BITMSK_PATT … #define SUNI1x10GEXP_BITOFF_PATT … /*---------------------------------------------------------------------------- * Register 0x2088: XRF Interrupt Enable * Bit 12-9 LANE_HICERE * Bit 8-5 HS_SD_LANEE * Bit 4 ALIGN_STATUS_ERRE * Bit 3-0 LANE_SYNC_STAT_ERRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LANE_HICERE … #define SUNI1x10GEXP_BITOFF_LANE_HICERE … #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE … #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE … #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE … #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE … #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE … /*---------------------------------------------------------------------------- * Register 0x2089: XRF Interrupt Status * Bit 12-9 LANE_HICERI * Bit 8-5 HS_SD_LANEI * Bit 4 ALIGN_STATUS_ERRI * Bit 3-0 LANE_SYNC_STAT_ERRI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LANE_HICERI … #define SUNI1x10GEXP_BITOFF_LANE_HICERI … #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI … #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI … #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI … #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI … #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI … /*---------------------------------------------------------------------------- * Register 0x208A: XRF Error Status * Bit 8-5 HS_SD_LANE * Bit 4 ALIGN_STATUS_ERR * Bit 3-0 LANE_SYNC_STAT_ERR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 … #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 … #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 … #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 … #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR … #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR … #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR … #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR … #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR … /*---------------------------------------------------------------------------- * Register 0x208B: XRF Diagnostic Interrupt Enable * Bit 7-4 LANE_OVERRUNE * Bit 3-0 LANE_UNDERRUNE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE … #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE … #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE … #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE … /*---------------------------------------------------------------------------- * Register 0x208C: XRF Diagnostic Interrupt Status * Bit 7-4 LANE_OVERRUNI * Bit 3-0 LANE_UNDERRUNI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI … #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI … #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI … #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI … /*---------------------------------------------------------------------------- * Register 0x20C0: RXOAM Configuration * Bit 15 RXOAM_BUSY * Bit 14-12 RXOAM_F2_SEL * Bit 10-8 RXOAM_F1_SEL * Bit 7-6 RXOAM_FILTER_CTRL * Bit 5-0 RXOAM_PX_EN *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY … #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL … #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL … #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL … #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL … #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL … #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL … #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN … #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN … /*---------------------------------------------------------------------------- * Register 0x20C1,0x20C2: RXOAM Filter Configuration * Bit 15-8 RXOAM_FX_MASK * Bit 7-0 RXOAM_FX_VAL *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK … #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK … #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL … #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl … /*---------------------------------------------------------------------------- * Register 0x20C3: RXOAM Configuration Register 2 * Bit 13 RXOAM_REC_BYTE_VAL * Bit 11-10 RXOAM_BYPASS_MODE * Bit 5-0 RXOAM_PX_CLEAR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL … #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE … #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE … #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR … #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR … /*---------------------------------------------------------------------------- * Register 0x20C4: RXOAM HEC Configuration * Bit 15-8 RXOAM_COSET * Bit 2 RXOAM_HEC_ERR_PKT * Bit 0 RXOAM_HEC_EN *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_COSET … #define SUNI1x10GEXP_BITOFF_RXOAM_COSET … #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT … #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN … /*---------------------------------------------------------------------------- * Register 0x20C7: RXOAM Interrupt Enable * Bit 10 RXOAM_FILTER_THRSHE * Bit 9 RXOAM_OAM_ERRE * Bit 8 RXOAM_HECE_THRSHE * Bit 7 RXOAM_SOPE * Bit 6 RXOAM_RFE * Bit 5 RXOAM_LFE * Bit 4 RXOAM_DV_ERRE * Bit 3 RXOAM_DATA_INVALIDE * Bit 2 RXOAM_FILTER_DROPE * Bit 1 RXOAM_HECE * Bit 0 RXOAM_OFLE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE … #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE … #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE … #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE … #define SUNI1x10GEXP_BITMSK_RXOAM_RFE … #define SUNI1x10GEXP_BITMSK_RXOAM_LFE … #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE … #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE … #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE … #define SUNI1x10GEXP_BITMSK_RXOAM_HECE … #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE … /*---------------------------------------------------------------------------- * Register 0x20C8: RXOAM Interrupt Status * Bit 10 RXOAM_FILTER_THRSHI * Bit 9 RXOAM_OAM_ERRI * Bit 8 RXOAM_HECE_THRSHI * Bit 7 RXOAM_SOPI * Bit 6 RXOAM_RFI * Bit 5 RXOAM_LFI * Bit 4 RXOAM_DV_ERRI * Bit 3 RXOAM_DATA_INVALIDI * Bit 2 RXOAM_FILTER_DROPI * Bit 1 RXOAM_HECI * Bit 0 RXOAM_OFLI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI … #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI … #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI … #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI … #define SUNI1x10GEXP_BITMSK_RXOAM_RFI … #define SUNI1x10GEXP_BITMSK_RXOAM_LFI … #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI … #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI … #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI … #define SUNI1x10GEXP_BITMSK_RXOAM_HECI … #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI … /*---------------------------------------------------------------------------- * Register 0x20C9: RXOAM Status * Bit 10 RXOAM_FILTER_THRSHV * Bit 8 RXOAM_HECE_THRSHV * Bit 6 RXOAM_RFV * Bit 5 RXOAM_LFV *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV … #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV … #define SUNI1x10GEXP_BITMSK_RXOAM_RFV … #define SUNI1x10GEXP_BITMSK_RXOAM_LFV … /*---------------------------------------------------------------------------- * Register 0x2100: MSTAT Control * Bit 2 MSTAT_WRITE * Bit 1 MSTAT_CLEAR * Bit 0 MSTAT_SNAP *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE … #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR … #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP … /*---------------------------------------------------------------------------- * Register 0x2109: MSTAT Counter Write Address * Bit 5-0 MSTAT_WRITE_ADDRESS *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS … #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS … /*---------------------------------------------------------------------------- * Register 0x2200: IFLX Global Configuration Register * Bit 15 IFLX_IRCU_ENABLE * Bit 14 IFLX_IDSWT_ENABLE * Bit 13-0 IFLX_IFD_CNT *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE … #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE … #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT … #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT … /*---------------------------------------------------------------------------- * Register 0x2209: IFLX FIFO Overflow Enable * Bit 0 IFLX_OVFE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_OVFE … /*---------------------------------------------------------------------------- * Register 0x220A: IFLX FIFO Overflow Interrupt * Bit 0 IFLX_OVFI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_OVFI … /*---------------------------------------------------------------------------- * Register 0x220D: IFLX Indirect Channel Address * Bit 15 IFLX_BUSY * Bit 14 IFLX_RWB *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_BUSY … #define SUNI1x10GEXP_BITMSK_IFLX_RWB … /*---------------------------------------------------------------------------- * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision * Bit 9-0 IFLX_LOLIM *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM … #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM … /*---------------------------------------------------------------------------- * Register 0x220F: IFLX Indirect Logical FIFO High Limit * Bit 9-0 IFLX_HILIM *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_HILIM … #define SUNI1x10GEXP_BITOFF_IFLX_HILIM … /*---------------------------------------------------------------------------- * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit * Bit 15 IFLX_FULL * Bit 14 IFLX_AFULL * Bit 13-0 IFLX_AFTH *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_FULL … #define SUNI1x10GEXP_BITMSK_IFLX_AFULL … #define SUNI1x10GEXP_BITMSK_IFLX_AFTH … #define SUNI1x10GEXP_BITOFF_IFLX_AFTH … /*---------------------------------------------------------------------------- * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit * Bit 15 IFLX_EMPTY * Bit 14 IFLX_AEMPTY * Bit 13-0 IFLX_AETH *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY … #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY … #define SUNI1x10GEXP_BITMSK_IFLX_AETH … #define SUNI1x10GEXP_BITOFF_IFLX_AETH … /*---------------------------------------------------------------------------- * Register 0x2240: PL4MOS Configuration Register * Bit 3 PL4MOS_RE_INIT * Bit 2 PL4MOS_EN * Bit 1 PL4MOS_NO_STATUS *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT … #define SUNI1x10GEXP_BITMSK_PL4MOS_EN … #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS … /*---------------------------------------------------------------------------- * Register 0x2243: PL4MOS MaxBurst1 Register * Bit 11-0 PL4MOS_MAX_BURST1 *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 … #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 … /*---------------------------------------------------------------------------- * Register 0x2244: PL4MOS MaxBurst2 Register * Bit 11-0 PL4MOS_MAX_BURST2 *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 … #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 … /*---------------------------------------------------------------------------- * Register 0x2245: PL4MOS Transfer Size Register * Bit 7-0 PL4MOS_MAX_TRANSFER *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER … #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER … /*---------------------------------------------------------------------------- * Register 0x2280: PL4ODP Configuration * Bit 15-12 PL4ODP_REPEAT_T * Bit 8 PL4ODP_SOP_RULE * Bit 1 PL4ODP_EN_PORTS * Bit 0 PL4ODP_EN_DFWD *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T … #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T … #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE … #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS … #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD … /*---------------------------------------------------------------------------- * Register 0x2282: PL4ODP Interrupt Mask * Bit 0 PL4ODP_OUT_DISE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE … #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE … /*---------------------------------------------------------------------------- * Register 0x2283: PL4ODP Interrupt * Bit 0 PL4ODP_OUT_DISI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI … #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI … #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI … /*---------------------------------------------------------------------------- * Register 0x2300: PL4IO Lock Detect Status * Bit 15 PL4IO_OUT_ROOLV * Bit 12 PL4IO_IS_ROOLV * Bit 11 PL4IO_DIP2_ERRV * Bit 8 PL4IO_ID_ROOLV * Bit 4 PL4IO_IS_DOOLV * Bit 0 PL4IO_ID_DOOLV *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV … #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV … /*---------------------------------------------------------------------------- * Register 0x2301: PL4IO Lock Detect Change * Bit 15 PL4IO_OUT_ROOLI * Bit 12 PL4IO_IS_ROOLI * Bit 11 PL4IO_DIP2_ERRI * Bit 8 PL4IO_ID_ROOLI * Bit 4 PL4IO_IS_DOOLI * Bit 0 PL4IO_ID_DOOLI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI … #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI … /*---------------------------------------------------------------------------- * Register 0x2302: PL4IO Lock Detect Mask * Bit 15 PL4IO_OUT_ROOLE * Bit 12 PL4IO_IS_ROOLE * Bit 11 PL4IO_DIP2_ERRE * Bit 8 PL4IO_ID_ROOLE * Bit 4 PL4IO_IS_DOOLE * Bit 0 PL4IO_ID_DOOLE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE … #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE … #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE … #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE … /*---------------------------------------------------------------------------- * Register 0x2303: PL4IO Lock Detect Limits * Bit 15-8 PL4IO_REF_LIMIT * Bit 7-0 PL4IO_TRAN_LIMIT *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT … #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT … #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT … #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT … /*---------------------------------------------------------------------------- * Register 0x2304: PL4IO Calendar Repetitions * Bit 15-8 PL4IO_IN_MUL * Bit 7-0 PL4IO_OUT_MUL *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL … #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL … #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL … #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL … /*---------------------------------------------------------------------------- * Register 0x2305: PL4IO Configuration * Bit 15 PL4IO_DIP2_ERR_CHK * Bit 11 PL4IO_ODAT_DIS * Bit 10 PL4IO_TRAIN_DIS * Bit 9 PL4IO_OSTAT_DIS * Bit 8 PL4IO_ISTAT_DIS * Bit 7 PL4IO_NO_ISTAT * Bit 6 PL4IO_STAT_OUTSEL * Bit 5 PL4IO_INSEL * Bit 4 PL4IO_DLSEL * Bit 1-0 PL4IO_OUTSEL *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK … #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS … #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS … #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS … #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS … #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT … #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL … #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL … #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL … #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL … #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL … /*---------------------------------------------------------------------------- * Register 0x3040: TXXG Configuration Register 1 * Bit 15 TXXG_TXEN0 * Bit 13 TXXG_HOSTPAUSE * Bit 12-7 TXXG_IPGT * Bit 5 TXXG_32BIT_ALIGN * Bit 4 TXXG_CRCEN * Bit 3 TXXG_FCTX * Bit 2 TXXG_FCRX * Bit 1 TXXG_PADEN * Bit 0 TXXG_SPRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 … #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE … #define SUNI1x10GEXP_BITMSK_TXXG_IPGT … #define SUNI1x10GEXP_BITOFF_TXXG_IPGT … #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN … #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN … #define SUNI1x10GEXP_BITMSK_TXXG_FCTX … #define SUNI1x10GEXP_BITMSK_TXXG_FCRX … #define SUNI1x10GEXP_BITMSK_TXXG_PADEN … #define SUNI1x10GEXP_BITMSK_TXXG_SPRE … /*---------------------------------------------------------------------------- * Register 0x3041: TXXG Configuration Register 2 * Bit 7-0 TXXG_HDRSIZE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE … /*---------------------------------------------------------------------------- * Register 0x3042: TXXG Configuration Register 3 * Bit 15 TXXG_FIFO_ERRE * Bit 14 TXXG_FIFO_UDRE * Bit 13 TXXG_MAX_LERRE * Bit 12 TXXG_MIN_LERRE * Bit 11 TXXG_XFERE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE … #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE … #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE … #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE … #define SUNI1x10GEXP_BITMSK_TXXG_XFERE … /*---------------------------------------------------------------------------- * Register 0x3043: TXXG Interrupt * Bit 15 TXXG_FIFO_ERRI * Bit 14 TXXG_FIFO_UDRI * Bit 13 TXXG_MAX_LERRI * Bit 12 TXXG_MIN_LERRI * Bit 11 TXXG_XFERI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI … #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI … #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI … #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI … #define SUNI1x10GEXP_BITMSK_TXXG_XFERI … /*---------------------------------------------------------------------------- * Register 0x3044: TXXG Status Register * Bit 1 TXXG_TXACTIVE * Bit 0 TXXG_PAUSED *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE … #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED … /*---------------------------------------------------------------------------- * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register * Bit 7-0 TXXG_TX_MINFR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR … #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR … /*---------------------------------------------------------------------------- * Register 0x3052: TXXG Pause Quantum Value Configuration Register * Bit 7-0 TXXG_FC_PAUSE_QNTM *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM … #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM … /*---------------------------------------------------------------------------- * Register 0x3080: XTEF Control * Bit 3-0 XTEF_FORCE_PARITY_ERR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR … #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR … /*---------------------------------------------------------------------------- * Register 0x3084: XTEF Interrupt Event Register * Bit 0 XTEF_LOST_SYNCI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI … /*---------------------------------------------------------------------------- * Register 0x3085: XTEF Interrupt Enable Register * Bit 0 XTEF_LOST_SYNCE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE … /*---------------------------------------------------------------------------- * Register 0x3086: XTEF Visibility Register * Bit 0 XTEF_LOST_SYNCV *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV … /*---------------------------------------------------------------------------- * Register 0x30C0: TXOAM OAM Configuration * Bit 15 TXOAM_HEC_EN * Bit 14 TXOAM_EMPTYCODE_EN * Bit 13 TXOAM_FORCE_IDLE * Bit 12 TXOAM_IGNORE_IDLE * Bit 11-6 TXOAM_PX_OVERWRITE * Bit 5-0 TXOAM_PX_SEL *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN … #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN … #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE … #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE … #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE … #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE … #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL … #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL … /*---------------------------------------------------------------------------- * Register 0x30C1: TXOAM Mini-Packet Rate Configuration * Bit 15 TXOAM_MINIDIS * Bit 14 TXOAM_BUSY * Bit 13 TXOAM_TRANS_EN * Bit 10-0 TXOAM_MINIRATE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS … #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY … #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN … #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE … /*---------------------------------------------------------------------------- * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration * Bit 13-10 TXOAM_FTHRESH * Bit 9-6 TXOAM_MINIPOST * Bit 5-0 TXOAM_MINIPRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH … #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH … #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST … #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST … #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE … /*---------------------------------------------------------------------------- * Register 0x30C6: TXOAM Interrupt Enable * Bit 2 TXOAM_SOP_ERRE * Bit 1 TXOAM_OFLE * Bit 0 TXOAM_ERRE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE … #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE … #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE … /*---------------------------------------------------------------------------- * Register 0x30C7: TXOAM Interrupt Status * Bit 2 TXOAM_SOP_ERRI * Bit 1 TXOAM_OFLI * Bit 0 TXOAM_ERRI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI … #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI … #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI … /*---------------------------------------------------------------------------- * Register 0x30CF: TXOAM Coset * Bit 7-0 TXOAM_COSET *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_TXOAM_COSET … /*---------------------------------------------------------------------------- * Register 0x3200: EFLX Global Configuration * Bit 15 EFLX_ERCU_EN * Bit 7 EFLX_EN_EDSWT *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN … #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT … /*---------------------------------------------------------------------------- * Register 0x3201: EFLX ERCU Global Status * Bit 13 EFLX_OVF_ERR *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR … /*---------------------------------------------------------------------------- * Register 0x3202: EFLX Indirect Channel Address * Bit 15 EFLX_BUSY * Bit 14 EFLX_RDWRB *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_BUSY … #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB … /*---------------------------------------------------------------------------- * Register 0x3203: EFLX Indirect Logical FIFO Low Limit *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM … #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM … /*---------------------------------------------------------------------------- * Register 0x3204: EFLX Indirect Logical FIFO High Limit *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_HILIM … #define SUNI1x10GEXP_BITOFF_EFLX_HILIM … /*---------------------------------------------------------------------------- * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit * Bit 15 EFLX_FULL * Bit 14 EFLX_AFULL * Bit 13-0 EFLX_AFTH *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_FULL … #define SUNI1x10GEXP_BITMSK_EFLX_AFULL … #define SUNI1x10GEXP_BITMSK_EFLX_AFTH … #define SUNI1x10GEXP_BITOFF_EFLX_AFTH … /*---------------------------------------------------------------------------- * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit * Bit 15 EFLX_EMPTY * Bit 14 EFLX_AEMPTY * Bit 13-0 EFLX_AETH *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY … #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY … #define SUNI1x10GEXP_BITMSK_EFLX_AETH … #define SUNI1x10GEXP_BITOFF_EFLX_AETH … /*---------------------------------------------------------------------------- * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU … #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU … /*---------------------------------------------------------------------------- * Register 0x320C: EFLX FIFO Overflow Error Enable * Bit 0 EFLX_OVFE *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_OVFE … /*---------------------------------------------------------------------------- * Register 0x320D: EFLX FIFO Overflow Error Indication * Bit 0 EFLX_OVFI *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_OVFI … /*---------------------------------------------------------------------------- * Register 0x3210: EFLX Channel Provision * Bit 0 EFLX_PROV *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_EFLX_PROV … /*---------------------------------------------------------------------------- * Register 0x3280: PL4IDU Configuration * Bit 2 PL4IDU_SYNCH_ON_TRAIN * Bit 1 PL4IDU_EN_PORTS * Bit 0 PL4IDU_EN_DFWD *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN … #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS … #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD … /*---------------------------------------------------------------------------- * Register 0x3282: PL4IDU Interrupt Mask * Bit 1 PL4IDU_DIP4E *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E … /*---------------------------------------------------------------------------- * Register 0x3283: PL4IDU Interrupt * Bit 1 PL4IDU_DIP4I *----------------------------------------------------------------------------*/ #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I … #endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
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