/* SPDX-License-Identifier: GPL-2.0 */ /* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */ #ifndef _VSC7321_REG_H_ #define _VSC7321_REG_H_ /* Register definitions for Vitesse VSC7321 (Meigs II) MAC * * Straight off the data sheet, VMDS-10038 Rev 2.0 and * PD0011-01-14-Meigs-II 2002-12-12 */ /* Just 'cause it's in here doesn't mean it's used. */ #define CRA(blk,sub,adr) … /* System and CPU comm's registers */ #define REG_CHIP_ID … #define REG_BLADE_ID … #define REG_SW_RESET … #define REG_MEM_BIST … #define REG_IFACE_MODE … #define REG_MSCH … #define REG_CRC_CNT … #define REG_CRC_CFG … #define REG_SI_TRANSFER_SEL … #define REG_PLL_CLK_SPEED … #define REG_SYS_CLK_SELECT … #define REG_GPIO_CTRL … #define REG_GPIO_OUT … #define REG_GPIO_IN … #define REG_CPU_TRANSFER_SEL … #define REG_LOCAL_DATA … #define REG_LOCAL_STATUS … /* Aggregator registers */ #define REG_AGGR_SETUP … #define REG_PMAP_TABLE … #define REG_MPLS_BIT0 … #define REG_MPLS_BIT1 … #define REG_MPLS_BIT2 … #define REG_MPLS_BIT3 … #define REG_MPLS_BITMASK … #define REG_PRE_BIT0POS … #define REG_PRE_BIT1POS … #define REG_PRE_BIT2POS … #define REG_PRE_BIT3POS … #define REG_PRE_ERR_CNT … /* BIST registers */ /*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */ /*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */ #define REG_RAM_BIST_CMD … #define REG_RAM_BIST_RESULT … #define BIST_PORT_SELECT … #define BIST_COMMAND … #define BIST_STATUS … #define BIST_ERR_CNT_LSB … #define BIST_ERR_CNT_MSB … #define BIST_ERR_SEL_LSB … #define BIST_ERR_SEL_MSB … #define BIST_ERROR_STATE … #define BIST_ERR_ADR0 … #define BIST_ERR_ADR1 … #define BIST_ERR_ADR2 … #define BIST_ERR_ADR3 … /* FIFO registers * ie = 0 for ingress, 1 for egress * fn = FIFO number, 0-9 */ #define REG_TEST(ie,fn) … #define REG_TOP_BOTTOM(ie,fn) … #define REG_TAIL(ie,fn) … #define REG_HEAD(ie,fn) … #define REG_HIGH_LOW_WM(ie,fn) … #define REG_CT_THRHLD(ie,fn) … #define REG_FIFO_DROP_CNT(ie,fn) … #define REG_DEBUG_BUF_CNT(ie,fn) … #define REG_BUCKI(fn) … #define REG_BUCKE(fn) … /* Traffic shaper buckets * ie = 0 for ingress, 1 for egress * bn = bucket number 0-10 (yes, 11 buckets) */ /* OK, this one's kinda ugly. Some hardware designers are perverse. */ #define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) … #define REG_TRAFFIC_SHAPER_CONTROL(ie) … #define REG_SRAM_ADR(ie) … #define REG_SRAM_WR_STRB(ie) … #define REG_SRAM_RD_STRB(ie) … #define REG_SRAM_DATA_0(ie) … #define REG_SRAM_DATA_1(ie) … #define REG_SRAM_DATA_2(ie) … #define REG_SRAM_DATA_3(ie) … #define REG_SRAM_DATA_BLK_TYPE(ie) … /* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */ #define REG_CONTROL(ie) … #define REG_ING_CONTROL … #define REG_EGR_CONTROL … #define REG_AGE_TIMER(ie) … #define REG_AGE_INC(ie) … #define DEBUG_OUT(ie) … #define DEBUG_CNT(ie) … /* SPI4 interface */ #define REG_SPI4_MISC … #define REG_SPI4_STATUS … #define REG_SPI4_ING_SETUP0 … #define REG_SPI4_ING_SETUP1 … #define REG_SPI4_ING_SETUP2 … #define REG_SPI4_EGR_SETUP0 … #define REG_SPI4_DBG_CNT(n) … #define REG_SPI4_DBG_SETUP … #define REG_SPI4_TEST … #define REG_TPGEN_UP0 … #define REG_TPGEN_UP1 … #define REG_TPCHK_UP0 … #define REG_TPCHK_UP1 … #define REG_TPSAM_P0 … #define REG_TPSAM_P1 … #define REG_TPERR_CNT … #define REG_SPI4_STICKY … #define REG_SPI4_DBG_INH … #define REG_SPI4_DBG_STATUS … #define REG_SPI4_DBG_GRANT … #define REG_SPI4_DESKEW … /* 10GbE MAC Block Registers */ /* Note that those registers that are exactly the same for 10GbE as for * tri-speed are only defined with the version that needs a port number. * Pass 0xa in those cases. * * Also note that despite the presence of a MAC address register, this part * does no ingress MAC address filtering. That register is used only for * pause frame detection and generation. */ /* 10GbE specific, and different from tri-speed */ #define REG_MISC_10G … #define REG_PAUSE_10G … #define REG_NORMALIZER_10G … #define REG_STICKY_RX … #define REG_DENORM_10G … #define REG_STICKY_TX … #define REG_MAX_RXHIGH … #define REG_MAX_RXLOW … #define REG_MAC_TX_STICKY … #define REG_MAC_TX_RUNNING … #define REG_TX_ABORT_AGE … #define REG_TX_ABORT_SHORT … #define REG_TX_ABORT_TAXI … #define REG_TX_ABORT_UNDERRUN … #define REG_TX_DENORM_DISCARD … #define REG_XAUI_STAT_A … #define REG_XAUI_STAT_B … #define REG_XAUI_STAT_C … #define REG_XAUI_CONF_A … #define REG_XAUI_CONF_B … #define REG_XAUI_CODE_GRP_CNT … #define REG_XAUI_CONF_TEST_A … #define REG_PDERRCNT … /* pn = port number 0-9 for tri-speed, 10 for 10GbE */ /* Both tri-speed and 10GbE */ #define REG_MAX_LEN(pn) … #define REG_MAC_HIGH_ADDR(pn) … #define REG_MAC_LOW_ADDR(pn) … /* tri-speed only * pn = port number, 0-9 */ #define REG_MODE_CFG(pn) … #define REG_PAUSE_CFG(pn) … #define REG_NORMALIZER(pn) … #define REG_TBI_STATUS(pn) … #define REG_PCS_STATUS_DBG(pn) … #define REG_PCS_CTRL(pn) … #define REG_TBI_CONFIG(pn) … #define REG_STICK_BIT(pn) … #define REG_DEV_SETUP(pn) … #define REG_DROP_CNT(pn) … #define REG_PORT_POS(pn) … #define REG_PORT_FAIL(pn) … #define REG_SERDES_CONF(pn) … #define REG_SERDES_TEST(pn) … #define REG_SERDES_STAT(pn) … #define REG_SERDES_COM_CNT(pn) … #define REG_DENORM(pn) … #define REG_DBG(pn) … #define REG_TX_IFG(pn) … #define REG_HDX(pn) … /* Statistics */ /* CRA(0x4,pn,reg) */ /* reg below */ /* pn = port number, 0-a, a = 10GbE */ enum { … }; #define REG_RX_XGMII_PROT_ERR … #define REG_STAT_STICKY10G … #define REG_RX_OK_BYTES(pn) … #define REG_RX_BAD_BYTES(pn) … #define REG_TX_OK_BYTES(pn) … /* MII-Management Block registers */ /* These are for MII-M interface 0, which is the bidirectional LVTTL one. If * we hooked up to the one with separate directions, the middle 0x0 needs to * change to 0x1. And the current errata states that MII-M 1 doesn't work. */ #define REG_MIIM_STATUS … #define REG_MIIM_CMD … #define REG_MIIM_DATA … #define REG_MIIM_PRESCALE … #define REG_ING_FFILT_UM_EN … #define REG_ING_FFILT_BE_EN … #define REG_ING_FFILT_VAL0 … #define REG_ING_FFILT_VAL1 … #define REG_ING_FFILT_MASK0 … #define REG_ING_FFILT_MASK1 … #define REG_ING_FFILT_MASK2 … #define REG_ING_FFILT_ETYPE … /* Whew. */ #endif
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