/* * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include "common.h" #include "regs.h" enum { … }; /* DBGI command mode */ enum { … }; /* IDT 75P52100 commands */ #define IDT_CMD_READ … #define IDT_CMD_WRITE … #define IDT_CMD_SEARCH … #define IDT_CMD_LEARN … /* IDT LAR register address and value for 144-bit mode (low 32 bits) */ #define IDT_LAR_ADR0 … #define IDT_LAR_MODE144 … /* IDT SCR and SSR addresses (low 32 bits) */ #define IDT_SCR_ADR0 … #define IDT_SSR0_ADR0 … #define IDT_SSR1_ADR0 … /* IDT GMR base address (low 32 bits) */ #define IDT_GMR_BASE_ADR0 … /* IDT data and mask array base addresses (low 32 bits) */ #define IDT_DATARY_BASE_ADR0 … #define IDT_MSKARY_BASE_ADR0 … /* IDT 75N43102 commands */ #define IDT4_CMD_SEARCH144 … #define IDT4_CMD_WRITE … #define IDT4_CMD_READ … /* IDT 75N43102 SCR address (low 32 bits) */ #define IDT4_SCR_ADR0 … /* IDT 75N43102 GMR base addresses (low 32 bits) */ #define IDT4_GMR_BASE0 … #define IDT4_GMR_BASE1 … #define IDT4_GMR_BASE2 … /* IDT 75N43102 data and mask array base addresses (low 32 bits) */ #define IDT4_DATARY_BASE_ADR0 … #define IDT4_MSKARY_BASE_ADR0 … #define MAX_WRITE_ATTEMPTS … #define MAX_ROUTES … /* * Issue a command to the TCAM and wait for its completion. The address and * any data required by the command must have been setup by the caller. */ static int mc5_cmd_write(struct adapter *adapter, u32 cmd) { … } static inline void dbgi_wr_data3(struct adapter *adapter, u32 v1, u32 v2, u32 v3) { … } /* * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM * command cmd. The data to be written must have been set up by the caller. * Returns -1 on failure, 0 on success. */ static int mc5_write(struct adapter *adapter, u32 addr_lo, u32 cmd) { … } static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base, u32 data_array_base, u32 write_cmd, int addr_shift) { … } static int init_idt52100(struct mc5 *mc5) { … } static int init_idt43102(struct mc5 *mc5) { … } /* Put MC5 in DBGI mode. */ static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5) { … } /* Put MC5 in M-Bus mode. */ static void mc5_dbgi_mode_disable(const struct mc5 *mc5) { … } /* * Initialization that requires the OS and protocol layers to already * be initialized goes here. */ int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, unsigned int nroutes) { … } #define MC5_INT_FATAL … /* * MC5 interrupt handler */ void t3_mc5_intr_handler(struct mc5 *mc5) { … } void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode) { … }
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