/* * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include <linux/etherdevice.h> #include "common.h" #include "regs.h" #include "sge_defs.h" #include "firmware_exports.h" static void t3_port_intr_clear(struct adapter *adapter, int idx); /** * t3_wait_op_done_val - wait until an operation is completed * @adapter: the adapter performing the operation * @reg: the register to check for completion * @mask: a single-bit field within @reg that indicates completion * @polarity: the value of the field when the operation is completed * @attempts: number of check iterations * @delay: delay in usecs between iterations * @valp: where to store the value of the register at completion time * * Wait until an operation is completed by checking a bit in a register * up to @attempts times. If @valp is not NULL the value of the register * at the time it indicated completion is stored there. Returns 0 if the * operation completes and -EAGAIN otherwise. */ int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp) { … } /** * t3_write_regs - write a bunch of registers * @adapter: the adapter to program * @p: an array of register address/register value pairs * @n: the number of address/value pairs * @offset: register address offset * * Takes an array of register address/register value pairs and writes each * value to the corresponding register. Register addresses are adjusted * by the supplied offset. */ void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, int n, unsigned int offset) { … } /** * t3_set_reg_field - set a register field to a value * @adapter: the adapter to program * @addr: the register address * @mask: specifies the portion of the register to modify * @val: the new value for the register field * * Sets a register field specified by the supplied mask to the * given value. */ void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, u32 val) { … } /** * t3_read_indirect - read indirectly addressed registers * @adap: the adapter * @addr_reg: register holding the indirect address * @data_reg: register holding the value of the indirect register * @vals: where the read register values are stored * @start_idx: index of first indirect register to read * @nregs: how many indirect registers to read * * Reads registers that are accessed indirectly through an address/data * register pair. */ static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, u32 *vals, unsigned int nregs, unsigned int start_idx) { … } /** * t3_mc7_bd_read - read from MC7 through backdoor accesses * @mc7: identifies MC7 to read from * @start: index of first 64-bit word to read * @n: number of 64-bit words to read * @buf: where to store the read result * * Read n 64-bit words from MC7 starting at word start, using backdoor * accesses. */ int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, u64 *buf) { … } /* * Initialize MI1. */ static void mi1_init(struct adapter *adap, const struct adapter_info *ai) { … } #define MDIO_ATTEMPTS … /* * MI1 read/write operations for clause 22 PHYs. */ static int t3_mi1_read(struct net_device *dev, int phy_addr, int mmd_addr, u16 reg_addr) { … } static int t3_mi1_write(struct net_device *dev, int phy_addr, int mmd_addr, u16 reg_addr, u16 val) { … } static const struct mdio_ops mi1_mdio_ops = …; /* * Performs the address cycle for clause 45 PHYs. * Must be called with the MDIO_LOCK held. */ static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr, int reg_addr) { … } /* * MI1 read/write operations for indirect-addressed PHYs. */ static int mi1_ext_read(struct net_device *dev, int phy_addr, int mmd_addr, u16 reg_addr) { … } static int mi1_ext_write(struct net_device *dev, int phy_addr, int mmd_addr, u16 reg_addr, u16 val) { … } static const struct mdio_ops mi1_mdio_ext_ops = …; /** * t3_mdio_change_bits - modify the value of a PHY register * @phy: the PHY to operate on * @mmd: the device address * @reg: the register address * @clear: what part of the register value to mask off * @set: what part of the register value to set * * Changes the value of a PHY register by applying a mask to its current * value and ORing the result with a new value. */ int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, unsigned int set) { … } /** * t3_phy_reset - reset a PHY block * @phy: the PHY to operate on * @mmd: the device address of the PHY block to reset * @wait: how long to wait for the reset to complete in 1ms increments * * Resets a PHY block and optionally waits for the reset to complete. * @mmd should be 0 for 10/100/1000 PHYs and the device address to reset * for 10G PHYs. */ int t3_phy_reset(struct cphy *phy, int mmd, int wait) { … } /** * t3_phy_advertise - set the PHY advertisement registers for autoneg * @phy: the PHY to operate on * @advert: bitmap of capabilities the PHY should advertise * * Sets a 10/100/1000 PHY's advertisement registers to advertise the * requested capabilities. */ int t3_phy_advertise(struct cphy *phy, unsigned int advert) { … } /** * t3_phy_advertise_fiber - set fiber PHY advertisement register * @phy: the PHY to operate on * @advert: bitmap of capabilities the PHY should advertise * * Sets a fiber PHY's advertisement register to advertise the * requested capabilities. */ int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert) { … } /** * t3_set_phy_speed_duplex - force PHY speed and duplex * @phy: the PHY to operate on * @speed: requested PHY speed * @duplex: requested PHY duplex * * Force a 10/100/1000 PHY's speed and duplex. This also disables * auto-negotiation except for GigE, where auto-negotiation is mandatory. */ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex) { … } int t3_phy_lasi_intr_enable(struct cphy *phy) { … } int t3_phy_lasi_intr_disable(struct cphy *phy) { … } int t3_phy_lasi_intr_clear(struct cphy *phy) { … } int t3_phy_lasi_intr_handler(struct cphy *phy) { … } static const struct adapter_info t3_adap_info[] = …; /* * Return the adapter_info structure with a given index. Out-of-range indices * return NULL. */ const struct adapter_info *t3_get_adapter_info(unsigned int id) { … } struct port_type_info { … }; static const struct port_type_info port_types[] = …; #define VPD_ENTRY(name, len) … /* * Partial EEPROM Vital Product Data structure. Includes only the ID and * VPD-R sections. */ struct t3_vpd { … }; #define EEPROM_STAT_ADDR … #define VPD_BASE … /** * t3_seeprom_wp - enable/disable EEPROM write protection * @adapter: the adapter * @enable: 1 to enable write protection, 0 to disable it * * Enables or disables write protection on the serial EEPROM. */ int t3_seeprom_wp(struct adapter *adapter, int enable) { … } static int vpdstrtouint(char *s, u8 len, unsigned int base, unsigned int *val) { … } static int vpdstrtou16(char *s, u8 len, unsigned int base, u16 *val) { … } /** * get_vpd_params - read VPD parameters from VPD EEPROM * @adapter: adapter to read * @p: where to store the parameters * * Reads card parameters stored in VPD EEPROM. */ static int get_vpd_params(struct adapter *adapter, struct vpd_params *p) { … } /* serial flash and firmware constants */ enum { … }; /** * sf1_read - read data from the serial flash * @adapter: the adapter * @byte_cnt: number of bytes to read * @cont: whether another operation will be chained * @valp: where to store the read data * * Reads up to 4 bytes of data from the serial flash. The location of * the read needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash. */ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, u32 *valp) { … } /** * sf1_write - write data to the serial flash * @adapter: the adapter * @byte_cnt: number of bytes to write * @cont: whether another operation will be chained * @val: value to write * * Writes up to 4 bytes of data to the serial flash. The location of * the write needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash. */ static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, u32 val) { … } /** * flash_wait_op - wait for a flash operation to complete * @adapter: the adapter * @attempts: max number of polls of the status register * @delay: delay between polls in ms * * Wait for a flash operation to complete by polling the status register. */ static int flash_wait_op(struct adapter *adapter, int attempts, int delay) { … } /** * t3_read_flash - read words from serial flash * @adapter: the adapter * @addr: the start address for the read * @nwords: how many 32-bit words to read * @data: where to store the read data * @byte_oriented: whether to store data as bytes or as words * * Read the specified number of 32-bit words from the serial flash. * If @byte_oriented is set the read data is stored as a byte array * (i.e., big-endian), otherwise as 32-bit words in the platform's * natural endianness. */ static int t3_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented) { … } /** * t3_write_flash - write up to a page of data to the serial flash * @adapter: the adapter * @addr: the start address to write * @n: length of data to write * @data: the data to write * * Writes up to a page of data (256 bytes) to the serial flash starting * at the given address. */ static int t3_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, const u8 *data) { … } /** * t3_get_tp_version - read the tp sram version * @adapter: the adapter * @vers: where to place the version * * Reads the protocol sram version from sram. */ int t3_get_tp_version(struct adapter *adapter, u32 *vers) { … } /** * t3_check_tpsram_version - read the tp sram version * @adapter: the adapter * * Reads the protocol sram version from flash. */ int t3_check_tpsram_version(struct adapter *adapter) { … } /** * t3_check_tpsram - check if provided protocol SRAM * is compatible with this driver * @adapter: the adapter * @tp_sram: the firmware image to write * @size: image size * * Checks if an adapter's tp sram is compatible with the driver. * Returns 0 if the versions are compatible, a negative error otherwise. */ int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram, unsigned int size) { … } enum fw_version_type { … }; /** * t3_get_fw_version - read the firmware version * @adapter: the adapter * @vers: where to place the version * * Reads the FW version from flash. */ int t3_get_fw_version(struct adapter *adapter, u32 *vers) { … } /** * t3_check_fw_version - check if the FW is compatible with this driver * @adapter: the adapter * * Checks if an adapter's FW is compatible with the driver. Returns 0 * if the versions are compatible, a negative error otherwise. */ int t3_check_fw_version(struct adapter *adapter) { … } /** * t3_flash_erase_sectors - erase a range of flash sectors * @adapter: the adapter * @start: the first sector to erase * @end: the last sector to erase * * Erases the sectors in the given range. */ static int t3_flash_erase_sectors(struct adapter *adapter, int start, int end) { … } /** * t3_load_fw - download firmware * @adapter: the adapter * @fw_data: the firmware image to write * @size: image size * * Write the supplied firmware image to the card's serial flash. * The FW image has the following sections: @size - 8 bytes of code and * data, followed by 4 bytes of FW version, followed by the 32-bit * 1's complement checksum of the whole image. */ int t3_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size) { … } #define CIM_CTL_BASE … /** * t3_cim_ctl_blk_read - read a block from CIM control region * * @adap: the adapter * @addr: the start address within the CIM control region * @n: number of words to read * @valp: where to store the result * * Reads a block of 4-byte words from the CIM control region. */ int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp) { … } static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg, u32 *rx_hash_high, u32 *rx_hash_low) { … } static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg, u32 rx_hash_high, u32 rx_hash_low) { … } /** * t3_link_changed - handle interface link changes * @adapter: the adapter * @port_id: the port index that changed link state * * Called when a port's link settings change to propagate the new values * to the associated PHY and MAC. After performing the common tasks it * invokes an OS-specific handler. */ void t3_link_changed(struct adapter *adapter, int port_id) { … } void t3_link_fault(struct adapter *adapter, int port_id) { … } /** * t3_link_start - apply link configuration to MAC/PHY * @phy: the PHY to setup * @mac: the MAC to setup * @lc: the requested link configuration * * Set up a port's MAC and PHY according to a desired link configuration. * - If the PHY can auto-negotiate first decide what to advertise, then * enable/disable auto-negotiation as desired, and reset. * - If the PHY does not auto-negotiate just reset it. * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, * otherwise do it later based on the outcome of auto-negotiation. */ int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc) { … } /** * t3_set_vlan_accel - control HW VLAN extraction * @adapter: the adapter * @ports: bitmap of adapter ports to operate on * @on: enable (1) or disable (0) HW VLAN extraction * * Enables or disables HW extraction of VLAN tags for the given port. */ void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on) { … } struct intr_info { … }; /** * t3_handle_intr_status - table driven interrupt handler * @adapter: the adapter that generated the interrupt * @reg: the interrupt status register to process * @mask: a mask to apply to the interrupt status * @acts: table of interrupt actions * @stats: statistics counters tracking interrupt occurrences * * A table driven interrupt handler that applies a set of masks to an * interrupt status word and performs the corresponding actions if the * interrupts described by the mask have occurred. The actions include * optionally printing a warning or alert message, and optionally * incrementing a stat counter. The table is terminated by an entry * specifying mask 0. Returns the number of fatal interrupt conditions. */ static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, unsigned int mask, const struct intr_info *acts, unsigned long *stats) { … } #define SGE_INTR_MASK … #define MC5_INTR_MASK … #define MC7_INTR_MASK … #define XGM_INTR_MASK … #define PCIX_INTR_MASK … #define PCIE_INTR_MASK … #define ULPRX_INTR_MASK … #define ULPTX_INTR_MASK … #define CPLSW_INTR_MASK … #define CIM_INTR_MASK … #define PMTX_INTR_MASK … #define PMRX_INTR_MASK … #define MPS_INTR_MASK … #define XGM_EXTRA_INTR_MASK … #define PL_INTR_MASK … /* * Interrupt handler for the PCIX1 module. */ static void pci_intr_handler(struct adapter *adapter) { … } /* * Interrupt handler for the PCIE module. */ static void pcie_intr_handler(struct adapter *adapter) { … } /* * TP interrupt handler. */ static void tp_intr_handler(struct adapter *adapter) { … } /* * CIM interrupt handler. */ static void cim_intr_handler(struct adapter *adapter) { … } /* * ULP RX interrupt handler. */ static void ulprx_intr_handler(struct adapter *adapter) { … } /* * ULP TX interrupt handler. */ static void ulptx_intr_handler(struct adapter *adapter) { … } #define ICSPI_FRM_ERR … #define OESPI_FRM_ERR … /* * PM TX interrupt handler. */ static void pmtx_intr_handler(struct adapter *adapter) { … } #define IESPI_FRM_ERR … #define OCSPI_FRM_ERR … /* * PM RX interrupt handler. */ static void pmrx_intr_handler(struct adapter *adapter) { … } /* * CPL switch interrupt handler. */ static void cplsw_intr_handler(struct adapter *adapter) { … } /* * MPS interrupt handler. */ static void mps_intr_handler(struct adapter *adapter) { … } #define MC7_INTR_FATAL … /* * MC7 interrupt handler. */ static void mc7_intr_handler(struct mc7 *mc7) { … } #define XGM_INTR_FATAL … /* * XGMAC interrupt handler. */ static int mac_intr_handler(struct adapter *adap, unsigned int idx) { … } /* * Interrupt handler for PHY events. */ int t3_phy_intr_handler(struct adapter *adapter) { … } /* * T3 slow path (non-data) interrupt handler. */ int t3_slow_intr_handler(struct adapter *adapter) { … } static unsigned int calc_gpio_intr(struct adapter *adap) { … } /** * t3_intr_enable - enable interrupts * @adapter: the adapter whose interrupts should be enabled * * Enable interrupts by setting the interrupt enable registers of the * various HW modules and then enabling the top-level interrupt * concentrator. */ void t3_intr_enable(struct adapter *adapter) { … } /** * t3_intr_disable - disable a card's interrupts * @adapter: the adapter whose interrupts should be disabled * * Disable interrupts. We only disable the top-level interrupt * concentrator and the SGE data interrupts. */ void t3_intr_disable(struct adapter *adapter) { … } /** * t3_intr_clear - clear all interrupts * @adapter: the adapter whose interrupts should be cleared * * Clears all interrupts. */ void t3_intr_clear(struct adapter *adapter) { … } void t3_xgm_intr_enable(struct adapter *adapter, int idx) { … } void t3_xgm_intr_disable(struct adapter *adapter, int idx) { … } /** * t3_port_intr_enable - enable port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts should be enabled * * Enable port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ void t3_port_intr_enable(struct adapter *adapter, int idx) { … } /** * t3_port_intr_disable - disable port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts should be disabled * * Disable port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ void t3_port_intr_disable(struct adapter *adapter, int idx) { … } /** * t3_port_intr_clear - clear port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts to clear * * Clear port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ static void t3_port_intr_clear(struct adapter *adapter, int idx) { … } #define SG_CONTEXT_CMD_ATTEMPTS … /** * t3_sge_write_context - write an SGE context * @adapter: the adapter * @id: the context id * @type: the context type * * Program an SGE context with the values already loaded in the * CONTEXT_DATA? registers. */ static int t3_sge_write_context(struct adapter *adapter, unsigned int id, unsigned int type) { … } /** * clear_sge_ctxt - completely clear an SGE context * @adap: the adapter * @id: the context id * @type: the context type * * Completely clear an SGE context. Used predominantly at post-reset * initialization. Note in particular that we don't skip writing to any * "sensitive bits" in the contexts the way that t3_sge_write_context() * does ... */ static int clear_sge_ctxt(struct adapter *adap, unsigned int id, unsigned int type) { … } /** * t3_sge_init_ecntxt - initialize an SGE egress context * @adapter: the adapter to configure * @id: the context id * @gts_enable: whether to enable GTS for the context * @type: the egress context type * @respq: associated response queue * @base_addr: base address of queue * @size: number of queue entries * @token: uP token * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE egress context and make it ready for use. If the * platform allows concurrent context operations, the caller is * responsible for appropriate locking. */ int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, enum sge_context_type type, int respq, u64 base_addr, unsigned int size, unsigned int token, int gen, unsigned int cidx) { … } /** * t3_sge_init_flcntxt - initialize an SGE free-buffer list context * @adapter: the adapter to configure * @id: the context id * @gts_enable: whether to enable GTS for the context * @base_addr: base address of queue * @size: number of queue entries * @bsize: size of each buffer for this queue * @cong_thres: threshold to signal congestion to upstream producers * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE free list context and make it ready for use. The * caller is responsible for ensuring only one context operation occurs * at a time. */ int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, int gts_enable, u64 base_addr, unsigned int size, unsigned int bsize, unsigned int cong_thres, int gen, unsigned int cidx) { … } /** * t3_sge_init_rspcntxt - initialize an SGE response queue context * @adapter: the adapter to configure * @id: the context id * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ * @base_addr: base address of queue * @size: number of queue entries * @fl_thres: threshold for selecting the normal or jumbo free list * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE response queue context and make it ready for use. * The caller is responsible for ensuring only one context operation * occurs at a time. */ int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, int irq_vec_idx, u64 base_addr, unsigned int size, unsigned int fl_thres, int gen, unsigned int cidx) { … } /** * t3_sge_init_cqcntxt - initialize an SGE completion queue context * @adapter: the adapter to configure * @id: the context id * @base_addr: base address of queue * @size: number of queue entries * @rspq: response queue for async notifications * @ovfl_mode: CQ overflow mode * @credits: completion queue credits * @credit_thres: the credit threshold * * Initialize an SGE completion queue context and make it ready for use. * The caller is responsible for ensuring only one context operation * occurs at a time. */ int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, unsigned int size, int rspq, int ovfl_mode, unsigned int credits, unsigned int credit_thres) { … } /** * t3_sge_enable_ecntxt - enable/disable an SGE egress context * @adapter: the adapter * @id: the egress context id * @enable: enable (1) or disable (0) the context * * Enable or disable an SGE egress context. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable) { … } /** * t3_sge_disable_fl - disable an SGE free-buffer list * @adapter: the adapter * @id: the free list context id * * Disable an SGE free-buffer list. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_fl(struct adapter *adapter, unsigned int id) { … } /** * t3_sge_disable_rspcntxt - disable an SGE response queue * @adapter: the adapter * @id: the response queue context id * * Disable an SGE response queue. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id) { … } /** * t3_sge_disable_cqcntxt - disable an SGE completion queue * @adapter: the adapter * @id: the completion queue context id * * Disable an SGE completion queue. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id) { … } /** * t3_sge_cqcntxt_op - perform an operation on a completion queue context * @adapter: the adapter * @id: the context id * @op: the operation to perform * @credits: credit value to write * * Perform the selected operation on an SGE completion queue context. * The caller is responsible for ensuring only one context operation * occurs at a time. */ int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, unsigned int credits) { … } /** * t3_config_rss - configure Rx packet steering * @adapter: the adapter * @rss_config: RSS settings (written to TP_RSS_CONFIG) * @cpus: values for the CPU lookup table (0xff terminated) * @rspq: values for the response queue lookup table (0xffff terminated) * * Programs the receive packet steering logic. @cpus and @rspq provide * the values for the CPU and response queue lookup tables. If they * provide fewer values than the size of the tables the supplied values * are used repeatedly until the tables are fully populated. */ void t3_config_rss(struct adapter *adapter, unsigned int rss_config, const u8 * cpus, const u16 *rspq) { … } /** * t3_tp_set_offload_mode - put TP in NIC/offload mode * @adap: the adapter * @enable: 1 to select offload mode, 0 for regular NIC * * Switches TP to NIC/offload mode. */ void t3_tp_set_offload_mode(struct adapter *adap, int enable) { … } /** * pm_num_pages - calculate the number of pages of the payload memory * @mem_size: the size of the payload memory * @pg_size: the size of each payload memory page * * Calculate the number of pages, each of the given size, that fit in a * memory of the specified size, respecting the HW requirement that the * number of pages must be a multiple of 24. */ static inline unsigned int pm_num_pages(unsigned int mem_size, unsigned int pg_size) { … } #define mem_region(adap, start, size, reg) … /** * partition_mem - partition memory and configure TP memory settings * @adap: the adapter * @p: the TP parameters * * Partitions context and payload memory and configures TP's memory * registers. */ static void partition_mem(struct adapter *adap, const struct tp_params *p) { … } static inline void tp_wr_indirect(struct adapter *adap, unsigned int addr, u32 val) { … } static void tp_config(struct adapter *adap, const struct tp_params *p) { … } /* Desired TP timer resolution in usec */ #define TP_TMR_RES … /* TCP timer values in ms */ #define TP_DACK_TIMER … #define TP_RTO_MIN … /** * tp_set_timers - set TP timing parameters * @adap: the adapter to set * @core_clk: the core clock frequency in Hz * * Set TP's timing parameters, such as the various timer resolutions and * the TCP timer values. */ static void tp_set_timers(struct adapter *adap, unsigned int core_clk) { … } /** * t3_tp_set_coalescing_size - set receive coalescing size * @adap: the adapter * @size: the receive coalescing size * @psh: whether a set PSH bit should deliver coalesced data * * Set the receive coalescing size and PSH bit handling. */ static int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh) { … } /** * t3_tp_set_max_rxsize - set the max receive size * @adap: the adapter * @size: the max receive size * * Set TP's max receive size. This is the limit that applies when * receive coalescing is disabled. */ static void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size) { … } static void init_mtus(unsigned short mtus[]) { … } /* * Initial congestion control parameters. */ static void init_cong_ctrl(unsigned short *a, unsigned short *b) { … } /* The minimum additive increment value for the congestion control table */ #define CC_MIN_INCR … /** * t3_load_mtus - write the MTU and congestion control HW tables * @adap: the adapter * @mtus: the unrestricted values for the MTU table * @alpha: the values for the congestion control alpha parameter * @beta: the values for the congestion control beta parameter * @mtu_cap: the maximum permitted effective MTU * * Write the MTU table with the supplied MTUs capping each at &mtu_cap. * Update the high-speed congestion control table with the supplied alpha, * beta, and MTUs. */ void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], unsigned short alpha[NCCTRL_WIN], unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap) { … } /** * t3_tp_get_mib_stats - read TP's MIB counters * @adap: the adapter * @tps: holds the returned counter values * * Returns the values of TP's MIB counters. */ void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps) { … } #define ulp_region(adap, name, start, len) … #define ulptx_region(adap, name, start, len) … static void ulp_config(struct adapter *adap, const struct tp_params *p) { … } /** * t3_set_proto_sram - set the contents of the protocol sram * @adap: the adapter * @data: the protocol image * * Write the contents of the protocol SRAM. */ int t3_set_proto_sram(struct adapter *adap, const u8 *data) { … } void t3_config_trace_filter(struct adapter *adapter, const struct trace_params *tp, int filter_index, int invert, int enable) { … } /** * t3_config_sched - configure a HW traffic scheduler * @adap: the adapter * @kbps: target rate in Kbps * @sched: the scheduler index * * Configure a HW scheduler for the target rate */ int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched) { … } static int tp_init(struct adapter *adap, const struct tp_params *p) { … } /* * Perform the bits of HW initialization that are dependent on the Tx * channels being used. */ static void chan_init_hw(struct adapter *adap, unsigned int chan_map) { … } static int calibrate_xgm(struct adapter *adapter) { … } static void calibrate_xgm_t3b(struct adapter *adapter) { … } struct mc7_timing_params { … }; /* * Write a value to a register and check that the write completed. These * writes normally complete in a cycle or two, so one read should suffice. * The very first read exists to flush the posted write to the device. */ static int wrreg_wait(struct adapter *adapter, unsigned int addr, u32 val) { … } static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type) { … } static void config_pcie(struct adapter *adap) { … } /* * Initialize and configure T3 HW modules. This performs the * initialization steps that need to be done once after a card is reset. * MAC and PHY initialization is handled separarely whenever a port is enabled. * * fw_params are passed to FW and their value is platform dependent. Only the * top 8 bits are available for use, the rest must be 0. */ int t3_init_hw(struct adapter *adapter, u32 fw_params) { … } /** * get_pci_mode - determine a card's PCI mode * @adapter: the adapter * @p: where to store the PCI settings * * Determines a card's PCI mode and associated parameters, such as speed * and width. */ static void get_pci_mode(struct adapter *adapter, struct pci_params *p) { … } /** * init_link_config - initialize a link's SW state * @lc: structure holding the link state * @caps: information about the current card * * Initializes the SW state maintained for each link, including the link's * capabilities and default speed/duplex/flow-control/autonegotiation * settings. */ static void init_link_config(struct link_config *lc, unsigned int caps) { … } /** * mc7_calc_size - calculate MC7 memory size * @cfg: the MC7 configuration * * Calculates the size of an MC7 memory in bytes from the value of its * configuration register. */ static unsigned int mc7_calc_size(u32 cfg) { … } static void mc7_prep(struct adapter *adapter, struct mc7 *mc7, unsigned int base_addr, const char *name) { … } static void mac_prep(struct cmac *mac, struct adapter *adapter, int index) { … } static void early_hw_init(struct adapter *adapter, const struct adapter_info *ai) { … } /* * Reset the adapter. * Older PCIe cards lose their config space during reset, PCI-X * ones don't. */ int t3_reset_adapter(struct adapter *adapter) { … } static int init_parity(struct adapter *adap) { … } /* * Initialize adapter SW state for the various HW modules, set initial values * for some adapter tunables, take PHYs out of reset, and initialize the MDIO * interface. */ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, int reset) { … } void t3_led_ready(struct adapter *adapter) { … } int t3_replay_prep_adapter(struct adapter *adapter) { … }
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